With the use of common clock framework, CPUFreq driver on EXYNOS5250 now
requires a few changes in clocks.
Tested on Exynos5250 based Arndale board.
The patches are based on v3.10-rc1.
Tushar Behera (2):
clk: exynos5250: Update cpufreq related clocks for EXYNOS5250
clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clock
drivers/clk/samsung/clk-exynos5250.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--
1.7.9.5
cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot
currently pass the clock names through a device tree node. Instead, we
need to make them available through a global alias.
cpufreq driver for EXYNOS5250 requires four clocks - 'armclk',
'mout_cpu', 'mout_mpll' and 'mout_apll'.
'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll'
and 'mout_apll' are now defined with an alias.
Signed-off-by: Tushar Behera <[email protected]>
---
drivers/clk/samsung/clk-exynos5250.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 5c97e75..05d099d 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -208,10 +208,10 @@ struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = {
};
struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
- MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
- MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
+ MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"),
+ MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),
MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1),
- MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
+ MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),
MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),
MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1),
MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
--
1.7.9.5
'mout_mpll' is added the list of parent clocks for 'mout_cpu'.
'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll'
should be added to the list of parent clocks.
This results in an error when cpufreq driver for EXYNOS5250 tries to
set 'mout_mpll' as a parent for 'mout_cpu'.
clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu
Signed-off-by: Tushar Behera <[email protected]>
---
drivers/clk/samsung/clk-exynos5250.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 05d099d..b6d79c0 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -155,7 +155,7 @@ static __initdata unsigned long exynos5250_clk_regs[] = {
/* list of all parent clock list */
PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
-PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
+PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
--
1.7.9.5
On 05/17/2013 11:25 AM, Tushar Behera wrote:
> With the use of common clock framework, CPUFreq driver on EXYNOS5250 now
> requires a few changes in clocks.
>
> Tested on Exynos5250 based Arndale board.
> The patches are based on v3.10-rc1.
>
> Tushar Behera (2):
> clk: exynos5250: Update cpufreq related clocks for EXYNOS5250
> clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clock
>
> drivers/clk/samsung/clk-exynos5250.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
Any comments on this series?
--
Tushar Behera
Quoting Tushar Behera (2013-05-27 22:38:44)
> On 05/17/2013 11:25 AM, Tushar Behera wrote:
> > With the use of common clock framework, CPUFreq driver on EXYNOS5250 now
> > requires a few changes in clocks.
> >
> > Tested on Exynos5250 based Arndale board.
> > The patches are based on v3.10-rc1.
> >
> > Tushar Behera (2):
> > clk: exynos5250: Update cpufreq related clocks for EXYNOS5250
> > clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clock
> >
> > drivers/clk/samsung/clk-exynos5250.c | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
>
> Any comments on this series?
>
I've taken both patches into clk-next.
Regards,
Mike
> --
> Tushar Behera
On 05/30/2013 04:12 AM, Mike Turquette wrote:
> Quoting Tushar Behera (2013-05-27 22:38:44)
>> On 05/17/2013 11:25 AM, Tushar Behera wrote:
>>> With the use of common clock framework, CPUFreq driver on EXYNOS5250 now
>>> requires a few changes in clocks.
>>>
>>> Tested on Exynos5250 based Arndale board.
>>> The patches are based on v3.10-rc1.
>>>
>>> Tushar Behera (2):
>>> clk: exynos5250: Update cpufreq related clocks for EXYNOS5250
>>> clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clock
>>>
>>> drivers/clk/samsung/clk-exynos5250.c | 8 ++++----
>>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>>
>>
>> Any comments on this series?
>>
>
> I've taken both patches into clk-next.
>
Would it be possible for you to queue them for 3.10-rc? These two
patches are sufficient for cpufreq to work on Arndale board. It would be
nice to have cpufreq working on 3.10 kernel.
> Regards,
> Mike
>
>> --
>> Tushar Behera
--
Tushar Behera
>> Would it be possible for you to queue them for 3.10-rc? These two
>> patches are sufficient for cpufreq to work on Arndale board. It would be
>> nice to have cpufreq working on 3.10 kernel.
>>
>
> I only want to take bug fixes into the -rc's. Did cpufreq work on
> Arndale in v3.10? If it did then this is a regression and can be fixed.
> If this is a new feature however I'll keep the patches in clk-next.
>
This fixes a regression as cpufreq was working for EXYNOS5250 based
systems before migration to CCF.
Though Arndale support was added during 3.10, this holds good for other
EXYNOS5250 based systems.
--
Tushar Behera