This patch set comprises some DT updates and cleanup patches that
piled up in the past. The first patch adds a cpu node for the
Marvell Sheeva PJ4(A) CPU found on Dove SoCs. While touching the
dtsi, also some nodes are renamed to achieve a consitent naming
scheme. The second patch adds some common pinmux settings to
the SoC's pinctrl node and moves the default pinctrl properties to
the corresponding nodes. The third patch adds a node for the
IR diode connected to a GPIO pin on SolidRun CuBox. Finally,
the last patch adds an initial DT file for the Globalscale D2Plug
which is also based on Marvell Dove SoC.
The whole patch set is based on v3.11-rc2 with DT part of
mv643xx_eth and irqchip/clocksource patches applied.
Although this patches are Marvell Dove only, the whole set is also
sent to devicetree mailing list to raise attention for potential DT
binding review.
Sebastian Hesselbarth (4):
ARM: dove: add cpu device tree node
ARM: dove: add common pinmux functions to DT
ARM: dove: add GPIO IR receiver node to SolidRun CuBox
ARM: dove: add initial DT file for Globalscale D2Plug
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/dove-cubox.dts | 30 ++---
arch/arm/boot/dts/dove-d2plug.dts | 69 +++++++++++
arch/arm/boot/dts/dove.dtsi | 235 +++++++++++++++++++++++++++++++++----
4 files changed, 295 insertions(+), 40 deletions(-)
create mode 100644 arch/arm/boot/dts/dove-d2plug.dts
---
Cc: Russell King <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
--
1.7.10.4
This adds a node for the IR receiver connected to a GPIO pin on the
SolidRun CuBox.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: Russell King <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/dove-cubox.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 525fb45..022646e 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -55,6 +55,13 @@
clock-frequency = <25000000>;
};
};
+
+ ir_recv: ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio0 19 1>;
+ pinctrl-0 = <&pmx_gpio_19>;
+ pinctrl-names = "default";
+ };
};
&uart0 { status = "okay"; };
--
1.7.10.4
This adds a node for the Marvell Sheeva PJ4A CPU found on Dove SoCs.
While at it, also move the l2-cache node out of internal registers and
consistently name different nodes.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: Russell King <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/dove.dtsi | 52 ++++++++++++++++++++++++++-----------------
1 file changed, 32 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 8d5be1e8..09d9710 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -10,6 +10,23 @@
gpio2 = &gpio2;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "marvell,pj4a", "marvell,sheeva-v7";
+ device_type = "cpu";
+ next-level-cache = <&l2>;
+ reg = <0>;
+ };
+ };
+
+ l2: l2-cache {
+ compatible = "marvell,tauros2-cache";
+ marvell,tauros2-cache-features = <0>;
+ };
+
soc@f1000000 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -25,11 +42,6 @@
0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
- l2: l2-cache {
- compatible = "marvell,tauros2-cache";
- marvell,tauros2-cache-features = <0>;
- };
-
timer: timer@20300 {
compatible = "marvell,orion-timer";
reg = <0x20300 0x20>;
@@ -60,14 +72,14 @@
#clock-cells = <1>;
};
- gate_clk: clock-gating-control@d0038 {
+ gate_clk: clock-gating-ctrl@d0038 {
compatible = "marvell,dove-gating-clock";
reg = <0xd0038 0x4>;
clocks = <&core_clk 0>;
#clock-cells = <1>;
};
- thermal: thermal@d001c {
+ thermal: thermal-diode@d001c {
compatible = "marvell,dove-thermal";
reg = <0xd001c 0x0c>, <0xd005c 0x08>;
};
@@ -108,7 +120,7 @@
status = "disabled";
};
- gpio0: gpio@d0400 {
+ gpio0: gpio-ctrl@d0400 {
compatible = "marvell,orion-gpio";
#gpio-cells = <2>;
gpio-controller;
@@ -119,7 +131,7 @@
interrupts = <12>, <13>, <14>, <60>;
};
- gpio1: gpio@d0420 {
+ gpio1: gpio-ctrl@d0420 {
compatible = "marvell,orion-gpio";
#gpio-cells = <2>;
gpio-controller;
@@ -130,7 +142,7 @@
interrupts = <61>;
};
- gpio2: gpio@e8400 {
+ gpio2: gpio-ctrl@e8400 {
compatible = "marvell,orion-gpio";
#gpio-cells = <2>;
gpio-controller;
@@ -138,13 +150,13 @@
ngpios = <8>;
};
- pinctrl: pinctrl@d0200 {
+ pinctrl: pin-ctrl@d0200 {
compatible = "marvell,dove-pinctrl";
reg = <0xd0200 0x10>;
clocks = <&gate_clk 22>;
};
- spi0: spi@10600 {
+ spi0: spi-ctrl@10600 {
compatible = "marvell,orion-spi";
#address-cells = <1>;
#size-cells = <0>;
@@ -155,7 +167,7 @@
status = "disabled";
};
- spi1: spi@14600 {
+ spi1: spi-ctrl@14600 {
compatible = "marvell,orion-spi";
#address-cells = <1>;
#size-cells = <0>;
@@ -166,7 +178,7 @@
status = "disabled";
};
- i2c0: i2c@11000 {
+ i2c0: i2c-ctrl@11000 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
@@ -194,7 +206,7 @@
status = "okay";
};
- sdio0: sdio@92000 {
+ sdio0: sdio-host@92000 {
compatible = "marvell,dove-sdhci";
reg = <0x92000 0x100>;
interrupts = <35>, <37>;
@@ -202,7 +214,7 @@
status = "disabled";
};
- sdio1: sdio@90000 {
+ sdio1: sdio-host@90000 {
compatible = "marvell,dove-sdhci";
reg = <0x90000 0x100>;
interrupts = <36>, <38>;
@@ -210,7 +222,7 @@
status = "disabled";
};
- sata0: sata@a0000 {
+ sata0: sata-host@a0000 {
compatible = "marvell,orion-sata";
reg = <0xa0000 0x2400>;
interrupts = <62>;
@@ -219,12 +231,12 @@
status = "disabled";
};
- rtc@d8500 {
+ rtc: real-time-clock@d8500 {
compatible = "marvell,orion-rtc";
reg = <0xd8500 0x20>;
};
- crypto: crypto@30000 {
+ crypto: crypto-engine@30000 {
compatible = "marvell,orion-crypto";
reg = <0x30000 0x10000>,
<0xc8000000 0x800>;
@@ -291,7 +303,7 @@
};
};
- eth: ethernet-controller@72000 {
+ eth: ethernet-ctrl@72000 {
compatible = "marvell,orion-eth";
#address-cells = <1>;
#size-cells = <0>;
--
1.7.10.4
This adds common dedicated and gpio pinmux functions to SoC pinctrl
node. It also relocates pinctrl references to corresponding DT nodes.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: Russell King <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/dove-cubox.dts | 23 +----
arch/arm/boot/dts/dove.dtsi | 183 ++++++++++++++++++++++++++++++++++++++
2 files changed, 186 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 955188f..525fb45 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -42,6 +42,8 @@
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 1 0>;
+ pinctrl-0 = <&pmx_gpio_1>;
+ pinctrl-names = "default";
};
};
@@ -110,6 +112,7 @@
status = "okay";
/* sdio0 card detect is connected to wrong pin on CuBox */
cd-gpios = <&gpio0 12 1>;
+ pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>;
};
&spi0 {
@@ -122,23 +125,3 @@
reg = <0>;
};
};
-
-&pinctrl {
- pinctrl-0 = <&pmx_gpio_1 &pmx_gpio_12>;
- pinctrl-names = "default";
-
- pmx_gpio_1: pmx-gpio-1 {
- marvell,pins = "mpp1";
- marvell,function = "gpio";
- };
-
- pmx_gpio_12: pmx-gpio-12 {
- marvell,pins = "mpp12";
- marvell,function = "gpio";
- };
-
- pmx_gpio_18: pmx-gpio-18 {
- marvell,pins = "mpp18";
- marvell,function = "gpio";
- };
-};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 09d9710..90257c7 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -99,6 +99,8 @@
reg-shift = <2>;
interrupts = <8>;
clocks = <&core_clk 0>;
+ pinctrl-0 = <&pmx_uart1>;
+ pinctrl-names = "default";
status = "disabled";
};
@@ -154,6 +156,181 @@
compatible = "marvell,dove-pinctrl";
reg = <0xd0200 0x10>;
clocks = <&gate_clk 22>;
+
+ pmx_gpio_0: pmx-gpio-0 {
+ marvell,pins = "mpp0";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_1: pmx-gpio-1 {
+ marvell,pins = "mpp1";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_2: pmx-gpio-2 {
+ marvell,pins = "mpp2";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_3: pmx-gpio-3 {
+ marvell,pins = "mpp3";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_4: pmx-gpio-4 {
+ marvell,pins = "mpp4";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_5: pmx-gpio-5 {
+ marvell,pins = "mpp5";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_6: pmx-gpio-6 {
+ marvell,pins = "mpp6";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_7: pmx-gpio-7 {
+ marvell,pins = "mpp7";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_8: pmx-gpio-8 {
+ marvell,pins = "mpp8";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_9: pmx-gpio-9 {
+ marvell,pins = "mpp9";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_10: pmx-gpio-10 {
+ marvell,pins = "mpp10";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_11: pmx-gpio-11 {
+ marvell,pins = "mpp11";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_12: pmx-gpio-12 {
+ marvell,pins = "mpp12";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_13: pmx-gpio-13 {
+ marvell,pins = "mpp13";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_14: pmx-gpio-14 {
+ marvell,pins = "mpp14";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_15: pmx-gpio-15 {
+ marvell,pins = "mpp15";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_16: pmx-gpio-16 {
+ marvell,pins = "mpp16";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_17: pmx-gpio-17 {
+ marvell,pins = "mpp17";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_18: pmx-gpio-18 {
+ marvell,pins = "mpp18";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_19: pmx-gpio-19 {
+ marvell,pins = "mpp19";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_20: pmx-gpio-20 {
+ marvell,pins = "mpp20";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_21: pmx-gpio-21 {
+ marvell,pins = "mpp21";
+ marvell,function = "gpio";
+ };
+
+ pmx_camera: pmx-camera {
+ marvell,pins = "mpp_camera";
+ marvell,function = "camera";
+ };
+
+ pmx_camera_gpio: pmx-camera-gpio {
+ marvell,pins = "mpp_camera";
+ marvell,function = "gpio";
+ };
+
+ pmx_sdio0: pmx-sdio0 {
+ marvell,pins = "mpp_sdio0";
+ marvell,function = "sdio0";
+ };
+
+ pmx_sdio0_gpio: pmx-sdio0-gpio {
+ marvell,pins = "mpp_sdio0";
+ marvell,function = "gpio";
+ };
+
+ pmx_sdio1: pmx-sdio1 {
+ marvell,pins = "mpp_sdio1";
+ marvell,function = "sdio1";
+ };
+
+ pmx_sdio1_gpio: pmx-sdio1-gpio {
+ marvell,pins = "mpp_sdio1";
+ marvell,function = "gpio";
+ };
+
+ pmx_audio1_gpio: pmx-audio1-gpio {
+ marvell,pins = "mpp_audio1";
+ marvell,function = "gpio";
+ };
+
+ pmx_spi0: pmx-spi0 {
+ marvell,pins = "mpp_spi0";
+ marvell,function = "spi0";
+ };
+
+ pmx_spi0_gpio: pmx-spi0-gpio {
+ marvell,pins = "mpp_spi0";
+ marvell,function = "gpio";
+ };
+
+ pmx_uart1: pmx-uart1 {
+ marvell,pins = "mpp_uart1";
+ marvell,function = "uart1";
+ };
+
+ pmx_uart1_gpio: pmx-uart1-gpio {
+ marvell,pins = "mpp_uart1";
+ marvell,function = "gpio";
+ };
+
+ pmx_nand: pmx-nand {
+ marvell,pins = "mpp_nand";
+ marvell,function = "nand";
+ };
+
+ pmx_nand_gpo: pmx-nand-gpo {
+ marvell,pins = "mpp_nand";
+ marvell,function = "gpo";
+ };
};
spi0: spi-ctrl@10600 {
@@ -164,6 +341,8 @@
interrupts = <6>;
reg = <0x10600 0x28>;
clocks = <&core_clk 0>;
+ pinctrl-0 = <&pmx_spi0>;
+ pinctrl-names = "default";
status = "disabled";
};
@@ -211,6 +390,8 @@
reg = <0x92000 0x100>;
interrupts = <35>, <37>;
clocks = <&gate_clk 8>;
+ pinctrl-0 = <&pmx_sdio0>;
+ pinctrl-names = "default";
status = "disabled";
};
@@ -219,6 +400,8 @@
reg = <0x90000 0x100>;
interrupts = <36>, <38>;
clocks = <&gate_clk 9>;
+ pinctrl-0 = <&pmx_sdio1>;
+ pinctrl-names = "default";
status = "disabled";
};
--
1.7.10.4
This adds an initial DT file for the Globalscale D2Plug with Dove SoC.
Currently, one LED is missing and I have not been able to get SD8787 driver
working. Those will be taken care of later.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
---
Cc: Russell King <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Andrew Lunn <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/dove-d2plug.dts | 69 +++++++++++++++++++++++++++++++++++++
2 files changed, 70 insertions(+)
create mode 100644 arch/arm/boot/dts/dove-d2plug.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 641b3c9..6f10a07 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
da850-evm.dtb
dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
dove-cubox.dtb \
+ dove-d2plug.dtb \
dove-dove-db.dtb
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/dove-d2plug.dts
new file mode 100644
index 0000000..e2222ce
--- /dev/null
+++ b/arch/arm/boot/dts/dove-d2plug.dts
@@ -0,0 +1,69 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+ model = "Globalscale D2Plug";
+ compatible = "globalscale,d2plug", "marvell,dove";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>;
+ pinctrl-names = "default";
+
+ wlan-ap {
+ label = "wlan-ap";
+ gpios = <&gpio0 0 1>;
+ };
+
+ wlan-act {
+ label = "wlan-act";
+ gpios = <&gpio0 1 1>;
+ };
+
+ bluetooth-act {
+ label = "bt-act";
+ gpios = <&gpio0 2 1>;
+ };
+ };
+};
+
+&uart0 { status = "okay"; };
+&sata0 { status = "okay"; };
+&i2c0 { status = "okay"; };
+&mdio { status = "okay"; };
+ð { status = "okay"; };
+
+/* Samsung M8G2F eMMC */
+&sdio0 {
+ status = "okay";
+ non-removable;
+ bus-width = <4>;
+};
+
+/* Marvell SD8787 WLAN/BT */
+&sdio1 {
+ status = "okay";
+ non-removable;
+ bus-width = <4>;
+};
+
+&spi0 {
+ status = "okay";
+
+ /* spi0.0: 4M Flash Macronix MX25L3205D */
+ spi-flash@0 {
+ compatible = "st,m25l3205d";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
--
1.7.10.4
On 29/07/13 13:29, Sebastian Hesselbarth wrote:
> This adds a node for the Marvell Sheeva PJ4A CPU found on Dove SoCs.
> While at it, also move the l2-cache node out of internal registers and
> consistently name different nodes.
>
> Signed-off-by: Sebastian Hesselbarth <[email protected]>
> ---
> Cc: Russell King <[email protected]>
> Cc: Jason Cooper <[email protected]>
> Cc: Andrew Lunn <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> ---
> arch/arm/boot/dts/dove.dtsi | 52 ++++++++++++++++++++++++++-----------------
> 1 file changed, 32 insertions(+), 20 deletions(-)
>
> diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
> index 8d5be1e8..09d9710 100644
> --- a/arch/arm/boot/dts/dove.dtsi
> +++ b/arch/arm/boot/dts/dove.dtsi
> @@ -10,6 +10,23 @@
> gpio2 = &gpio2;
> };
>
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "marvell,pj4a", "marvell,sheeva-v7";
> + device_type = "cpu";
> + next-level-cache = <&l2>;
> + reg = <0>;
> + };
> + };
> +
> + l2: l2-cache {
> + compatible = "marvell,tauros2-cache";
> + marvell,tauros2-cache-features = <0>;
> + };
Hi Sebastian,
This is not entirely related to the patch but thought of checking with
you. I was trying to get info on L2 cache controller on Marvell SoCs,
mainly structure or way/set size. Is that something we can get
dynamically ? Some specification I referred said its integrated and some
said its separate(not unified). Basically I need information around
various L2 cache implementations(Tauros2/Feroceon) from Marvell.
Any pointers or contacts to get this information will be helpful.
Regards,
Sudeep
On 07/29/2013 02:41 PM, Sudeep KarkadaNagesha wrote:
> On 29/07/13 13:29, Sebastian Hesselbarth wrote:
>> This adds a node for the Marvell Sheeva PJ4A CPU found on Dove SoCs.
>> While at it, also move the l2-cache node out of internal registers and
>> consistently name different nodes.
>>
>> Signed-off-by: Sebastian Hesselbarth <[email protected]>
>> ---
>> Cc: Russell King <[email protected]>
>> Cc: Jason Cooper <[email protected]>
>> Cc: Andrew Lunn <[email protected]>
>> Cc: [email protected]
>> Cc: [email protected]
>> Cc: [email protected]
>> ---
>> arch/arm/boot/dts/dove.dtsi | 52 ++++++++++++++++++++++++++-----------------
>> 1 file changed, 32 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
>> index 8d5be1e8..09d9710 100644
>> --- a/arch/arm/boot/dts/dove.dtsi
>> +++ b/arch/arm/boot/dts/dove.dtsi
>> @@ -10,6 +10,23 @@
>> gpio2 = &gpio2;
>> };
>>
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu0: cpu@0 {
>> + compatible = "marvell,pj4a", "marvell,sheeva-v7";
>> + device_type = "cpu";
>> + next-level-cache = <&l2>;
>> + reg = <0>;
>> + };
>> + };
>> +
>> + l2: l2-cache {
>> + compatible = "marvell,tauros2-cache";
>> + marvell,tauros2-cache-features = <0>;
>> + };
> Hi Sebastian,
>
> This is not entirely related to the patch but thought of checking with
> you. I was trying to get info on L2 cache controller on Marvell SoCs,
> mainly structure or way/set size. Is that something we can get
> dynamically ? Some specification I referred said its integrated and some
> said its separate(not unified). Basically I need information around
> various L2 cache implementations(Tauros2/Feroceon) from Marvell.
>
> Any pointers or contacts to get this information will be helpful.
Sudeep,
I added Maen and Lior on Cc. Unfortunately, public Marvell SoC
datasheets only refer some closed Marvell datasheets when it comes
to CPU(s) used. Maybe they can help out.
Sebastian
On Mon, Jul 29, 2013 at 02:29:06PM +0200, Sebastian Hesselbarth wrote:
> This adds an initial DT file for the Globalscale D2Plug with Dove SoC.
> Currently, one LED is missing and I have not been able to get SD8787 driver
> working. Those will be taken care of later.
Hi Sebastion
I took a hard look at SDIO and failed to get it working when doing
DMA. Polled IO does however work. I guess we need some help from
Marvell engineers before we get stable SDIO with DMA.
Andrew
On 07/29/2013 08:45 PM, Andrew Lunn wrote:
> On Mon, Jul 29, 2013 at 02:29:06PM +0200, Sebastian Hesselbarth wrote:
>> This adds an initial DT file for the Globalscale D2Plug with Dove SoC.
>> Currently, one LED is missing and I have not been able to get SD8787 driver
>> working. Those will be taken care of later.
>
> I took a hard look at SDIO and failed to get it working when doing
> DMA. Polled IO does however work. I guess we need some help from
> Marvell engineers before we get stable SDIO with DMA.
Andrew,
have you tried this on the Dove D2Plug or any other Marvell SoC?
Dove is using a different SDHCI compatible SDIO controller.
Anyway, I haven't had a deep look into neither SDIO/SDHCI DMA nor
sd8787 driver.
Also, the DMA issue is not holding back this patch, is it?
Sebastian
On Tue, Jul 30, 2013 at 10:03:56AM +0200, Sebastian Hesselbarth wrote:
> On 07/29/2013 08:45 PM, Andrew Lunn wrote:
> >On Mon, Jul 29, 2013 at 02:29:06PM +0200, Sebastian Hesselbarth wrote:
> >>This adds an initial DT file for the Globalscale D2Plug with Dove SoC.
> >>Currently, one LED is missing and I have not been able to get SD8787 driver
> >>working. Those will be taken care of later.
> >
> >I took a hard look at SDIO and failed to get it working when doing
> >DMA. Polled IO does however work. I guess we need some help from
> >Marvell engineers before we get stable SDIO with DMA.
>
> Andrew,
>
> have you tried this on the Dove D2Plug or any other Marvell SoC?
Hi Sebastian
I only tried it on Kirkwood. I've had similar bug reports for 370,
which appears to shares the same IP core.
> Dove is using a different SDHCI compatible SDIO controller.
Ah, O.K. Didn't know. It will be interesting to see if this core has
the same problems, i.e. shares the same DMA engine as the MVSDIO core.
> Also, the DMA issue is not holding back this patch, is it?
No, not at all. I just wanted to point out, there are known problems
with the in kernel driver for MVSDIO.
Andrew
On Mon, Jul 29, 2013 at 02:29:02PM +0200, Sebastian Hesselbarth wrote:
> This patch set comprises some DT updates and cleanup patches that
> piled up in the past. The first patch adds a cpu node for the
> Marvell Sheeva PJ4(A) CPU found on Dove SoCs. While touching the
> dtsi, also some nodes are renamed to achieve a consitent naming
> scheme. The second patch adds some common pinmux settings to
> the SoC's pinctrl node and moves the default pinctrl properties to
> the corresponding nodes. The third patch adds a node for the
> IR diode connected to a GPIO pin on SolidRun CuBox. Finally,
> the last patch adds an initial DT file for the Globalscale D2Plug
> which is also based on Marvell Dove SoC.
>
> The whole patch set is based on v3.11-rc2 with DT part of
> mv643xx_eth and irqchip/clocksource patches applied.
>
> Although this patches are Marvell Dove only, the whole set is also
> sent to devicetree mailing list to raise attention for potential DT
> binding review.
>
> Sebastian Hesselbarth (4):
> ARM: dove: add cpu device tree node
> ARM: dove: add common pinmux functions to DT
> ARM: dove: add GPIO IR receiver node to SolidRun CuBox
> ARM: dove: add initial DT file for Globalscale D2Plug
>
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/dove-cubox.dts | 30 ++---
> arch/arm/boot/dts/dove-d2plug.dts | 69 +++++++++++
> arch/arm/boot/dts/dove.dtsi | 235 +++++++++++++++++++++++++++++++++----
> 4 files changed, 295 insertions(+), 40 deletions(-)
> create mode 100644 arch/arm/boot/dts/dove-d2plug.dts
Whole series applied to mvebu/boards.
thx,
Jason.