The Latest AMD NAVI GPU card has an integrated Type-C controller and
Designware I2C with PCI Interface. The Type-C controller can be
accessed over I2C. The client driver is part of the USB Type-C UCSI
driver.
Also, there exists a couple of notable IP limitations that are dealt as
workarounds:
- I2C transaction work on a polling mode as IP does not generate
interrupt.
- I2C read command sent twice to address the IP issues.
Reviewed-by: Shyam Sundar S K <[email protected]>
Co-developed-by: Nehal Bakulchandra Shah <[email protected]>
Signed-off-by: Nehal Bakulchandra Shah <[email protected]>
Signed-off-by: Sanket Goswami <[email protected]>
---
Changes in v2:
- Utilized existing functionality of i2c_dw_xfer_init to configure I2C
bus.
- Removed i2c_dw_populate_client and rewrrient navi_amd_register_client
to deduplicate from existing drivers.
- Addressed review comments from Andy.
drivers/i2c/busses/i2c-designware-common.c | 3 +
drivers/i2c/busses/i2c-designware-core.h | 3 +
drivers/i2c/busses/i2c-designware-master.c | 136 +++++++++++++++++++++
drivers/i2c/busses/i2c-designware-pcidrv.c | 57 +++++++++
4 files changed, 199 insertions(+)
diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c
index 3c19aada4b30..50883a70b482 100644
--- a/drivers/i2c/busses/i2c-designware-common.c
+++ b/drivers/i2c/busses/i2c-designware-common.c
@@ -150,6 +150,9 @@ int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
reg = readl(dev->base + DW_IC_COMP_TYPE);
i2c_dw_release_lock(dev);
+ if (dev->flags & AMD_NON_INTR_MODE)
+ map_cfg.max_register = AMD_UCSI_INTR_REG;
+
if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
map_cfg.reg_read = dw_reg_read_swab;
map_cfg.reg_write = dw_reg_write_swab;
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index 5392b82f68a4..f29923c452ac 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -293,9 +293,12 @@ struct dw_i2c_dev {
#define ACCESS_INTR_MASK BIT(0)
#define ACCESS_NO_IRQ_SUSPEND BIT(1)
+#define AMD_NON_INTR_MODE BIT(2)
#define MODEL_MSCC_OCELOT BIT(8)
#define MODEL_BAIKAL_BT1 BIT(9)
#define MODEL_MASK GENMASK(11, 8)
+#define AMD_UCSI_INTR_EN 0xd
+#define AMD_UCSI_INTR_REG 0x474
int i2c_dw_init_regmap(struct dw_i2c_dev *dev);
u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset);
diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c
index dd27b9dbe931..a76e1f992850 100644
--- a/drivers/i2c/busses/i2c-designware-master.c
+++ b/drivers/i2c/busses/i2c-designware-master.c
@@ -23,6 +23,10 @@
#include "i2c-designware-core.h"
+#define AMD_TIMEOUT_MIN_MSEC 10000
+#define AMD_TIMEOUT_MAX_MSEC 11000
+#define AMD_MASTERCFG_MASK GENMASK(15, 0)
+
static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
{
/* Configure Tx/Rx FIFO threshold levels */
@@ -208,6 +212,13 @@ static int i2c_dw_init_master(struct dw_i2c_dev *dev)
if (dev->sda_hold_time)
regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
+ /*
+ * In order to enable the interrupt for UCSI i.e. AMD NAVI GPU card,
+ * it is mandatory to set the right value in specific register
+ * (offset:0x474) as per the hardware IP specification.
+ */
+ if (dev->flags & AMD_NON_INTR_MODE)
+ regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN);
i2c_dw_configure_fifo_master(dev);
i2c_dw_release_lock(dev);
@@ -259,6 +270,121 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK);
}
+static int i2c_dw_check_stopbit(struct dw_i2c_dev *i2cd)
+{
+ u32 val;
+ int ret;
+
+ ret = regmap_read_poll_timeout(i2cd->map, DW_IC_INTR_STAT, val,
+ !(val & DW_IC_INTR_STOP_DET),
+ 1100, 20000);
+ if (ret) {
+ dev_err(i2cd->dev, "i2c timeout error %d\n", ret);
+ return -ETIMEDOUT;
+ }
+
+ regmap_read(i2cd->map, DW_IC_CLR_INTR, &val);
+ if (val & DW_IC_INTR_STOP_DET)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int i2c_dw_status(struct dw_i2c_dev *i2cd)
+{
+ int status;
+
+ status = i2c_dw_wait_bus_not_busy(i2cd);
+ if (status)
+ return -ETIMEDOUT;
+
+ return i2c_dw_check_stopbit(i2cd);
+}
+
+/*
+ * Initiate and continue master read/write transaction with polling
+ * based transfer routine afterward write messages into the tx buffer.
+ */
+static int amd_i2c_dw_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num_msgs)
+{
+ struct dw_i2c_dev *i2cd = i2c_get_adapdata(adap);
+ int msg_wrt_idx, msg_itr_lmt, buf_len, data_idx;
+ int cmd = 0, ret, status;
+ u8 *tx_buf;
+ u32 val;
+
+ ret = i2c_dw_acquire_lock(i2cd);
+ if (ret) {
+ dev_err(i2cd->dev, "Failed to get bus ownership\n");
+ return ret;
+ }
+
+ i2cd->msgs = msgs;
+ i2cd->msgs_num = num_msgs;
+ i2c_dw_xfer_init(i2cd);
+ i2c_dw_disable_int(i2cd);
+
+ /* Initiate messages read/write transaction */
+ for (msg_wrt_idx = 0; msg_wrt_idx < num_msgs; msg_wrt_idx++) {
+ tx_buf = msgs[msg_wrt_idx].buf;
+ buf_len = msgs[msg_wrt_idx].len;
+
+ if (!(msgs[msg_wrt_idx].flags & I2C_M_RD))
+ regmap_write(i2cd->map, DW_IC_TX_TL, buf_len - 1);
+ /*
+ * Initiate the i2c read/write transaction of buffer length,
+ * and poll for bus busy status. For the last message transfer,
+ * update the command with stopbit enable.
+ */
+ for (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) {
+ if (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1)
+ cmd |= BIT(9);
+
+ if (msgs[msg_wrt_idx].flags & I2C_M_RD) {
+ /* Due to hardware bug, need to write the same command twice. */
+ regmap_write(i2cd->map, DW_IC_DATA_CMD, 0x100);
+ regmap_write(i2cd->map, DW_IC_DATA_CMD, 0x100 | cmd);
+ if (cmd) {
+ regmap_write(i2cd->map, DW_IC_TX_TL, 2 * (buf_len - 1));
+ regmap_write(i2cd->map, DW_IC_RX_TL, 2 * (buf_len - 1));
+ /*
+ * Need to check the stop bit. However, it cannot be
+ * detected from the registers so we check it always
+ * when read/write the last byte.
+ */
+ status = i2c_dw_status(i2cd);
+ if (status) {
+ ret = -ETIMEDOUT;
+ goto lock_release;
+ }
+ for (data_idx = 0; data_idx < buf_len; data_idx++) {
+ regmap_read(i2cd->map, DW_IC_DATA_CMD, &val);
+ tx_buf[data_idx] = val;
+ }
+ status = i2c_dw_check_stopbit(i2cd);
+ if (status) {
+ ret = -ETIMEDOUT;
+ goto lock_release;
+ }
+ }
+ } else {
+ regmap_write(i2cd->map, DW_IC_DATA_CMD, *tx_buf++ | cmd);
+ usleep_range(AMD_TIMEOUT_MIN_MSEC, AMD_TIMEOUT_MAX_MSEC);
+ }
+ }
+ status = i2c_dw_check_stopbit(i2cd);
+ if (status) {
+ ret = -ETIMEDOUT;
+ goto lock_release;
+ }
+ }
+
+lock_release:
+ i2c_dw_release_lock(i2cd);
+
+ return ret;
+}
+
/*
* Initiate (and continue) low level master read/write transaction.
* This function is only called from i2c_dw_isr, and pumping i2c_msg
@@ -461,6 +587,13 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
pm_runtime_get_sync(dev->dev);
+ /*
+ * Initiate I2C message transfer when AMD NAVI GPU card is enabled,
+ * As it is polling based transfer mechanism, which does not support
+ * interrupt based functionalities of existing DesignWare driver.
+ */
+ if (dev->flags & AMD_NON_INTR_MODE)
+ return amd_i2c_dw_master_xfer(adap, msgs, num);
if (dev_WARN_ONCE(dev->dev, dev->suspended, "Transfer while suspended\n")) {
ret = -ESHUTDOWN;
@@ -774,6 +907,9 @@ int i2c_dw_probe_master(struct dw_i2c_dev *dev)
adap->dev.parent = dev->dev;
i2c_set_adapdata(adap, dev);
+ if (dev->flags & AMD_NON_INTR_MODE)
+ return i2c_add_numbered_adapter(adap);
+
if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
irq_flags = IRQF_NO_SUSPEND;
} else {
diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index 55c83a7a24f3..9673e8d52eee 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -26,6 +26,7 @@
#include "i2c-designware-core.h"
#define DRIVER_NAME "i2c-designware-pci"
+#define AMD_CLK_RATE_HZ 100000
enum dw_pci_ctl_id_t {
medfield,
@@ -34,6 +35,7 @@ enum dw_pci_ctl_id_t {
cherrytrail,
haswell,
elkhartlake,
+ navi_amd,
};
struct dw_scl_sda_cfg {
@@ -78,11 +80,23 @@ static struct dw_scl_sda_cfg hsw_config = {
.sda_hold = 0x9,
};
+/* NAVI-AMD HCNT/LCNT/SDA hold time */
+static struct dw_scl_sda_cfg navi_amd_config = {
+ .ss_hcnt = 0x1ae,
+ .ss_lcnt = 0x23a,
+ .sda_hold = 0x9,
+};
+
static u32 mfld_get_clk_rate_khz(struct dw_i2c_dev *dev)
{
return 25000;
}
+static u32 navi_amd_get_clk_rate_khz(struct dw_i2c_dev *dev)
+{
+ return AMD_CLK_RATE_HZ;
+}
+
static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
{
struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev);
@@ -104,6 +118,31 @@ static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
return -ENODEV;
}
+static int navi_amd_register_client(struct dw_i2c_dev *i2cd)
+{
+ struct i2c_board_info info;
+
+ memset(&info, 0, sizeof(struct i2c_board_info));
+ strscpy(info.type, "ccgx-ucsi", I2C_NAME_SIZE);
+ info.addr = 0x08;
+ info.irq = i2cd->irq;
+
+ i2cd->slave = i2c_new_client_device(&i2cd->adapter, &info);
+ if (!i2cd->slave)
+ return -ENODEV;
+
+ return 0;
+}
+
+static int navi_amd_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
+{
+ struct dw_i2c_dev *dev = dev_get_drvdata(&pdev->dev);
+
+ dev->flags |= AMD_NON_INTR_MODE;
+ dev->timings.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
+ return 0;
+}
+
static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
{
/*
@@ -155,6 +194,12 @@ static struct dw_pci_controller dw_pci_controllers[] = {
.bus_num = -1,
.get_clk_rate_khz = ehl_get_clk_rate_khz,
},
+ [navi_amd] = {
+ .bus_num = -1,
+ .scl_sda_cfg = &navi_amd_config,
+ .setup = navi_amd_setup,
+ .get_clk_rate_khz = navi_amd_get_clk_rate_khz,
+ },
};
#ifdef CONFIG_PM
@@ -274,6 +319,14 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
return r;
}
+ if (dev->flags & AMD_NON_INTR_MODE)
+ r = navi_amd_register_client(dev);
+
+ if (r) {
+ dev_err(dev->dev, "register client failed with %d\n", r);
+ return r;
+ }
+
pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
@@ -337,6 +390,10 @@ static const struct pci_device_id i2_designware_pci_ids[] = {
{ PCI_VDEVICE(INTEL, 0x4bbe), elkhartlake },
{ PCI_VDEVICE(INTEL, 0x4bbf), elkhartlake },
{ PCI_VDEVICE(INTEL, 0x4bc0), elkhartlake },
+ { PCI_VDEVICE(ATI, 0x7314), navi_amd },
+ { PCI_VDEVICE(ATI, 0x73a4), navi_amd },
+ { PCI_VDEVICE(ATI, 0x73e4), navi_amd },
+ { PCI_VDEVICE(ATI, 0x73c4), navi_amd },
{ 0,}
};
MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
--
2.25.1
Hi
On 3/22/21 6:59 PM, Sanket Goswami wrote:
> The Latest AMD NAVI GPU card has an integrated Type-C controller and
> Designware I2C with PCI Interface. The Type-C controller can be
> accessed over I2C. The client driver is part of the USB Type-C UCSI
> driver.
>
> Also, there exists a couple of notable IP limitations that are dealt as
> workarounds:
> - I2C transaction work on a polling mode as IP does not generate
> interrupt.
> - I2C read command sent twice to address the IP issues.
>
> Reviewed-by: Shyam Sundar S K <[email protected]>
> Co-developed-by: Nehal Bakulchandra Shah <[email protected]>
> Signed-off-by: Nehal Bakulchandra Shah <[email protected]>
> Signed-off-by: Sanket Goswami <[email protected]>
> ---
> Changes in v2:
> - Utilized existing functionality of i2c_dw_xfer_init to configure I2C
> bus.
> - Removed i2c_dw_populate_client and rewrrient navi_amd_register_client
> to deduplicate from existing drivers.
> - Addressed review comments from Andy.
>
> drivers/i2c/busses/i2c-designware-common.c | 3 +
> drivers/i2c/busses/i2c-designware-core.h | 3 +
> drivers/i2c/busses/i2c-designware-master.c | 136 +++++++++++++++++++++
> drivers/i2c/busses/i2c-designware-pcidrv.c | 57 +++++++++
> 4 files changed, 199 insertions(+)
>
> diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c
> index 3c19aada4b30..50883a70b482 100644
> --- a/drivers/i2c/busses/i2c-designware-common.c
> +++ b/drivers/i2c/busses/i2c-designware-common.c
> @@ -150,6 +150,9 @@ int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
> reg = readl(dev->base + DW_IC_COMP_TYPE);
> i2c_dw_release_lock(dev);
>
> + if (dev->flags & AMD_NON_INTR_MODE)
> + map_cfg.max_register = AMD_UCSI_INTR_REG;
> +
> if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
> map_cfg.reg_read = dw_reg_read_swab;
> map_cfg.reg_write = dw_reg_write_swab;
> diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
> index 5392b82f68a4..f29923c452ac 100644
> --- a/drivers/i2c/busses/i2c-designware-core.h
> +++ b/drivers/i2c/busses/i2c-designware-core.h
> @@ -293,9 +293,12 @@ struct dw_i2c_dev {
> #define ACCESS_INTR_MASK BIT(0)
> #define ACCESS_NO_IRQ_SUSPEND BIT(1)
>
> +#define AMD_NON_INTR_MODE BIT(2)
> #define MODEL_MSCC_OCELOT BIT(8)
> #define MODEL_BAIKAL_BT1 BIT(9)
> #define MODEL_MASK GENMASK(11, 8)
> +#define AMD_UCSI_INTR_EN 0xd
> +#define AMD_UCSI_INTR_REG 0x474
>
> int i2c_dw_init_regmap(struct dw_i2c_dev *dev);
> u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset);
> diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c
> index dd27b9dbe931..a76e1f992850 100644
> --- a/drivers/i2c/busses/i2c-designware-master.c
> +++ b/drivers/i2c/busses/i2c-designware-master.c
> @@ -23,6 +23,10 @@
>
> #include "i2c-designware-core.h"
>
> +#define AMD_TIMEOUT_MIN_MSEC 10000
> +#define AMD_TIMEOUT_MAX_MSEC 11000
> +#define AMD_MASTERCFG_MASK GENMASK(15, 0)
> +
> static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
> {
> /* Configure Tx/Rx FIFO threshold levels */
> @@ -208,6 +212,13 @@ static int i2c_dw_init_master(struct dw_i2c_dev *dev)
> if (dev->sda_hold_time)
> regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
>
> + /*
> + * In order to enable the interrupt for UCSI i.e. AMD NAVI GPU card,
> + * it is mandatory to set the right value in specific register
> + * (offset:0x474) as per the hardware IP specification.
> + */
> + if (dev->flags & AMD_NON_INTR_MODE)
> + regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN);
This confuses me - this patch is about adding support for DesignWare IP
that does not generate interrupts but here code is enabling an
interrupt. I guess it's for UCSI but should above code then go to a
driver handling that IP?
> +static int i2c_dw_check_stopbit(struct dw_i2c_dev *i2cd)
...
> +static int i2c_dw_status(struct dw_i2c_dev *i2cd)
...
> +static int amd_i2c_dw_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num_msgs)
...
> +{
> + struct dw_i2c_dev *i2cd = i2c_get_adapdata(adap);
For uniformity I'd use struct dw_i2c_dev *dev name instead of *i2cd
since that what driver uses currently in other places.
> @@ -461,6 +587,13 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
> dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
>
> pm_runtime_get_sync(dev->dev);
> + /*
> + * Initiate I2C message transfer when AMD NAVI GPU card is enabled,
> + * As it is polling based transfer mechanism, which does not support
> + * interrupt based functionalities of existing DesignWare driver.
> + */
> + if (dev->flags & AMD_NON_INTR_MODE)
> + return amd_i2c_dw_master_xfer(adap, msgs, num);
>
Does runtime PM go out of sync here?
Jarkko
Hi Jarkko,
On 23-Mar-21 19:40, Jarkko Nikula wrote:
> [CAUTION: External Email]
>
> Hi
>
> On 3/22/21 6:59 PM, Sanket Goswami wrote:
>> The Latest AMD NAVI GPU card has an integrated Type-C controller and
>> Designware I2C with PCI Interface. The Type-C controller can be
>> accessed over I2C. The client driver is part of the USB Type-C UCSI
>> driver.
>>
>> Also, there exists a couple of notable IP limitations that are dealt as
>> workarounds:
>> - I2C transaction work on a polling mode as IP does not generate
>> interrupt.
>> - I2C read command sent twice to address the IP issues.
>>
>> Reviewed-by: Shyam Sundar S K <[email protected]>
>> Co-developed-by: Nehal Bakulchandra Shah <[email protected]>
>> Signed-off-by: Nehal Bakulchandra Shah <[email protected]>
>> Signed-off-by: Sanket Goswami <[email protected]>
>> ---
>> Changes in v2:
>> - Utilized existing functionality of i2c_dw_xfer_init to configure I2C
>> bus.
>> - Removed i2c_dw_populate_client and rewrrient navi_amd_register_client
>> to deduplicate from existing drivers.
>> - Addressed review comments from Andy.
>>
>> drivers/i2c/busses/i2c-designware-common.c | 3 +
>> drivers/i2c/busses/i2c-designware-core.h | 3 +
>> drivers/i2c/busses/i2c-designware-master.c | 136 +++++++++++++++++++++
>> drivers/i2c/busses/i2c-designware-pcidrv.c | 57 +++++++++
>> 4 files changed, 199 insertions(+)
>>
>> diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c
>> index 3c19aada4b30..50883a70b482 100644
>> --- a/drivers/i2c/busses/i2c-designware-common.c
>> +++ b/drivers/i2c/busses/i2c-designware-common.c
>> @@ -150,6 +150,9 @@ int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
>> reg = readl(dev->base + DW_IC_COMP_TYPE);
>> i2c_dw_release_lock(dev);
>>
>> + if (dev->flags & AMD_NON_INTR_MODE)
>> + map_cfg.max_register = AMD_UCSI_INTR_REG;
>> +
>> if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
>> map_cfg.reg_read = dw_reg_read_swab;
>> map_cfg.reg_write = dw_reg_write_swab;
>> diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
>> index 5392b82f68a4..f29923c452ac 100644
>> --- a/drivers/i2c/busses/i2c-designware-core.h
>> +++ b/drivers/i2c/busses/i2c-designware-core.h
>> @@ -293,9 +293,12 @@ struct dw_i2c_dev {
>> #define ACCESS_INTR_MASK BIT(0)
>> #define ACCESS_NO_IRQ_SUSPEND BIT(1)
>>
>> +#define AMD_NON_INTR_MODE BIT(2)
>> #define MODEL_MSCC_OCELOT BIT(8)
>> #define MODEL_BAIKAL_BT1 BIT(9)
>> #define MODEL_MASK GENMASK(11, 8)
>> +#define AMD_UCSI_INTR_EN 0xd
>> +#define AMD_UCSI_INTR_REG 0x474
>>
>> int i2c_dw_init_regmap(struct dw_i2c_dev *dev);
>> u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset);
>> diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c
>> index dd27b9dbe931..a76e1f992850 100644
>> --- a/drivers/i2c/busses/i2c-designware-master.c
>> +++ b/drivers/i2c/busses/i2c-designware-master.c
>> @@ -23,6 +23,10 @@
>>
>> #include "i2c-designware-core.h"
>>
>> +#define AMD_TIMEOUT_MIN_MSEC 10000
>> +#define AMD_TIMEOUT_MAX_MSEC 11000
>> +#define AMD_MASTERCFG_MASK GENMASK(15, 0)
>> +
>> static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
>> {
>> /* Configure Tx/Rx FIFO threshold levels */
>> @@ -208,6 +212,13 @@ static int i2c_dw_init_master(struct dw_i2c_dev *dev)
>> if (dev->sda_hold_time)
>> regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
>>
>> + /*
>> + * In order to enable the interrupt for UCSI i.e. AMD NAVI GPU card,
>> + * it is mandatory to set the right value in specific register
>> + * (offset:0x474) as per the hardware IP specification.
>> + */
>> + if (dev->flags & AMD_NON_INTR_MODE)
>> + regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN);
>
> This confuses me - this patch is about adding support for DesignWare IP
> that does not generate interrupts but here code is enabling an
> interrupt. I guess it's for UCSI but should above code then go to a
> driver handling that IP?
That's true, This patch is regarding DesignWare IP. However, interrupt enablement for
UCSI has to be performed from the I2C master driver as AMD_UCSI_INTR_REG is part of this
DesignWare IP specification. Hence, we feel this should not be part of the UCSI driver.
Please suggest if you have any alternate thoughts.
>
>> +static int i2c_dw_check_stopbit(struct dw_i2c_dev *i2cd)
> ...
>> +static int i2c_dw_status(struct dw_i2c_dev *i2cd)
> ...
>> +static int amd_i2c_dw_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num_msgs)
> ...
>> +{
>> + struct dw_i2c_dev *i2cd = i2c_get_adapdata(adap);
>
> For uniformity I'd use struct dw_i2c_dev *dev name instead of *i2cd
> since that what driver uses currently in other places.
Got your point, it will be addressed in v3.
>
>> @@ -461,6 +587,13 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
>> dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
>>
>> pm_runtime_get_sync(dev->dev);
>> + /*
>> + * Initiate I2C message transfer when AMD NAVI GPU card is enabled,
>> + * As it is polling based transfer mechanism, which does not support
>> + * interrupt based functionalities of existing DesignWare driver.
>> + */
>> + if (dev->flags & AMD_NON_INTR_MODE)
>> + return amd_i2c_dw_master_xfer(adap, msgs, num);
>>
> Does runtime PM go out of sync here?
Thanks for pointing out this, It will be also addressed in v3.
>
> Jarkko
Thanks,
Sanket