This patch control special clock for ADC in Exynos series's FSYS block.
If special clock of ADC is registerd on clock list of common clk framework,
Exynos ADC drvier have to control this clock.
Exynos3250/Exynos4/Exynos5 has 'adc' clock as following:
- 'adc' clock: bus clock for ADC
Exynos3250 has additional 'sclk_tsadc' clock as following:
- 'sclk_tsadc' clock: special clock for ADC which provide clock to internal ADC
Exynos 4210/4212/4412 and Exynos5250/5420 has not included 'sclk_tsadc' clock
in FSYS_BLK. But, Exynos3250 based on Cortex-A7 has only included 'sclk_tsadc'
clock in FSYS_BLK.
Cc: Jonathan Cameron <[email protected]>
Cc: Kukjin Kim <[email protected]>
Cc: Naveen Krishna Chatradhi <[email protected]>
Cc: [email protected]
Signed-off-by: Chanwoo Choi <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
---
drivers/iio/adc/exynos_adc.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index d25b262..4cd1975 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -88,6 +88,7 @@ struct exynos_adc {
void __iomem *regs;
void __iomem *enable_reg;
struct clk *clk;
+ struct clk *sclk;
unsigned int irq;
struct regulator *vdd;
@@ -308,6 +309,13 @@ static int exynos_adc_probe(struct platform_device *pdev)
goto err_irq;
}
+ info->sclk = devm_clk_get(&pdev->dev, "sclk_tsadc");
+ if (IS_ERR(info->sclk)) {
+ dev_warn(&pdev->dev, "failed getting sclk clock, err = %ld\n",
+ PTR_ERR(info->sclk));
+ info->sclk = NULL;
+ }
+
info->vdd = devm_regulator_get(&pdev->dev, "vdd");
if (IS_ERR(info->vdd)) {
dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
@@ -341,6 +349,7 @@ static int exynos_adc_probe(struct platform_device *pdev)
goto err_iio_dev;
clk_prepare_enable(info->clk);
+ clk_prepare_enable(info->sclk);
exynos_adc_hw_init(info);
@@ -357,6 +366,7 @@ err_of_populate:
exynos_adc_remove_devices);
regulator_disable(info->vdd);
clk_disable_unprepare(info->clk);
+ clk_disable_unprepare(info->sclk);
err_iio_dev:
iio_device_unregister(indio_dev);
err_irq:
@@ -373,6 +383,7 @@ static int exynos_adc_remove(struct platform_device *pdev)
exynos_adc_remove_devices);
regulator_disable(info->vdd);
clk_disable_unprepare(info->clk);
+ clk_disable_unprepare(info->sclk);
writel(0, info->enable_reg);
iio_device_unregister(indio_dev);
free_irq(info->irq, info);
@@ -398,6 +409,7 @@ static int exynos_adc_suspend(struct device *dev)
}
clk_disable_unprepare(info->clk);
+ clk_disable_unprepare(info->sclk);
writel(0, info->enable_reg);
regulator_disable(info->vdd);
@@ -416,6 +428,7 @@ static int exynos_adc_resume(struct device *dev)
writel(1, info->enable_reg);
clk_prepare_enable(info->clk);
+ clk_prepare_enable(info->sclk);
exynos_adc_hw_init(info);
--
1.8.0
Hi,
On Friday, April 11, 2014 11:00:40 AM Chanwoo Choi wrote:
> This patch control special clock for ADC in Exynos series's FSYS block.
s/control/controls/
> If special clock of ADC is registerd on clock list of common clk framework,
> Exynos ADC drvier have to control this clock.
s/drvier/driver/
> Exynos3250/Exynos4/Exynos5 has 'adc' clock as following:
> - 'adc' clock: bus clock for ADC
>
> Exynos3250 has additional 'sclk_tsadc' clock as following:
> - 'sclk_tsadc' clock: special clock for ADC which provide clock to internal ADC
>
> Exynos 4210/4212/4412 and Exynos5250/5420 has not included 'sclk_tsadc' clock
> in FSYS_BLK. But, Exynos3250 based on Cortex-A7 has only included 'sclk_tsadc'
> clock in FSYS_BLK.
>
> Cc: Jonathan Cameron <[email protected]>
> Cc: Kukjin Kim <[email protected]>
> Cc: Naveen Krishna Chatradhi <[email protected]>
> Cc: [email protected]
> Signed-off-by: Chanwoo Choi <[email protected]>
> Signed-off-by: Kyungmin Park <[email protected]>
> ---
> drivers/iio/adc/exynos_adc.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
> index d25b262..4cd1975 100644
> --- a/drivers/iio/adc/exynos_adc.c
> +++ b/drivers/iio/adc/exynos_adc.c
> @@ -88,6 +88,7 @@ struct exynos_adc {
> void __iomem *regs;
> void __iomem *enable_reg;
> struct clk *clk;
> + struct clk *sclk;
> unsigned int irq;
> struct regulator *vdd;
>
> @@ -308,6 +309,13 @@ static int exynos_adc_probe(struct platform_device *pdev)
> goto err_irq;
> }
>
> + info->sclk = devm_clk_get(&pdev->dev, "sclk_tsadc");
> + if (IS_ERR(info->sclk)) {
> + dev_warn(&pdev->dev, "failed getting sclk clock, err = %ld\n",
> + PTR_ERR(info->sclk));
> + info->sclk = NULL;
> + }
> +
> info->vdd = devm_regulator_get(&pdev->dev, "vdd");
> if (IS_ERR(info->vdd)) {
> dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
> @@ -341,6 +349,7 @@ static int exynos_adc_probe(struct platform_device *pdev)
> goto err_iio_dev;
>
> clk_prepare_enable(info->clk);
> + clk_prepare_enable(info->sclk);
>
> exynos_adc_hw_init(info);
>
> @@ -357,6 +366,7 @@ err_of_populate:
> exynos_adc_remove_devices);
> regulator_disable(info->vdd);
> clk_disable_unprepare(info->clk);
> + clk_disable_unprepare(info->sclk);
Please disable clocks in the reverse of order in which they were enabled.
> err_iio_dev:
> iio_device_unregister(indio_dev);
> err_irq:
> @@ -373,6 +383,7 @@ static int exynos_adc_remove(struct platform_device *pdev)
> exynos_adc_remove_devices);
> regulator_disable(info->vdd);
> clk_disable_unprepare(info->clk);
> + clk_disable_unprepare(info->sclk);
ditto
> writel(0, info->enable_reg);
> iio_device_unregister(indio_dev);
> free_irq(info->irq, info);
> @@ -398,6 +409,7 @@ static int exynos_adc_suspend(struct device *dev)
> }
>
> clk_disable_unprepare(info->clk);
> + clk_disable_unprepare(info->sclk);
ditto
> writel(0, info->enable_reg);
> regulator_disable(info->vdd);
>
> @@ -416,6 +428,7 @@ static int exynos_adc_resume(struct device *dev)
>
> writel(1, info->enable_reg);
> clk_prepare_enable(info->clk);
> + clk_prepare_enable(info->sclk);
>
> exynos_adc_hw_init(info);
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
Hi Chanwoo,
On 11/04/14 04:00, Chanwoo Choi wrote:
> This patch control special clock for ADC in Exynos series's FSYS block.
> If special clock of ADC is registerd on clock list of common clk framework,
> Exynos ADC drvier have to control this clock.
>
> Exynos3250/Exynos4/Exynos5 has 'adc' clock as following:
> - 'adc' clock: bus clock for ADC
>
> Exynos3250 has additional 'sclk_tsadc' clock as following:
> - 'sclk_tsadc' clock: special clock for ADC which provide clock to internal ADC
>
> Exynos 4210/4212/4412 and Exynos5250/5420 has not included 'sclk_tsadc' clock
> in FSYS_BLK. But, Exynos3250 based on Cortex-A7 has only included 'sclk_tsadc'
> clock in FSYS_BLK.
I think a new compatible should be added for the ADC device for Exynos3250
and the required clocks should be handled properly, based on compatible
value. This could be handled, e.g. through some flags in driver's data
selected based on the compatible property value.
And the new clocks should be documented in Documentation/devicetree/bindings
/arm/samsung/exynos-adc.txt.
> Cc: Jonathan Cameron <[email protected]>
> Cc: Kukjin Kim <[email protected]>
> Cc: Naveen Krishna Chatradhi <[email protected]>
> Cc: [email protected]
> Signed-off-by: Chanwoo Choi <[email protected]>
> Signed-off-by: Kyungmin Park <[email protected]>
> ---
> drivers/iio/adc/exynos_adc.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
> index d25b262..4cd1975 100644
> --- a/drivers/iio/adc/exynos_adc.c
> +++ b/drivers/iio/adc/exynos_adc.c
> @@ -88,6 +88,7 @@ struct exynos_adc {
> void __iomem *regs;
> void __iomem *enable_reg;
> struct clk *clk;
> + struct clk *sclk;
> unsigned int irq;
> struct regulator *vdd;
>
> @@ -308,6 +309,13 @@ static int exynos_adc_probe(struct platform_device *pdev)
> goto err_irq;
> }
>
> + info->sclk = devm_clk_get(&pdev->dev, "sclk_tsadc");
> + if (IS_ERR(info->sclk)) {
> + dev_warn(&pdev->dev, "failed getting sclk clock, err = %ld\n",
> + PTR_ERR(info->sclk));
> + info->sclk = NULL;
> + }
> +
> info->vdd = devm_regulator_get(&pdev->dev, "vdd");
> if (IS_ERR(info->vdd)) {
> dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
> @@ -341,6 +349,7 @@ static int exynos_adc_probe(struct platform_device *pdev)
> goto err_iio_dev;
>
> clk_prepare_enable(info->clk);
> + clk_prepare_enable(info->sclk);
>
> exynos_adc_hw_init(info);
>
> @@ -357,6 +366,7 @@ err_of_populate:
> exynos_adc_remove_devices);
> regulator_disable(info->vdd);
> clk_disable_unprepare(info->clk);
> + clk_disable_unprepare(info->sclk);
> err_iio_dev:
> iio_device_unregister(indio_dev);
> err_irq:
> @@ -373,6 +383,7 @@ static int exynos_adc_remove(struct platform_device *pdev)
> exynos_adc_remove_devices);
> regulator_disable(info->vdd);
> clk_disable_unprepare(info->clk);
> + clk_disable_unprepare(info->sclk);
> writel(0, info->enable_reg);
> iio_device_unregister(indio_dev);
> free_irq(info->irq, info);
> @@ -398,6 +409,7 @@ static int exynos_adc_suspend(struct device *dev)
> }
>
> clk_disable_unprepare(info->clk);
> + clk_disable_unprepare(info->sclk);
> writel(0, info->enable_reg);
> regulator_disable(info->vdd);
>
> @@ -416,6 +428,7 @@ static int exynos_adc_resume(struct device *dev)
>
> writel(1, info->enable_reg);
> clk_prepare_enable(info->clk);
> + clk_prepare_enable(info->sclk);
>
> exynos_adc_hw_init(info);
>
>
Regards,
Sylwester
Hi,
On 11.04.2014 11:41, Bartlomiej Zolnierkiewicz wrote:
>
> Hi,
>
> On Friday, April 11, 2014 11:00:40 AM Chanwoo Choi wrote:
>> This patch control special clock for ADC in Exynos series's FSYS block.
>
> s/control/controls/
>
>> If special clock of ADC is registerd on clock list of common clk framework,
>> Exynos ADC drvier have to control this clock.
>
> s/drvier/driver/
>
>> Exynos3250/Exynos4/Exynos5 has 'adc' clock as following:
>> - 'adc' clock: bus clock for ADC
>>
>> Exynos3250 has additional 'sclk_tsadc' clock as following:
>> - 'sclk_tsadc' clock: special clock for ADC which provide clock to internal ADC
>>
>> Exynos 4210/4212/4412 and Exynos5250/5420 has not included 'sclk_tsadc' clock
>> in FSYS_BLK. But, Exynos3250 based on Cortex-A7 has only included 'sclk_tsadc'
>> clock in FSYS_BLK.
>>
>> Cc: Jonathan Cameron <[email protected]>
>> Cc: Kukjin Kim <[email protected]>
>> Cc: Naveen Krishna Chatradhi <[email protected]>
>> Cc: [email protected]
>> Signed-off-by: Chanwoo Choi <[email protected]>
>> Signed-off-by: Kyungmin Park <[email protected]>
>> ---
>> drivers/iio/adc/exynos_adc.c | 13 +++++++++++++
>> 1 file changed, 13 insertions(+)
This change alters DT bindings for Exynos ADC, so documentation must be
modified appropriately.
>>
>> diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
>> index d25b262..4cd1975 100644
>> --- a/drivers/iio/adc/exynos_adc.c
>> +++ b/drivers/iio/adc/exynos_adc.c
>> @@ -88,6 +88,7 @@ struct exynos_adc {
>> void __iomem *regs;
>> void __iomem *enable_reg;
>> struct clk *clk;
>> + struct clk *sclk;
>> unsigned int irq;
>> struct regulator *vdd;
>>
>> @@ -308,6 +309,13 @@ static int exynos_adc_probe(struct platform_device *pdev)
>> goto err_irq;
>> }
>>
>> + info->sclk = devm_clk_get(&pdev->dev, "sclk_tsadc");
>> + if (IS_ERR(info->sclk)) {
>> + dev_warn(&pdev->dev, "failed getting sclk clock, err = %ld\n",
>> + PTR_ERR(info->sclk));
>> + info->sclk = NULL;
>> + }
>> +
Is there any reason why we should have a warning on SoCs which don't
have this clock? I think this clock should be acquired only for affected
SoCs.
Best regards,
Tomasz
Hi Bartlomiej,
On Fri, Apr 11, 2014 at 6:41 PM, Bartlomiej Zolnierkiewicz
<[email protected]> wrote:
>
> Hi,
>
> On Friday, April 11, 2014 11:00:40 AM Chanwoo Choi wrote:
>> This patch control special clock for ADC in Exynos series's FSYS block.
>
> s/control/controls/
I'll fix it.
>
>> If special clock of ADC is registerd on clock list of common clk framework,
>> Exynos ADC drvier have to control this clock.
>
> s/drvier/driver/
I'll fix it.
>
>> Exynos3250/Exynos4/Exynos5 has 'adc' clock as following:
>> - 'adc' clock: bus clock for ADC
>>
>> Exynos3250 has additional 'sclk_tsadc' clock as following:
>> - 'sclk_tsadc' clock: special clock for ADC which provide clock to internal ADC
>>
>> Exynos 4210/4212/4412 and Exynos5250/5420 has not included 'sclk_tsadc' clock
>> in FSYS_BLK. But, Exynos3250 based on Cortex-A7 has only included 'sclk_tsadc'
>> clock in FSYS_BLK.
>>
>> Cc: Jonathan Cameron <[email protected]>
>> Cc: Kukjin Kim <[email protected]>
>> Cc: Naveen Krishna Chatradhi <[email protected]>
>> Cc: [email protected]
>> Signed-off-by: Chanwoo Choi <[email protected]>
>> Signed-off-by: Kyungmin Park <[email protected]>
>> ---
>> drivers/iio/adc/exynos_adc.c | 13 +++++++++++++
>> 1 file changed, 13 insertions(+)
>>
>> diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
>> index d25b262..4cd1975 100644
>> --- a/drivers/iio/adc/exynos_adc.c
>> +++ b/drivers/iio/adc/exynos_adc.c
>> @@ -88,6 +88,7 @@ struct exynos_adc {
>> void __iomem *regs;
>> void __iomem *enable_reg;
>> struct clk *clk;
>> + struct clk *sclk;
>> unsigned int irq;
>> struct regulator *vdd;
>>
>> @@ -308,6 +309,13 @@ static int exynos_adc_probe(struct platform_device *pdev)
>> goto err_irq;
>> }
>>
>> + info->sclk = devm_clk_get(&pdev->dev, "sclk_tsadc");
>> + if (IS_ERR(info->sclk)) {
>> + dev_warn(&pdev->dev, "failed getting sclk clock, err = %ld\n",
>> + PTR_ERR(info->sclk));
>> + info->sclk = NULL;
>> + }
>> +
>> info->vdd = devm_regulator_get(&pdev->dev, "vdd");
>> if (IS_ERR(info->vdd)) {
>> dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
>> @@ -341,6 +349,7 @@ static int exynos_adc_probe(struct platform_device *pdev)
>> goto err_iio_dev;
>>
>> clk_prepare_enable(info->clk);
>> + clk_prepare_enable(info->sclk);
>>
>> exynos_adc_hw_init(info);
>>
>> @@ -357,6 +366,7 @@ err_of_populate:
>> exynos_adc_remove_devices);
>> regulator_disable(info->vdd);
>> clk_disable_unprepare(info->clk);
>> + clk_disable_unprepare(info->sclk);
>
> Please disable clocks in the reverse of order in which they were enabled.
Is it necessary? I don't think that.
Best Regards,
Chanwoo Choi
Hi Sylwester,
On Fri, Apr 11, 2014 at 7:05 PM, Sylwester Nawrocki
<[email protected]> wrote:
> Hi Chanwoo,
>
> On 11/04/14 04:00, Chanwoo Choi wrote:
>> This patch control special clock for ADC in Exynos series's FSYS block.
>> If special clock of ADC is registerd on clock list of common clk framework,
>> Exynos ADC drvier have to control this clock.
>>
>> Exynos3250/Exynos4/Exynos5 has 'adc' clock as following:
>> - 'adc' clock: bus clock for ADC
>>
>> Exynos3250 has additional 'sclk_tsadc' clock as following:
>> - 'sclk_tsadc' clock: special clock for ADC which provide clock to internal ADC
>>
>> Exynos 4210/4212/4412 and Exynos5250/5420 has not included 'sclk_tsadc' clock
>> in FSYS_BLK. But, Exynos3250 based on Cortex-A7 has only included 'sclk_tsadc'
>> clock in FSYS_BLK.
>
> I think a new compatible should be added for the ADC device for Exynos3250
> and the required clocks should be handled properly, based on compatible
> value. This could be handled, e.g. through some flags in driver's data
> selected based on the compatible property value.
OK, I'll consider new patch using new compatible string according to
your comment.
>
> And the new clocks should be documented in Documentation/devicetree/bindings
> /arm/samsung/exynos-adc.txt.
OK, I'll modify it. Thanks,
Best Regards,
Chanwoo Choi
Hi Tomasz,
On Fri, Apr 11, 2014 at 7:56 PM, Tomasz Figa <[email protected]> wrote:
> Hi,
>
>
> On 11.04.2014 11:41, Bartlomiej Zolnierkiewicz wrote:
>>
>>
>> Hi,
>>
>> On Friday, April 11, 2014 11:00:40 AM Chanwoo Choi wrote:
>>>
>>> This patch control special clock for ADC in Exynos series's FSYS block.
>>
>>
>> s/control/controls/
>>
>>> If special clock of ADC is registerd on clock list of common clk
>>> framework,
>>> Exynos ADC drvier have to control this clock.
>>
>>
>> s/drvier/driver/
>>
>>> Exynos3250/Exynos4/Exynos5 has 'adc' clock as following:
>>> - 'adc' clock: bus clock for ADC
>>>
>>> Exynos3250 has additional 'sclk_tsadc' clock as following:
>>> - 'sclk_tsadc' clock: special clock for ADC which provide clock to
>>> internal ADC
>>>
>>> Exynos 4210/4212/4412 and Exynos5250/5420 has not included 'sclk_tsadc'
>>> clock
>>> in FSYS_BLK. But, Exynos3250 based on Cortex-A7 has only included
>>> 'sclk_tsadc'
>>> clock in FSYS_BLK.
>>>
>>> Cc: Jonathan Cameron <[email protected]>
>>> Cc: Kukjin Kim <[email protected]>
>>> Cc: Naveen Krishna Chatradhi <[email protected]>
>>> Cc: [email protected]
>>> Signed-off-by: Chanwoo Choi <[email protected]>
>>> Signed-off-by: Kyungmin Park <[email protected]>
>>> ---
>>> drivers/iio/adc/exynos_adc.c | 13 +++++++++++++
>>> 1 file changed, 13 insertions(+)
>
>
> This change alters DT bindings for Exynos ADC, so documentation must be
> modified appropriately.
OK, I'll add DT modification patch on next posting.
>
>
>>>
>>> diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
>>> index d25b262..4cd1975 100644
>>> --- a/drivers/iio/adc/exynos_adc.c
>>> +++ b/drivers/iio/adc/exynos_adc.c
>>> @@ -88,6 +88,7 @@ struct exynos_adc {
>>> void __iomem *regs;
>>> void __iomem *enable_reg;
>>> struct clk *clk;
>>> + struct clk *sclk;
>>> unsigned int irq;
>>> struct regulator *vdd;
>>>
>>> @@ -308,6 +309,13 @@ static int exynos_adc_probe(struct platform_device
>>> *pdev)
>>> goto err_irq;
>>> }
>>>
>>> + info->sclk = devm_clk_get(&pdev->dev, "sclk_tsadc");
>>> + if (IS_ERR(info->sclk)) {
>>> + dev_warn(&pdev->dev, "failed getting sclk clock, err =
>>> %ld\n",
>>> +
>>> PTR_ERR(info->sclk));
>>> + info->sclk = NULL;
>>> + }
>>> +
>
>
> Is there any reason why we should have a warning on SoCs which don't have
> this clock? I think this clock should be acquired only for affected SoCs.
You are right.
As Sylwester comment on previous reply, I'll consider to use new compatible name
to handle clock in only proper SoC according to compatible name.
Best Regards,
Chanwoo Choi
On April 11, 2014 11:45:42 PM GMT+01:00, "최찬우" <[email protected]> wrote:
>Hi Bartlomiej,
>
>On Fri, Apr 11, 2014 at 6:41 PM, Bartlomiej Zolnierkiewicz
><[email protected]> wrote:
>>
>> Hi,
>>
>> On Friday, April 11, 2014 11:00:40 AM Chanwoo Choi wrote:
>>> This patch control special clock for ADC in Exynos series's FSYS
>block.
>>
>> s/control/controls/
>
>I'll fix it.
>
>>
>>> If special clock of ADC is registerd on clock list of common clk
>framework,
>>> Exynos ADC drvier have to control this clock.
>>
>> s/drvier/driver/
>
>I'll fix it.
>
>>
>>> Exynos3250/Exynos4/Exynos5 has 'adc' clock as following:
>>> - 'adc' clock: bus clock for ADC
>>>
>>> Exynos3250 has additional 'sclk_tsadc' clock as following:
>>> - 'sclk_tsadc' clock: special clock for ADC which provide clock to
>internal ADC
>>>
>>> Exynos 4210/4212/4412 and Exynos5250/5420 has not included
>'sclk_tsadc' clock
>>> in FSYS_BLK. But, Exynos3250 based on Cortex-A7 has only included
>'sclk_tsadc'
>>> clock in FSYS_BLK.
>>>
>>> Cc: Jonathan Cameron <[email protected]>
>>> Cc: Kukjin Kim <[email protected]>
>>> Cc: Naveen Krishna Chatradhi <[email protected]>
>>> Cc: [email protected]
>>> Signed-off-by: Chanwoo Choi <[email protected]>
>>> Signed-off-by: Kyungmin Park <[email protected]>
>>> ---
>>> drivers/iio/adc/exynos_adc.c | 13 +++++++++++++
>>> 1 file changed, 13 insertions(+)
>>>
>>> diff --git a/drivers/iio/adc/exynos_adc.c
>b/drivers/iio/adc/exynos_adc.c
>>> index d25b262..4cd1975 100644
>>> --- a/drivers/iio/adc/exynos_adc.c
>>> +++ b/drivers/iio/adc/exynos_adc.c
>>> @@ -88,6 +88,7 @@ struct exynos_adc {
>>> void __iomem *regs;
>>> void __iomem *enable_reg;
>>> struct clk *clk;
>>> + struct clk *sclk;
>>> unsigned int irq;
>>> struct regulator *vdd;
>>>
>>> @@ -308,6 +309,13 @@ static int exynos_adc_probe(struct
>platform_device *pdev)
>>> goto err_irq;
>>> }
>>>
>>> + info->sclk = devm_clk_get(&pdev->dev, "sclk_tsadc");
>>> + if (IS_ERR(info->sclk)) {
>>> + dev_warn(&pdev->dev, "failed getting sclk clock, err =
>%ld\n",
>>> +
>PTR_ERR(info->sclk));
>>> + info->sclk = NULL;
>>> + }
>>> +
>>> info->vdd = devm_regulator_get(&pdev->dev, "vdd");
>>> if (IS_ERR(info->vdd)) {
>>> dev_err(&pdev->dev, "failed getting regulator, err =
>%ld\n",
>>> @@ -341,6 +349,7 @@ static int exynos_adc_probe(struct
>platform_device *pdev)
>>> goto err_iio_dev;
>>>
>>> clk_prepare_enable(info->clk);
>>> + clk_prepare_enable(info->sclk);
>>>
>>> exynos_adc_hw_init(info);
>>>
>>> @@ -357,6 +366,7 @@ err_of_populate:
>>> exynos_adc_remove_devices);
>>> regulator_disable(info->vdd);
>>> clk_disable_unprepare(info->clk);
>>> + clk_disable_unprepare(info->sclk);
>>
>> Please disable clocks in the reverse of order in which they were
>enabled.
>
>Is it necessary? I don't think that.
It is probably not a bug but it is more obviously correct in the reverse order so that is how it should be done!
>
>Best Regards,
>Chanwoo Choi
--
Sent from my Android phone with K-9 Mail. Please excuse my brevity.
Hi Jonathan,
On 04/12/2014 04:49 PM, Jonathan Cameron wrote:
>
>
> On April 11, 2014 11:45:42 PM GMT+01:00, "최찬우" <[email protected]> wrote:
>> Hi Bartlomiej,
>>
>> On Fri, Apr 11, 2014 at 6:41 PM, Bartlomiej Zolnierkiewicz
>> <[email protected]> wrote:
>>>
>>> Hi,
>>>
>>> On Friday, April 11, 2014 11:00:40 AM Chanwoo Choi wrote:
>>>> This patch control special clock for ADC in Exynos series's FSYS
>> block.
>>>
>>> s/control/controls/
>>
>> I'll fix it.
>>
>>>
>>>> If special clock of ADC is registerd on clock list of common clk
>> framework,
>>>> Exynos ADC drvier have to control this clock.
>>>
>>> s/drvier/driver/
>>
>> I'll fix it.
>>
>>>
>>>> Exynos3250/Exynos4/Exynos5 has 'adc' clock as following:
>>>> - 'adc' clock: bus clock for ADC
>>>>
>>>> Exynos3250 has additional 'sclk_tsadc' clock as following:
>>>> - 'sclk_tsadc' clock: special clock for ADC which provide clock to
>> internal ADC
>>>>
>>>> Exynos 4210/4212/4412 and Exynos5250/5420 has not included
>> 'sclk_tsadc' clock
>>>> in FSYS_BLK. But, Exynos3250 based on Cortex-A7 has only included
>> 'sclk_tsadc'
>>>> clock in FSYS_BLK.
>>>>
>>>> Cc: Jonathan Cameron <[email protected]>
>>>> Cc: Kukjin Kim <[email protected]>
>>>> Cc: Naveen Krishna Chatradhi <[email protected]>
>>>> Cc: [email protected]
>>>> Signed-off-by: Chanwoo Choi <[email protected]>
>>>> Signed-off-by: Kyungmin Park <[email protected]>
>>>> ---
>>>> drivers/iio/adc/exynos_adc.c | 13 +++++++++++++
>>>> 1 file changed, 13 insertions(+)
>>>>
>>>> diff --git a/drivers/iio/adc/exynos_adc.c
>> b/drivers/iio/adc/exynos_adc.c
>>>> index d25b262..4cd1975 100644
>>>> --- a/drivers/iio/adc/exynos_adc.c
>>>> +++ b/drivers/iio/adc/exynos_adc.c
>>>> @@ -88,6 +88,7 @@ struct exynos_adc {
>>>> void __iomem *regs;
>>>> void __iomem *enable_reg;
>>>> struct clk *clk;
>>>> + struct clk *sclk;
>>>> unsigned int irq;
>>>> struct regulator *vdd;
>>>>
>>>> @@ -308,6 +309,13 @@ static int exynos_adc_probe(struct
>> platform_device *pdev)
>>>> goto err_irq;
>>>> }
>>>>
>>>> + info->sclk = devm_clk_get(&pdev->dev, "sclk_tsadc");
>>>> + if (IS_ERR(info->sclk)) {
>>>> + dev_warn(&pdev->dev, "failed getting sclk clock, err =
>> %ld\n",
>>>> +
>> PTR_ERR(info->sclk));
>>>> + info->sclk = NULL;
>>>> + }
>>>> +
>>>> info->vdd = devm_regulator_get(&pdev->dev, "vdd");
>>>> if (IS_ERR(info->vdd)) {
>>>> dev_err(&pdev->dev, "failed getting regulator, err =
>> %ld\n",
>>>> @@ -341,6 +349,7 @@ static int exynos_adc_probe(struct
>> platform_device *pdev)
>>>> goto err_iio_dev;
>>>>
>>>> clk_prepare_enable(info->clk);
>>>> + clk_prepare_enable(info->sclk);
>>>>
>>>> exynos_adc_hw_init(info);
>>>>
>>>> @@ -357,6 +366,7 @@ err_of_populate:
>>>> exynos_adc_remove_devices);
>>>> regulator_disable(info->vdd);
>>>> clk_disable_unprepare(info->clk);
>>>> + clk_disable_unprepare(info->sclk);
>>>
>>> Please disable clocks in the reverse of order in which they were
>> enabled.
>>
>> Is it necessary? I don't think that.
> It is probably not a bug but it is more obviously correct in the reverse order so that is how it should be done!
OK, I'll fix it on next posting(v2). Thanks.
Best Regards,
Chanwoo Choi