ABE DPLL frequency need to be lowered from 361267200
to 180633600 to facilitate the ATL requironments.
The dpll_abe_m2x2_ck clock need to be set to double
of ABE DPLL rate in order to have correct clocks
for audio.
Signed-off-by: Peter Ujfalusi <[email protected]>
---
drivers/clk/ti/clk-7xx.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index f7e40734c819..19a55bf407dd 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -16,7 +16,7 @@
#include <linux/clkdev.h>
#include <linux/clk/ti.h>
-#define DRA7_DPLL_ABE_DEFFREQ 361267200
+#define DRA7_DPLL_ABE_DEFFREQ 180633600
#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
@@ -322,6 +322,11 @@ int __init dra7xx_dt_clk_init(void)
if (rc)
pr_err("%s: failed to configure ABE DPLL!\n", __func__);
+ dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
+ rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
+ if (rc)
+ pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
+
dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
if (rc)
--
1.9.1
On 04/02/2014 04:48 PM, Peter Ujfalusi wrote:
> ABE DPLL frequency need to be lowered from 361267200
> to 180633600 to facilitate the ATL requironments.
> The dpll_abe_m2x2_ck clock need to be set to double
> of ABE DPLL rate in order to have correct clocks
> for audio.
Do you have some sort of TRM reference for this?
-Tero
>
> Signed-off-by: Peter Ujfalusi <[email protected]>
> ---
> drivers/clk/ti/clk-7xx.c | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
> index f7e40734c819..19a55bf407dd 100644
> --- a/drivers/clk/ti/clk-7xx.c
> +++ b/drivers/clk/ti/clk-7xx.c
> @@ -16,7 +16,7 @@
> #include <linux/clkdev.h>
> #include <linux/clk/ti.h>
>
> -#define DRA7_DPLL_ABE_DEFFREQ 361267200
> +#define DRA7_DPLL_ABE_DEFFREQ 180633600
> #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
>
>
> @@ -322,6 +322,11 @@ int __init dra7xx_dt_clk_init(void)
> if (rc)
> pr_err("%s: failed to configure ABE DPLL!\n", __func__);
>
> + dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
> + if (rc)
> + pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
> +
> dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
> rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
> if (rc)
>
On 04/02/2014 05:12 PM, Tero Kristo wrote:
> On 04/02/2014 04:48 PM, Peter Ujfalusi wrote:
>> ABE DPLL frequency need to be lowered from 361267200
>> to 180633600 to facilitate the ATL requironments.
>> The dpll_abe_m2x2_ck clock need to be set to double
>> of ABE DPLL rate in order to have correct clocks
>> for audio.
>
> Do you have some sort of TRM reference for this?
The ATL's max divider is 32.
For audio purpose the clock coming out from the ATL instance should be
128 * fs. It is only possible to have 44.1KHz sampling rate with ABE DPLL set
to 361267200 or 180633600. Which means:
The atl generated clock should be 128 * 44100 = 5644800
>From ABE_DPLL 361267200 we would need to have 64 as divider (ATL can't do this).
>From the suggested ABE_DPLL of 180633600 we can use ATL divider of 32, which
is the maximum it can do.
So the reason for the change is to have ATLPCLK clock which can be used for
audio in the future, the 361267200 is just too high.
>
> -Tero
>
>>
>> Signed-off-by: Peter Ujfalusi <[email protected]>
>> ---
>> drivers/clk/ti/clk-7xx.c | 7 ++++++-
>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
>> index f7e40734c819..19a55bf407dd 100644
>> --- a/drivers/clk/ti/clk-7xx.c
>> +++ b/drivers/clk/ti/clk-7xx.c
>> @@ -16,7 +16,7 @@
>> #include <linux/clkdev.h>
>> #include <linux/clk/ti.h>
>>
>> -#define DRA7_DPLL_ABE_DEFFREQ 361267200
>> +#define DRA7_DPLL_ABE_DEFFREQ 180633600
>> #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
>>
>>
>> @@ -322,6 +322,11 @@ int __init dra7xx_dt_clk_init(void)
>> if (rc)
>> pr_err("%s: failed to configure ABE DPLL!\n", __func__);
>>
>> + dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
>> + if (rc)
>> + pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
>> +
>> dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
>> rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
>> if (rc)
>>
>
--
P?ter
Mike, Tero,
On 04/03/2014 09:29 AM, Peter Ujfalusi wrote:
> On 04/02/2014 05:12 PM, Tero Kristo wrote:
>> On 04/02/2014 04:48 PM, Peter Ujfalusi wrote:
>>> ABE DPLL frequency need to be lowered from 361267200
>>> to 180633600 to facilitate the ATL requironments.
>>> The dpll_abe_m2x2_ck clock need to be set to double
>>> of ABE DPLL rate in order to have correct clocks
>>> for audio.
>>
>> Do you have some sort of TRM reference for this?
>
> The ATL's max divider is 32.
> For audio purpose the clock coming out from the ATL instance should be
> 128 * fs. It is only possible to have 44.1KHz sampling rate with ABE DPLL set
> to 361267200 or 180633600. Which means:
> The atl generated clock should be 128 * 44100 = 5644800
> From ABE_DPLL 361267200 we would need to have 64 as divider (ATL can't do this).
> From the suggested ABE_DPLL of 180633600 we can use ATL divider of 32, which
> is the maximum it can do.
>
> So the reason for the change is to have ATLPCLK clock which can be used for
> audio in the future, the 361267200 is just too high.
Tero: can I have your ack for this patch or do you have further concerns?
Mike: do you want me to resend this patch?
Thanks,
P?ter
>
>>
>> -Tero
>>
>>>
>>> Signed-off-by: Peter Ujfalusi <[email protected]>
>>> ---
>>> drivers/clk/ti/clk-7xx.c | 7 ++++++-
>>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
>>> index f7e40734c819..19a55bf407dd 100644
>>> --- a/drivers/clk/ti/clk-7xx.c
>>> +++ b/drivers/clk/ti/clk-7xx.c
>>> @@ -16,7 +16,7 @@
>>> #include <linux/clkdev.h>
>>> #include <linux/clk/ti.h>
>>>
>>> -#define DRA7_DPLL_ABE_DEFFREQ 361267200
>>> +#define DRA7_DPLL_ABE_DEFFREQ 180633600
>>> #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
>>>
>>>
>>> @@ -322,6 +322,11 @@ int __init dra7xx_dt_clk_init(void)
>>> if (rc)
>>> pr_err("%s: failed to configure ABE DPLL!\n", __func__);
>>>
>>> + dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
>>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
>>> + if (rc)
>>> + pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
>>> +
>>> dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
>>> rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
>>> if (rc)
>>>
>>
>
>
On 04/24/2014 12:11 PM, Peter Ujfalusi wrote:
> Mike, Tero,
>
> On 04/03/2014 09:29 AM, Peter Ujfalusi wrote:
>> On 04/02/2014 05:12 PM, Tero Kristo wrote:
>>> On 04/02/2014 04:48 PM, Peter Ujfalusi wrote:
>>>> ABE DPLL frequency need to be lowered from 361267200
>>>> to 180633600 to facilitate the ATL requironments.
>>>> The dpll_abe_m2x2_ck clock need to be set to double
>>>> of ABE DPLL rate in order to have correct clocks
>>>> for audio.
>>>
>>> Do you have some sort of TRM reference for this?
>>
>> The ATL's max divider is 32.
>> For audio purpose the clock coming out from the ATL instance should be
>> 128 * fs. It is only possible to have 44.1KHz sampling rate with ABE DPLL set
>> to 361267200 or 180633600. Which means:
>> The atl generated clock should be 128 * 44100 = 5644800
>> From ABE_DPLL 361267200 we would need to have 64 as divider (ATL can't do this).
>> From the suggested ABE_DPLL of 180633600 we can use ATL divider of 32, which
>> is the maximum it can do.
>>
>> So the reason for the change is to have ATLPCLK clock which can be used for
>> audio in the future, the 361267200 is just too high.
>
> Tero: can I have your ack for this patch or do you have further concerns?
Yea looks good to me, except for the fact that there is some work on
getting default rate/parent support through DT. I would like a comment
from Mike about the estimate when this can get in, and whether we should
merge intermediate solutions still like this.
Anyway, you can consider this patch acked by me, I'll let Mike to decide
what to do with it though.
-Tero
> Mike: do you want me to resend this patch?
>
> Thanks,
> P?ter
>
>>
>>>
>>> -Tero
>>>
>>>>
>>>> Signed-off-by: Peter Ujfalusi <[email protected]>
>>>> ---
>>>> drivers/clk/ti/clk-7xx.c | 7 ++++++-
>>>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
>>>> index f7e40734c819..19a55bf407dd 100644
>>>> --- a/drivers/clk/ti/clk-7xx.c
>>>> +++ b/drivers/clk/ti/clk-7xx.c
>>>> @@ -16,7 +16,7 @@
>>>> #include <linux/clkdev.h>
>>>> #include <linux/clk/ti.h>
>>>>
>>>> -#define DRA7_DPLL_ABE_DEFFREQ 361267200
>>>> +#define DRA7_DPLL_ABE_DEFFREQ 180633600
>>>> #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
>>>>
>>>>
>>>> @@ -322,6 +322,11 @@ int __init dra7xx_dt_clk_init(void)
>>>> if (rc)
>>>> pr_err("%s: failed to configure ABE DPLL!\n", __func__);
>>>>
>>>> + dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
>>>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
>>>> + if (rc)
>>>> + pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
>>>> +
>>>> dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
>>>> rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
>>>> if (rc)
>>>>
>>>
>>
>>
>
On 05/06/2014 04:39 PM, Peter Ujfalusi wrote:
>>> Tero: can I have your ack for this patch or do you have further concerns?
>>
>> Yea looks good to me, except for the fact that there is some work on getting
>> default rate/parent support through DT. I would like a comment from Mike about
>> the estimate when this can get in, and whether we should merge intermediate
>> solutions still like this.
>>
>> Anyway, you can consider this patch acked by me, I'll let Mike to decide what
>> to do with it though.
>
> Do you have anything against this patch? Since right now there is no other
> ways to fix the ABE DPLL for dra7 it would be great if we could have this in
> till we have the final solution. Also I'd like to point out that the original
> frequency the ABE DPLL was not correct and renders the audio to be not usable
> on the platform.
Mike: can we have this patch still pushed for 3.16? I can resend it right away
if you lost the original patch.
Thanks,
P?ter
>
>>>>
>>>>>
>>>>> -Tero
>>>>>
>>>>>>
>>>>>> Signed-off-by: Peter Ujfalusi <[email protected]>
>>>>>> ---
>>>>>> drivers/clk/ti/clk-7xx.c | 7 ++++++-
>>>>>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
>>>>>> index f7e40734c819..19a55bf407dd 100644
>>>>>> --- a/drivers/clk/ti/clk-7xx.c
>>>>>> +++ b/drivers/clk/ti/clk-7xx.c
>>>>>> @@ -16,7 +16,7 @@
>>>>>> #include <linux/clkdev.h>
>>>>>> #include <linux/clk/ti.h>
>>>>>>
>>>>>> -#define DRA7_DPLL_ABE_DEFFREQ 361267200
>>>>>> +#define DRA7_DPLL_ABE_DEFFREQ 180633600
>>>>>> #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
>>>>>>
>>>>>>
>>>>>> @@ -322,6 +322,11 @@ int __init dra7xx_dt_clk_init(void)
>>>>>> if (rc)
>>>>>> pr_err("%s: failed to configure ABE DPLL!\n", __func__);
>>>>>>
>>>>>> + dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
>>>>>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
>>>>>> + if (rc)
>>>>>> + pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
>>>>>> +
>>>>>> dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
>>>>>> rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
>>>>>> if (rc)
>>>>>>
>>>>>
>>>>
>>>>
>>>
>>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to [email protected]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
Quoting Peter Ujfalusi (2014-07-14 03:10:28)
> On 05/06/2014 04:39 PM, Peter Ujfalusi wrote:
> >>> Tero: can I have your ack for this patch or do you have further concerns?
> >>
> >> Yea looks good to me, except for the fact that there is some work on getting
> >> default rate/parent support through DT. I would like a comment from Mike about
> >> the estimate when this can get in, and whether we should merge intermediate
> >> solutions still like this.
Tero,
On May 19 you said, "Thanks, queued for 3.16/ti-clk-drv." but I never
received that as part of the TI clock fixes. :-(
I've taken Sylwester's patch in for the DT-based assigned clock rates
and parents. You can find it in clk-next. (maybe you are still on
vacation? I don't know...)
> >>
> >> Anyway, you can consider this patch acked by me, I'll let Mike to decide what
> >> to do with it though.
> >
> > Do you have anything against this patch? Since right now there is no other
> > ways to fix the ABE DPLL for dra7 it would be great if we could have this in
> > till we have the final solution. Also I'd like to point out that the original
> > frequency the ABE DPLL was not correct and renders the audio to be not usable
> > on the platform.
>
> Mike: can we have this patch still pushed for 3.16? I can resend it right away
> if you lost the original patch.
Peter,
I have your original patch. No need to resend. Let's see if Tero
comments this week, otherwise I can take it with his previously supplied
Ack and send it off. Probably needs to be sent by Thursday at the
latest.
Regards,
Mike
>
> Thanks,
> Péter
>
>
> >
> >>>>
> >>>>>
> >>>>> -Tero
> >>>>>
> >>>>>>
> >>>>>> Signed-off-by: Peter Ujfalusi <[email protected]>
> >>>>>> ---
> >>>>>> drivers/clk/ti/clk-7xx.c | 7 ++++++-
> >>>>>> 1 file changed, 6 insertions(+), 1 deletion(-)
> >>>>>>
> >>>>>> diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
> >>>>>> index f7e40734c819..19a55bf407dd 100644
> >>>>>> --- a/drivers/clk/ti/clk-7xx.c
> >>>>>> +++ b/drivers/clk/ti/clk-7xx.c
> >>>>>> @@ -16,7 +16,7 @@
> >>>>>> #include <linux/clkdev.h>
> >>>>>> #include <linux/clk/ti.h>
> >>>>>>
> >>>>>> -#define DRA7_DPLL_ABE_DEFFREQ 361267200
> >>>>>> +#define DRA7_DPLL_ABE_DEFFREQ 180633600
> >>>>>> #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
> >>>>>>
> >>>>>>
> >>>>>> @@ -322,6 +322,11 @@ int __init dra7xx_dt_clk_init(void)
> >>>>>> if (rc)
> >>>>>> pr_err("%s: failed to configure ABE DPLL!\n", __func__);
> >>>>>>
> >>>>>> + dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
> >>>>>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
> >>>>>> + if (rc)
> >>>>>> + pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
> >>>>>> +
> >>>>>> dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
> >>>>>> rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
> >>>>>> if (rc)
> >>>>>>
> >>>>>
> >>>>
> >>>>
> >>>
> >>
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> > the body of a message to [email protected]
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
> >
>
On 07/29/2014 09:27 AM, Mike Turquette wrote:
> Quoting Peter Ujfalusi (2014-07-14 03:10:28)
>> On 05/06/2014 04:39 PM, Peter Ujfalusi wrote:
>>>>> Tero: can I have your ack for this patch or do you have further concerns?
>>>>
>>>> Yea looks good to me, except for the fact that there is some work on getting
>>>> default rate/parent support through DT. I would like a comment from Mike about
>>>> the estimate when this can get in, and whether we should merge intermediate
>>>> solutions still like this.
>
> Tero,
>
> On May 19 you said, "Thanks, queued for 3.16/ti-clk-drv." but I never
> received that as part of the TI clock fixes. :-(
>
> I've taken Sylwester's patch in for the DT-based assigned clock rates
> and parents. You can find it in clk-next. (maybe you are still on
> vacation? I don't know...)
>
>>>>
>>>> Anyway, you can consider this patch acked by me, I'll let Mike to decide what
>>>> to do with it though.
>>>
>>> Do you have anything against this patch? Since right now there is no other
>>> ways to fix the ABE DPLL for dra7 it would be great if we could have this in
>>> till we have the final solution. Also I'd like to point out that the original
>>> frequency the ABE DPLL was not correct and renders the audio to be not usable
>>> on the platform.
>>
>> Mike: can we have this patch still pushed for 3.16? I can resend it right away
>> if you lost the original patch.
>
> Peter,
>
> I have your original patch. No need to resend. Let's see if Tero
> comments this week, otherwise I can take it with his previously supplied
> Ack and send it off. Probably needs to be sent by Thursday at the
> latest.
Oh yea, seems this got lost into the myriad of branches I have. I can
push this on top of my for-v3.17/ti-clk-drv if you like.
-Tero
>
> Regards,
> Mike
>
>>
>> Thanks,
>> Péter
>>
>>
>>>
>>>>>>
>>>>>>>
>>>>>>> -Tero
>>>>>>>
>>>>>>>>
>>>>>>>> Signed-off-by: Peter Ujfalusi <[email protected]>
>>>>>>>> ---
>>>>>>>> drivers/clk/ti/clk-7xx.c | 7 ++++++-
>>>>>>>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>>>>>>>
>>>>>>>> diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
>>>>>>>> index f7e40734c819..19a55bf407dd 100644
>>>>>>>> --- a/drivers/clk/ti/clk-7xx.c
>>>>>>>> +++ b/drivers/clk/ti/clk-7xx.c
>>>>>>>> @@ -16,7 +16,7 @@
>>>>>>>> #include <linux/clkdev.h>
>>>>>>>> #include <linux/clk/ti.h>
>>>>>>>>
>>>>>>>> -#define DRA7_DPLL_ABE_DEFFREQ 361267200
>>>>>>>> +#define DRA7_DPLL_ABE_DEFFREQ 180633600
>>>>>>>> #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
>>>>>>>>
>>>>>>>>
>>>>>>>> @@ -322,6 +322,11 @@ int __init dra7xx_dt_clk_init(void)
>>>>>>>> if (rc)
>>>>>>>> pr_err("%s: failed to configure ABE DPLL!\n", __func__);
>>>>>>>>
>>>>>>>> + dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
>>>>>>>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
>>>>>>>> + if (rc)
>>>>>>>> + pr_err("%s: failed to configure ABE DPLL m2x2!\n", __func__);
>>>>>>>> +
>>>>>>>> dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
>>>>>>>> rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
>>>>>>>> if (rc)
>>>>>>>>
>>>>>>>
>>>>>>
>>>>>>
>>>>>
>>>>
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>>> the body of a message to [email protected]
>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>>
>>
On Tue, Jul 29, 2014 at 1:23 AM, Tero Kristo <[email protected]> wrote:
> On 07/29/2014 09:27 AM, Mike Turquette wrote:
>>
>> Quoting Peter Ujfalusi (2014-07-14 03:10:28)
>>>
>>> On 05/06/2014 04:39 PM, Peter Ujfalusi wrote:
>>>>>>
>>>>>> Tero: can I have your ack for this patch or do you have further
>>>>>> concerns?
>>>>>
>>>>>
>>>>> Yea looks good to me, except for the fact that there is some work on
>>>>> getting
>>>>> default rate/parent support through DT. I would like a comment from
>>>>> Mike about
>>>>> the estimate when this can get in, and whether we should merge
>>>>> intermediate
>>>>> solutions still like this.
>>
>>
>> Tero,
>>
>> On May 19 you said, "Thanks, queued for 3.16/ti-clk-drv." but I never
>> received that as part of the TI clock fixes. :-(
>>
>> I've taken Sylwester's patch in for the DT-based assigned clock rates
>> and parents. You can find it in clk-next. (maybe you are still on
>> vacation? I don't know...)
>>
>>>>>
>>>>> Anyway, you can consider this patch acked by me, I'll let Mike to
>>>>> decide what
>>>>> to do with it though.
>>>>
>>>>
>>>> Do you have anything against this patch? Since right now there is no
>>>> other
>>>> ways to fix the ABE DPLL for dra7 it would be great if we could have
>>>> this in
>>>> till we have the final solution. Also I'd like to point out that the
>>>> original
>>>> frequency the ABE DPLL was not correct and renders the audio to be not
>>>> usable
>>>> on the platform.
>>>
>>>
>>> Mike: can we have this patch still pushed for 3.16? I can resend it right
>>> away
>>> if you lost the original patch.
>>
>>
>> Peter,
>>
>> I have your original patch. No need to resend. Let's see if Tero
>> comments this week, otherwise I can take it with his previously supplied
>> Ack and send it off. Probably needs to be sent by Thursday at the
>> latest.
>
>
> Oh yea, seems this got lost into the myriad of branches I have. I can push
> this on top of my for-v3.17/ti-clk-drv if you like.
That is the easiest thing for me. I think that Peter wanted to take
this as a fix for 3.16 though. Peter is that correct?
Regards,
Mike
>
> -Tero
>
>
>>
>> Regards,
>> Mike
>>
>>>
>>> Thanks,
>>> Péter
>>>
>>>
>>>>
>>>>>>>
>>>>>>>>
>>>>>>>> -Tero
>>>>>>>>
>>>>>>>>>
>>>>>>>>> Signed-off-by: Peter Ujfalusi <[email protected]>
>>>>>>>>> ---
>>>>>>>>> drivers/clk/ti/clk-7xx.c | 7 ++++++-
>>>>>>>>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>>>>>>>>
>>>>>>>>> diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
>>>>>>>>> index f7e40734c819..19a55bf407dd 100644
>>>>>>>>> --- a/drivers/clk/ti/clk-7xx.c
>>>>>>>>> +++ b/drivers/clk/ti/clk-7xx.c
>>>>>>>>> @@ -16,7 +16,7 @@
>>>>>>>>> #include <linux/clkdev.h>
>>>>>>>>> #include <linux/clk/ti.h>
>>>>>>>>>
>>>>>>>>> -#define DRA7_DPLL_ABE_DEFFREQ 361267200
>>>>>>>>> +#define DRA7_DPLL_ABE_DEFFREQ 180633600
>>>>>>>>> #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> @@ -322,6 +322,11 @@ int __init dra7xx_dt_clk_init(void)
>>>>>>>>> if (rc)
>>>>>>>>> pr_err("%s: failed to configure ABE DPLL!\n",
>>>>>>>>> __func__);
>>>>>>>>>
>>>>>>>>> + dpll_ck = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
>>>>>>>>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_ABE_DEFFREQ * 2);
>>>>>>>>> + if (rc)
>>>>>>>>> + pr_err("%s: failed to configure ABE DPLL m2x2!\n",
>>>>>>>>> __func__);
>>>>>>>>> +
>>>>>>>>> dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
>>>>>>>>> rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
>>>>>>>>> if (rc)
>>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>
>>>>>
>>>>
>>>> --
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>>>> the body of a message to [email protected]
>>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>>>
>>>
>
On 07/29/2014 07:12 PM, Mike Turquette wrote:
>> Oh yea, seems this got lost into the myriad of branches I have. I can push
>> this on top of my for-v3.17/ti-clk-drv if you like.
>
> That is the easiest thing for me. I think that Peter wanted to take
> this as a fix for 3.16 though. Peter is that correct?
Yes, it would have been better to have it in 3.16 along with the DRA7 ATL
clock driver. W/O this patch the ATL will not going to be usable since the ABE
DPLL is set too high to be usable for it's purpose.
--
Péter
On 07/30/2014 08:53 AM, Peter Ujfalusi wrote:
> On 07/29/2014 07:12 PM, Mike Turquette wrote:
>>> Oh yea, seems this got lost into the myriad of branches I have. I can push
>>> this on top of my for-v3.17/ti-clk-drv if you like.
>>
>> That is the easiest thing for me. I think that Peter wanted to take
>> this as a fix for 3.16 though. Peter is that correct?
>
> Yes, it would have been better to have it in 3.16 along with the DRA7 ATL
> clock driver. W/O this patch the ATL will not going to be usable since the ABE
> DPLL is set too high to be usable for it's purpose.
>
Ok, this is now pushed on top of the for-v3.17/ti-clk-driver branch in
my git-repo. Mike, do you want a new pull-req for this just in case?
-Tero
Quoting Tero Kristo (2014-07-30 05:27:07)
> On 07/30/2014 08:53 AM, Peter Ujfalusi wrote:
> > On 07/29/2014 07:12 PM, Mike Turquette wrote:
> >>> Oh yea, seems this got lost into the myriad of branches I have. I can push
> >>> this on top of my for-v3.17/ti-clk-drv if you like.
> >>
> >> That is the easiest thing for me. I think that Peter wanted to take
> >> this as a fix for 3.16 though. Peter is that correct?
> >
> > Yes, it would have been better to have it in 3.16 along with the DRA7 ATL
> > clock driver. W/O this patch the ATL will not going to be usable since the ABE
> > DPLL is set too high to be usable for it's purpose.
> >
>
> Ok, this is now pushed on top of the for-v3.17/ti-clk-driver branch in
> my git-repo. Mike, do you want a new pull-req for this just in case?
I've picked it manually and applied on top of 3.16-rc7 for a last minute
fix. I can add your Ack if you like.
Regards,
Mike
>
> -Tero
On 07/31/2014 01:42 AM, Mike Turquette wrote:
> Quoting Tero Kristo (2014-07-30 05:27:07)
>> On 07/30/2014 08:53 AM, Peter Ujfalusi wrote:
>>> On 07/29/2014 07:12 PM, Mike Turquette wrote:
>>>>> Oh yea, seems this got lost into the myriad of branches I have. I can push
>>>>> this on top of my for-v3.17/ti-clk-drv if you like.
>>>>
>>>> That is the easiest thing for me. I think that Peter wanted to take
>>>> this as a fix for 3.16 though. Peter is that correct?
>>>
>>> Yes, it would have been better to have it in 3.16 along with the DRA7 ATL
>>> clock driver. W/O this patch the ATL will not going to be usable since the ABE
>>> DPLL is set too high to be usable for it's purpose.
>>>
>>
>> Ok, this is now pushed on top of the for-v3.17/ti-clk-driver branch in
>> my git-repo. Mike, do you want a new pull-req for this just in case?
>
> I've picked it manually and applied on top of 3.16-rc7 for a last minute
> fix. I can add your Ack if you like.
Ok thanks, Add my ack if you wish, no need from my side.
-Tero