LinuxLists.cc - [PATCH v5 00/11] memory: add Atmel EBI (External Bus Interface) driver

2014-12-03 20:44:24

Subject: [PATCH v5 00/11] memory: add Atmel EBI (External Bus Interface) driver

2014-12-03 20:44:35

Subject: [PATCH v5 08/11] ARM: at91/dt: add HSMC (Static Memory Controller) node in sama5d3 dtsi

Add the SMC node in sama5d3 dtsi.

Signed-off-by: Boris Brezillon <[email protected]>
---
arch/arm/boot/dts/sama5d3.dtsi | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 5f4144d..9f1eed5 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -395,6 +395,11 @@
clock-names = "tdes_clk";
};

+ hsmc: hsmc@ffffc000 {
+ compatible = "atmel,sama5d3-smc", "syscon";
+ reg = <0xffffc000 0x1000>;
+ };
+
dma0: dma-controller@ffffe600 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffe600 0x200>;
--
1.9.1

2014-12-03 20:44:38

by Boris Brezillon

[permalink] [raw]

Subject: [PATCH v5 11/11] ARM: at91/dt: add NOR definition in sama5d3xcm dtsi

The sama5d3 evaluation kit embeds a NOR chip which is connected through
the EBI.
Define this NOR chip in the CPU module dtsi.

Signed-off-by: Boris Brezillon <[email protected]>
---
arch/arm/boot/dts/sama5d3xcm.dtsi | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index cfcd200..9ed3e4a 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -75,6 +75,39 @@
};
};

+ ebi@10000000 {
+ pinctrl-0 = <&pinctrl_ebi_addr &pinctrl_ebi_cs0>;
+
+ cs@0 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ atmel,read-mode = "nrd";
+ atmel,write-mode = "nwe";
+ atmel,bus-width = <16>;
+ atmel,ncs-rd-setup-ns = <0>;
+ atmel,ncs-wr-setup-ns = <0>;
+ atmel,nwe-setup-ns = <8>;
+ atmel,nrd-setup-ns = <16>;
+ atmel,ncs-rd-pulse-ns = <84>;
+ atmel,ncs-wr-pulse-ns = <84>;
+ atmel,nrd-pulse-ns = <76>;
+ atmel,nwe-pulse-ns = <76>;
+ atmel,nrd-cycle-ns = <107>;
+ atmel,nwe-cycle-ns = <84>;
+ atmel,tdf-ns = <16>;
+
+ nor: flash@0,0 {
+ compatible = "cfi-flash";
+ linux,mtd-name = "physmap-flash.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x0 0x1000000>;
+ bank-width = <2>;
+ };
+ };
+ };
+
nand0: nand@60000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
--
1.9.1

2014-12-03 20:45:03

by Boris Brezillon

[permalink] [raw]

Subject: [PATCH v5 10/11] ARM: at91/dt: add EBI (External Bus Interface) node in sama5d3 dtsi

Add EBI node and EBI pin muxing.

Signed-off-by: Boris Brezillon <[email protected]>
---
arch/arm/boot/dts/sama5d3.dtsi | 83 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 83 insertions(+)

diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index d49dab7..d011ade 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -530,6 +530,63 @@
};
};

+ ebi {
+ pinctrl_ebi_addr: ebi-addr-0 {
+ atmel,pins =
+ <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE
+ AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_cs0: ebi-cs0-0 {
+ atmel,pins =
+ <AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_cs1: ebi-cs1-0 {
+ atmel,pins =
+ <AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_cs2: ebi-cs2-0 {
+ atmel,pins =
+ <AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 {
+ atmel,pins =
+ <AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_ebi_nwait: ebi-nwait-0 {
+ atmel,pins =
+ <AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+ };
+ };
+
i2c0 {
pinctrl_i2c0: i2c0-0 {
atmel,pins =
@@ -1407,6 +1464,32 @@
status = "disabled";
};

+ ebi: ebi@10000000 {
+ compatible = "atmel,sama5d3-ebi", "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <&hsmc>;
+ atmel,matrix = <&matrix>;
+ reg = <0x10000000 0x10000000
+ 0x40000000 0x30000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x40000000 0x10000000
+ 0x2 0x0 0x50000000 0x10000000
+ 0x3 0x0 0x60000000 0x10000000>;
+ clocks = <&mck>;
+
+ /*
+ * TODO: EBI pins should be referenced here, but they
+ * conflict with NAND pins, which should actually be a
+ * sub device of the EBI bus and thus should not
+ * request it's own set of pins as they are shared
+ * with other devices connected on the EBI bus.
+ *
+ * pinctrl-names = "default";
+ * pinctrl-0 = <&pinctrl_ebi_addr>;
+ */
+ };
+
nand0: nand@60000000 {
compatible = "atmel,at91rm9200-nand";
#address-cells = <1>;
--
1.9.1

2014-12-03 20:44:34

by Boris Brezillon

[permalink] [raw]

Subject: [PATCH v5 06/11] memory: atmel-ebi: add DT bindings documentation

2014-12-03 20:45:57

by Boris Brezillon

[permalink] [raw]

Subject: [PATCH v5 09/11] ARM: at91/dt: add matrix node in sama5d3 dtsi

Add matrix node in sama5d3 dtsi so that it can be referenced by other
devices.

Signed-off-by: Boris Brezillon <[email protected]>
---
arch/arm/boot/dts/sama5d3.dtsi | 5 +++++
1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 9f1eed5..d49dab7 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -425,6 +425,11 @@
clock-names = "ddrck", "mpddr";
};

+ matrix: matrix@ffffec00 {
+ compatible = "atmel,sama5d3-matrix", "syscon";
+ reg = <0xffffec00 0x200>;
+ };
+
dbgu: serial@ffffee00 {
compatible = "atmel,at91sam9260-usart";
reg = <0xffffee00 0x200>;
--
1.9.1

2014-12-03 20:44:32

by Boris Brezillon

[permalink] [raw]

Subject: [PATCH v5 05/11] memory: add Atmel EBI (External Bus Interface) driver

The EBI (External Bus Interface) is used to access external peripherals
(NOR, SRAM, NAND, and other specific devices like ethernet controllers).
Each device is assigned a CS line and an address range and can have its
own configuration (timings, access mode, bus width, ...).
This driver provides a generic DT binding to configure a device according
to its requirements.
For specific device controllers (like the NAND one) the SMC timings
should be configured by the controller driver through the matrix and
smc syscon regmaps.

Signed-off-by: Jean-Jacques Hiblot <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
---
drivers/memory/Kconfig | 11 +
drivers/memory/Makefile | 1 +
drivers/memory/atmel-ebi.c | 579 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 591 insertions(+)
create mode 100644 drivers/memory/atmel-ebi.c

diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 6d91c27..dfe24a2 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -17,6 +17,17 @@ config ATMEL_SDRAMC
Starting with the at91sam9g45, this controller supports SDR, DDR and
LP-DDR memories.

+config ATMEL_EBI
+ bool "Atmel EBI driver"
+ default y
+ depends on ARCH_AT91 && OF
+ select MFD_SYSCON
+ help
+ Driver for Atmel EBI controller.
+ Used to configure the EBI (external bus interface) when the device-
+ tree is used. This bus supports NANDs, external ethernet controller,
+ SRAMs, ATA devices, etc.
+
config TI_AEMIF
tristate "Texas Instruments AEMIF driver"
depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index c32d319..7ca2c19 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -6,6 +6,7 @@ ifeq ($(CONFIG_DDR),y)
obj-$(CONFIG_OF) += of_memory.o
endif
obj-$(CONFIG_ATMEL_SDRAMC) += atmel-sdramc.o
+obj-$(CONFIG_ATMEL_EBI) += atmel-ebi.o
obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
obj-$(CONFIG_TI_EMIF) += emif.o
obj-$(CONFIG_FSL_CORENET_CF) += fsl-corenet-cf.o
diff --git a/drivers/memory/atmel-ebi.c b/drivers/memory/atmel-ebi.c
new file mode 100644
index 0000000..ff6bccd
--- /dev/null
+++ b/drivers/memory/atmel-ebi.c
@@ -0,0 +1,579 @@
+/*
+ * EBI driver for Atmel chips
+ * inspired by the fsl weim bus driver
+ *
+ * Copyright (C) 2013 JJ Hiblot.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/atmel-matrix.h>
+#include <linux/mfd/syscon/atmel-smc.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+
+struct at91sam9_smc_timings {
+ u32 ncs_rd_setup_ns;
+ u32 nrd_setup_ns;
+ u32 ncs_wr_setup_ns;
+ u32 nwe_setup_ns;
+ u32 ncs_rd_pulse_ns;
+ u32 nrd_pulse_ns;
+ u32 ncs_wr_pulse_ns;
+ u32 nwe_pulse_ns;
+ u32 nrd_cycle_ns;
+ u32 nwe_cycle_ns;
+ u32 tdf_ns;
+};
+
+struct at91sam9_smc_generic_fields {
+ struct regmap_field *setup;
+ struct regmap_field *pulse;
+ struct regmap_field *cycle;
+ struct regmap_field *mode;
+};
+
+struct at91sam9_ebi_dev_config {
+ struct at91sam9_smc_timings timings;
+ u32 mode;
+};
+
+struct at91_ebi;
+
+struct at91_ebi_dev {
+ struct device_node *np;
+ struct at91_smc_timings *timings;
+ struct at91_ebi *ebi;
+ u32 mode;
+ int cs;
+ void *config;
+};
+
+struct at91_ebi_caps {
+ unsigned int available_cs;
+ const struct reg_field *ebi_csa;
+ int (*xlate_config)(struct at91_ebi_dev *ebid);
+ int (*apply_config)(struct at91_ebi_dev *ebid);
+ int (*init)(struct at91_ebi *ebi);
+};
+
+struct at91_ebi {
+ struct clk *clk;
+ struct regmap *smc;
+ struct regmap *matrix;
+
+ struct regmap_field *ebi_csa;
+
+ struct device *dev;
+ const struct at91_ebi_caps *caps;
+ struct at91_ebi_dev *devs[AT91_MATRIX_EBI_NUM_CS];
+ void *priv;
+};
+
+static int at91sam9_ebi_apply_config(struct at91_ebi_dev *ebid)
+{
+ unsigned int clk_rate = clk_get_rate(ebid->ebi->clk);
+ struct at91sam9_ebi_dev_config *config = ebid->config;
+ struct at91sam9_smc_timings *timings = &config->timings;
+ struct at91sam9_smc_generic_fields *fields = ebid->ebi->priv;
+ u32 coded_val;
+ u32 val;
+
+ coded_val = at91sam9_smc_setup_ns_to_cycles(clk_rate,
+ timings->ncs_rd_setup_ns);
+ val = AT91SAM9_SMC_NCS_NRDSETUP(coded_val);
+ coded_val = at91sam9_smc_setup_ns_to_cycles(clk_rate,
+ timings->nrd_setup_ns);
+ val |= AT91SAM9_SMC_NRDSETUP(coded_val);
+ coded_val = at91sam9_smc_setup_ns_to_cycles(clk_rate,
+ timings->ncs_wr_setup_ns);
+ val |= AT91SAM9_SMC_NCS_WRSETUP(coded_val);
+ coded_val = at91sam9_smc_setup_ns_to_cycles(clk_rate,
+ timings->nwe_setup_ns);
+ val |= AT91SAM9_SMC_NWESETUP(coded_val);
+ regmap_fields_write(fields->setup, ebid->cs, val);
+
+ coded_val = at91sam9_smc_pulse_ns_to_cycles(clk_rate,
+ timings->ncs_rd_pulse_ns);
+ val = AT91SAM9_SMC_NCS_NRDPULSE(coded_val);
+ coded_val = at91sam9_smc_pulse_ns_to_cycles(clk_rate,
+ timings->nrd_pulse_ns);
+ val |= AT91SAM9_SMC_NRDPULSE(coded_val);
+ coded_val = at91sam9_smc_pulse_ns_to_cycles(clk_rate,
+ timings->ncs_wr_pulse_ns);
+ val |= AT91SAM9_SMC_NCS_WRPULSE(coded_val);
+ coded_val = at91sam9_smc_pulse_ns_to_cycles(clk_rate,
+ timings->nwe_pulse_ns);
+ val |= AT91SAM9_SMC_NWEPULSE(coded_val);
+ regmap_fields_write(fields->pulse, ebid->cs, val);
+
+ coded_val = at91sam9_smc_cycle_ns_to_cycles(clk_rate,
+ timings->nrd_cycle_ns);
+ val = AT91SAM9_SMC_NRDCYCLE(coded_val);
+ coded_val = at91sam9_smc_cycle_ns_to_cycles(clk_rate,
+ timings->nwe_cycle_ns);
+ val |= AT91SAM9_SMC_NWECYCLE(coded_val);
+ regmap_fields_write(fields->cycle, ebid->cs, val);
+
+ val = DIV_ROUND_UP(timings->tdf_ns, clk_rate);
+ if (val > AT91_SMC_TDF_MAX)
+ val = AT91_SMC_TDF_MAX;
+ regmap_fields_write(fields->mode, ebid->cs,
+ config->mode | AT91_SMC_TDF_(val));
+
+ return 0;
+}
+
+static int at91sam9_smc_xslate_timings(struct at91_ebi_dev *ebid)
+{
+ struct at91sam9_ebi_dev_config *config = ebid->config;
+ struct at91sam9_smc_timings *timings;
+ struct device_node *np = ebid->np;
+
+ timings = &config->timings;
+
+ of_property_read_u32(np, "atmel,ncs-rd-setup-ns",
+ &timings->ncs_rd_setup_ns);
+ of_property_read_u32(np, "atmel,nrd-setup-ns",
+ &timings->nrd_setup_ns);
+ of_property_read_u32(np, "atmel,ncs-wr-setup-ns",
+ &timings->ncs_wr_setup_ns);
+ of_property_read_u32(np, "atmel,nwe-setup-ns",
+ &timings->nwe_setup_ns);
+ of_property_read_u32(np, "atmel,ncs-rd-pulse-ns",
+ &timings->ncs_rd_pulse_ns);
+ of_property_read_u32(np, "atmel,nrd-pulse-ns",
+ &timings->nrd_pulse_ns);
+ of_property_read_u32(np, "atmel,ncs-wr-pulse-ns",
+ &timings->ncs_wr_pulse_ns);
+ of_property_read_u32(np, "atmel,nwe-pulse-ns", &timings->nwe_pulse_ns);
+ of_property_read_u32(np, "atmel,nwe-cycle-ns", &timings->nwe_cycle_ns);
+ of_property_read_u32(np, "atmel,nrd-cycle-ns", &timings->nrd_cycle_ns);
+ of_property_read_u32(np, "atmel,tdf-ns", &timings->tdf_ns);
+
+ return 0;
+}
+
+static int at91sam9_ebi_xslate_config(struct at91_ebi_dev *ebid)
+{
+ struct at91sam9_ebi_dev_config *config = ebid->config;
+ struct device_node *np = ebid->np;
+ const char *tmp_str;
+ u32 tmp;
+ int ret;
+
+ config = devm_kzalloc(ebid->ebi->dev, sizeof(*config), GFP_KERNEL);
+ if (!config)
+ return -ENOMEM;
+
+ ebid->config = config;
+
+ ret = of_property_read_u32(np, "atmel,bus-width", &tmp);
+ if (ret)
+ return ret;
+
+ switch (tmp) {
+ case 8:
+ config->mode |= AT91_SMC_DBW_8;
+ break;
+
+ case 16:
+ config->mode |= AT91_SMC_DBW_16;
+ break;
+
+ case 32:
+ config->mode |= AT91_SMC_DBW_32;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ if (of_property_read_bool(np, "atmel,tdf-optimized"))
+ config->mode |= AT91_SMC_TDFMODE_OPTIMIZED;
+
+ tmp_str = NULL;
+ of_property_read_string(np, "atmel,byte-access-type", &tmp_str);
+ if (tmp_str && !strcmp(tmp_str, "write"))
+ config->mode |= AT91_SMC_BAT_WRITE;
+
+ tmp_str = NULL;
+ of_property_read_string(np, "atmel,read-mode", &tmp_str);
+ if (tmp_str && !strcmp(tmp_str, "nrd"))
+ config->mode |= AT91_SMC_READMODE_NRD;
+
+ tmp_str = NULL;
+ of_property_read_string(np, "atmel,write-mode", &tmp_str);
+ if (tmp_str && !strcmp(tmp_str, "nwe"))
+ config->mode |= AT91_SMC_WRITEMODE_NWE;
+
+ tmp_str = NULL;
+ of_property_read_string(np, "atmel,exnw-mode", &tmp_str);
+ if (tmp_str) {
+ if (!strcmp(tmp_str, "frozen"))
+ config->mode |= AT91_SMC_EXNWMODE_FROZEN;
+ else if (!strcmp(tmp_str, "ready"))
+ config->mode |= AT91_SMC_EXNWMODE_READY;
+ }
+
+ tmp = 0;
+ ret = of_property_read_u32(np, "atmel,page-mode", &tmp);
+ if (!ret) {
+ switch (tmp) {
+ case 4:
+ config->mode |= AT91_SMC_PS_4;
+ break;
+
+ case 8:
+ config->mode |= AT91_SMC_PS_8;
+ break;
+
+ case 16:
+ config->mode |= AT91_SMC_PS_16;
+ break;
+
+ case 32:
+ config->mode |= AT91_SMC_PS_32;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ config->mode |= AT91_SMC_PMEN;
+ }
+
+ return at91sam9_smc_xslate_timings(ebid);
+}
+
+static int at91sam9_ebi_init(struct at91_ebi *ebi)
+{
+ struct at91sam9_smc_generic_fields *fields;
+ struct reg_field field = REG_FIELD(0, 0, 31);
+
+ fields = devm_kzalloc(ebi->dev, sizeof(*fields), GFP_KERNEL);
+ if (!fields)
+ return -ENOMEM;
+
+ field.id_size = fls(ebi->caps->available_cs);
+ field.id_offset = AT91SAM9_SMC_GENERIC_BLK_SZ;
+
+ field.reg = AT91SAM9_SMC_SETUP(AT91SAM9_SMC_GENERIC);
+ fields->setup = devm_regmap_field_alloc(ebi->dev, ebi->smc, field);
+ if (IS_ERR(fields->setup))
+ return PTR_ERR(fields->setup);
+
+ field.reg = AT91SAM9_SMC_PULSE(AT91SAM9_SMC_GENERIC);
+ fields->pulse = devm_regmap_field_alloc(ebi->dev, ebi->smc, field);
+ if (IS_ERR(fields->pulse))
+ return PTR_ERR(fields->pulse);
+
+ field.reg = AT91SAM9_SMC_CYCLE(AT91SAM9_SMC_GENERIC);
+ fields->cycle = devm_regmap_field_alloc(ebi->dev, ebi->smc, field);
+ if (IS_ERR(fields->cycle))
+ return PTR_ERR(fields->cycle);
+
+ field.reg = AT91SAM9_SMC_MODE(AT91SAM9_SMC_GENERIC);
+ fields->mode = devm_regmap_field_alloc(ebi->dev, ebi->smc, field);
+ if (IS_ERR(fields->mode))
+ return PTR_ERR(fields->mode);
+
+ ebi->priv = fields;
+
+ return 0;
+}
+
+static int sama5d3_ebi_init(struct at91_ebi *ebi)
+{
+ struct at91sam9_smc_generic_fields *fields;
+ struct reg_field field = REG_FIELD(0, 0, 31);
+
+ fields = devm_kzalloc(ebi->dev, sizeof(*fields), GFP_KERNEL);
+ if (!fields)
+ return -ENOMEM;
+
+ field.id_size = fls(ebi->caps->available_cs);
+ field.id_offset = SAMA5_SMC_GENERIC_BLK_SZ;
+
+ field.reg = AT91SAM9_SMC_SETUP(SAMA5_SMC_GENERIC);
+ fields->setup = devm_regmap_field_alloc(ebi->dev, ebi->smc, field);
+ if (IS_ERR(fields->setup))
+ return PTR_ERR(fields->setup);
+
+ field.reg = AT91SAM9_SMC_PULSE(SAMA5_SMC_GENERIC);
+ fields->pulse = devm_regmap_field_alloc(ebi->dev, ebi->smc, field);
+ if (IS_ERR(fields->pulse))
+ return PTR_ERR(fields->pulse);
+
+ field.reg = AT91SAM9_SMC_CYCLE(SAMA5_SMC_GENERIC);
+ fields->cycle = devm_regmap_field_alloc(ebi->dev, ebi->smc, field);
+ if (IS_ERR(fields->cycle))
+ return PTR_ERR(fields->cycle);
+
+ field.reg = SAMA5_SMC_MODE(SAMA5_SMC_GENERIC);
+ fields->mode = devm_regmap_field_alloc(ebi->dev, ebi->smc, field);
+ if (IS_ERR(fields->mode))
+ return PTR_ERR(fields->mode);
+
+ ebi->priv = fields;
+
+ return 0;
+}
+
+static int at91_ebi_dev_setup(struct at91_ebi *ebi, struct device_node *np)
+{
+ struct device *dev = ebi->dev;
+ struct device_node *dev_np;
+ struct at91_ebi_dev *ebid;
+ u32 tmp;
+ int ret;
+
+ dev_np = of_get_next_child(np, NULL);
+ if (!dev_np)
+ return -EINVAL;
+
+ if (!of_device_is_available(dev_np))
+ return 0;
+
+ ebid = devm_kzalloc(ebi->dev, sizeof(*ebid), GFP_KERNEL);
+ if (!ebid)
+ return -ENOMEM;
+
+ ret = of_property_read_u32(dev_np, "reg" , &tmp);
+ if (ret < 0) {
+ dev_err(dev, "missing mandatory reg property\n");
+ return ret;
+ }
+
+ if (tmp > AT91_MATRIX_EBI_NUM_CS ||
+ !(BIT(tmp) & ebi->caps->available_cs)) {
+ dev_err(dev, "invalid reg property\n");
+ return -EINVAL;
+ }
+
+ ebid->cs = tmp;
+ ebid->np = np;
+ ebid->ebi = ebi;
+
+ if (of_property_read_bool(np, "atmel,specialized-logic"))
+ goto populate;
+
+ if (ebid->ebi->ebi_csa)
+ regmap_field_update_bits(ebid->ebi->ebi_csa,
+ BIT(ebid->cs),
+ ~BIT(ebid->cs));
+
+ ret = ebid->ebi->caps->xlate_config(ebid);
+ if (ret)
+ return ret;
+
+ ret = ebid->ebi->caps->apply_config(ebid);
+ if (ret)
+ return ret;
+ ebi->devs[ebid->cs] = ebid;
+
+populate:
+ return of_platform_populate(np, of_default_bus_match_table, NULL, dev);
+}
+
+static const struct reg_field at91sam9260_ebi_csa =
+ REG_FIELD(AT91SAM9260_MATRIX_EBICSA, 0,
+ AT91_MATRIX_EBI_NUM_CS - 1);
+
+static const struct at91_ebi_caps at91sam9260_ebi_caps = {
+ .available_cs = 0xff,
+ .ebi_csa = &at91sam9260_ebi_csa,
+ .xlate_config = at91sam9_ebi_xslate_config,
+ .apply_config = at91sam9_ebi_apply_config,
+ .init = at91sam9_ebi_init,
+};
+
+static const struct reg_field at91sam9261_ebi_csa =
+ REG_FIELD(AT91SAM9261_MATRIX_EBICSA, 0,
+ AT91_MATRIX_EBI_NUM_CS - 1);
+
+static const struct at91_ebi_caps at91sam9261_ebi_caps = {
+ .available_cs = 0xff,
+ .ebi_csa = &at91sam9261_ebi_csa,
+ .xlate_config = at91sam9_ebi_xslate_config,
+ .apply_config = at91sam9_ebi_apply_config,
+ .init = at91sam9_ebi_init,
+};
+
+static const struct reg_field at91sam9263_ebi0_csa =
+ REG_FIELD(AT91SAM9263_MATRIX_EBI0CSA, 0,
+ AT91_MATRIX_EBI_NUM_CS - 1);
+
+static const struct at91_ebi_caps at91sam9263_ebi0_caps = {
+ .available_cs = 0x3f,
+ .ebi_csa = &at91sam9263_ebi0_csa,
+ .xlate_config = at91sam9_ebi_xslate_config,
+ .apply_config = at91sam9_ebi_apply_config,
+ .init = at91sam9_ebi_init,
+};
+
+static const struct reg_field at91sam9263_ebi1_csa =
+ REG_FIELD(AT91SAM9263_MATRIX_EBI1CSA, 0,
+ AT91_MATRIX_EBI_NUM_CS - 1);
+
+static const struct at91_ebi_caps at91sam9263_ebi1_caps = {
+ .available_cs = 0x7,
+ .ebi_csa = &at91sam9263_ebi1_csa,
+ .xlate_config = at91sam9_ebi_xslate_config,
+ .apply_config = at91sam9_ebi_apply_config,
+ .init = at91sam9_ebi_init,
+};
+
+static const struct reg_field at91sam9rl_ebi_csa =
+ REG_FIELD(AT91SAM9RL_MATRIX_EBICSA, 0,
+ AT91_MATRIX_EBI_NUM_CS - 1);
+
+static const struct at91_ebi_caps at91sam9rl_ebi_caps = {
+ .available_cs = 0x3f,
+ .ebi_csa = &at91sam9rl_ebi_csa,
+ .xlate_config = at91sam9_ebi_xslate_config,
+ .apply_config = at91sam9_ebi_apply_config,
+ .init = at91sam9_ebi_init,
+};
+
+static const struct reg_field at91sam9g45_ebi_csa =
+ REG_FIELD(AT91SAM9G45_MATRIX_EBICSA, 0,
+ AT91_MATRIX_EBI_NUM_CS - 1);
+
+static const struct at91_ebi_caps at91sam9g45_ebi_caps = {
+ .available_cs = 0x3f,
+ .ebi_csa = &at91sam9g45_ebi_csa,
+ .xlate_config = at91sam9_ebi_xslate_config,
+ .apply_config = at91sam9_ebi_apply_config,
+ .init = at91sam9_ebi_init,
+};
+
+static const struct at91_ebi_caps at91sam9x5_ebi_caps = {
+ .available_cs = 0x3f,
+ .ebi_csa = &at91sam9263_ebi0_csa,
+ .xlate_config = at91sam9_ebi_xslate_config,
+ .apply_config = at91sam9_ebi_apply_config,
+ .init = at91sam9_ebi_init,
+};
+
+static const struct at91_ebi_caps sama5d3_ebi_caps = {
+ .available_cs = 0xf,
+ .xlate_config = at91sam9_ebi_xslate_config,
+ .apply_config = at91sam9_ebi_apply_config,
+ .init = sama5d3_ebi_init,
+};
+
+static const struct of_device_id at91_ebi_id_table[] = {
+ {
+ .compatible = "atmel,at91sam9260-ebi",
+ .data = &at91sam9260_ebi_caps,
+ },
+ {
+ .compatible = "atmel,at91sam9261-ebi",
+ .data = &at91sam9261_ebi_caps,
+ },
+ {
+ .compatible = "atmel,at91sam9263-ebi0",
+ .data = &at91sam9263_ebi0_caps,
+ },
+ {
+ .compatible = "atmel,at91sam9263-ebi1",
+ .data = &at91sam9263_ebi1_caps,
+ },
+ {
+ .compatible = "atmel,at91sam9rl-ebi",
+ .data = &at91sam9rl_ebi_caps,
+ },
+ {
+ .compatible = "atmel,at91sam9g45-ebi",
+ .data = &at91sam9g45_ebi_caps,
+ },
+ {
+ .compatible = "atmel,at91sam9x5-ebi",
+ .data = &at91sam9x5_ebi_caps,
+ },
+ {
+ .compatible = "atmel,sama5d3-ebi",
+ .data = &sama5d3_ebi_caps,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, at91_ebi_id_table);
+
+static int at91_ebi_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+ struct device_node *child;
+ struct at91_ebi *ebi;
+ struct clk *clk;
+ int ret;
+
+ match = of_match_device(at91_ebi_id_table, &pdev->dev);
+ if (!match || !match->data)
+ return -EINVAL;
+
+ ebi = devm_kzalloc(&pdev->dev, sizeof(*ebi), GFP_KERNEL);
+ if (!ebi)
+ return -ENOMEM;
+
+ ebi->caps = match->data;
+ ebi->dev = &pdev->dev;
+
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ ebi->clk = clk;
+
+ ebi->smc = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "atmel,smc");
+ if (IS_ERR(ebi->smc))
+ return PTR_ERR(ebi->smc);
+
+ /*
+ * The sama5d3 does not provide an EBICSA register and thus does need
+ * to access the matrix registers.
+ */
+ if (ebi->caps->ebi_csa) {
+ ebi->matrix =
+ syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "atmel,matrix");
+ if (IS_ERR(ebi->matrix))
+ return PTR_ERR(ebi->matrix);
+
+ ebi->ebi_csa = regmap_field_alloc(ebi->matrix,
+ *ebi->caps->ebi_csa);
+ if (IS_ERR(ebi->ebi_csa))
+ return PTR_ERR(ebi->ebi_csa);
+ }
+
+ ret = ebi->caps->init(ebi);
+ if (ret)
+ return ret;
+
+ for_each_child_of_node(pdev->dev.of_node, child) {
+ ret = at91_ebi_dev_setup(ebi, child);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
+static struct platform_driver at91_ebi_driver = {
+ .driver = {
+ .name = "atmel-ebi",
+ .of_match_table = at91_ebi_id_table,
+ },
+};
+module_platform_driver_probe(at91_ebi_driver, at91_ebi_probe);
+
+MODULE_AUTHOR("JJ Hiblot");
+MODULE_DESCRIPTION("Atmel's EBI driver");
+MODULE_LICENSE("GPL");
--
1.9.1

2014-12-03 20:46:47

by Boris Brezillon

[permalink] [raw]

Subject: [PATCH v5 07/11] ARM: at91: select ATMEL_EBI when compiling a kernel for at91sam9 or sama5d3

at91sam9* and sama5d* SoCs have an EBI (External Bus Interface).
Select the ATMEL_EBI driver when support for these SoCs is selected.

Signed-off-by: Boris Brezillon <[email protected]>
---
.../bindings/memory-controllers/atmel-ebi.txt | 18 +++++++++---------
arch/arm/mach-at91/Kconfig | 2 ++
2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt
index 3749ea1..68af1ad 100644
--- a/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt
@@ -16,6 +16,7 @@ Required properties:
"atmel,at91sam9261-ebi"
"atmel,at91sam9263-ebi0"
"atmel,at91sam9263-ebi1"
+ "atmel,at91sam9rl-ebi"
"atmel,at91sam9g45-ebi"
"atmel,at91sam9x5-ebi"
"atmel,sama5d3-ebi"
@@ -51,15 +52,14 @@ Required child cs node properties:
memory layout.

Optional child cs node properties:
-- atmel,generic-dev boolean property specifying if the device is
- a generic device.
+- atmel,specialized-logic boolean property specifying if the device is
+ a connected to a specialized logic:
+ NAND, Compact Flash, SDR-SDRAM.
The following properties are only parsed if
- this property is present.
- Specialized devices are attached to specialized
- controllers which are responsible for
- configuring the bus appropriately.
- Here are some examples of specialized
- controllers: NAND, CompactFlash, SDR-SDRAM.
+ this property is absent.
+ If this property is set, specialized controller
+ drivers are responsible for configuring the bus
+ appropriately.

- atmel,bus-width: width of the asynchronous device's data bus
8, 16 or 32.
@@ -99,7 +99,7 @@ present 0 is assumed):
- atmel,tdf-optimized data float optimized mode. If present the data
float time is optimized depending on the next
device being accessed (next device setup
- time is substracted to the current devive data
+ time is subtracted to the current device data
float time).

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0e6d548..78b1412 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -49,6 +49,7 @@ config SOC_AT91SAM9
select GENERIC_CLOCKEVENTS
select MEMORY if USE_OF
select ATMEL_SDRAMC if USE_OF
+ select ATMEL_EBI

config SOC_SAMA5
bool
@@ -58,6 +59,7 @@ config SOC_SAMA5
select USE_OF
select MEMORY
select ATMEL_SDRAMC
+ select ATMEL_EBI

menu "Atmel AT91 System-on-Chip"

--
1.9.1

2014-12-03 20:44:29

by Boris Brezillon

[permalink] [raw]

Subject: [PATCH v5 02/11] mfd: syscon: Add Atmel Matrix bus DT binding documentation

The Matrix registers are provided to configure internal bus behavior on
at91 SoCs.
Some registers might be accessed by several drivers (e.g. to configure
external memory bus timings), hence we declare this register set as a
syscon device.

Signed-off-by: Boris Brezillon <[email protected]>
Acked-by: Lee Jones <[email protected]>
---
.../devicetree/bindings/mfd/atmel-matrix.txt | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/atmel-matrix.txt

diff --git a/Documentation/devicetree/bindings/mfd/atmel-matrix.txt b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt
new file mode 100644
index 0000000..e3ef50c
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/atmel-matrix.txt
@@ -0,0 +1,24 @@
+* Device tree bindings for Atmel Bus Matrix
+
+The Bus Matrix registers are used to configure Atmel SoCs internal bus
+behavior (master/slave priorities, undefined burst length type, ...)
+
+Required properties:
+- compatible: Should be one of the following
+ "atmel,at91sam9260-matrix", "syscon"
+ "atmel,at91sam9261-matrix", "syscon"
+ "atmel,at91sam9263-matrix", "syscon"
+ "atmel,at91sam9rl-matrix", "syscon"
+ "atmel,at91sam9g45-matrix", "syscon"
+ "atmel,at91sam9n12-matrix", "syscon"
+ "atmel,at91sam9x5-matrix", "syscon"
+ "atmel,sama5d3-matrix", "syscon"
+- reg: Contains offset/length value of the Bus Matrix
+ memory region.
+
+Example:
+
+matrix: matrix@ffffec00 {
+ compatible = "atmel,sama5d3-matrix", "syscon";
+ reg = <0xffffec00 0x200>;
+};
--
1.9.1

2014-12-03 20:47:13

by Boris Brezillon

[permalink] [raw]

Subject: [PATCH v5 04/11] mfd: syscon: Add Atmel SMC binding doc

The SMC registers are used to configure Atmel EBI (External Bus Interface)
to interface with standard memory devices (NAND, NOR, SRAM or specialized
devices like FPGAs).

Declare this memory region as a syscon, so that different drivers can
configure the SMC interface (mostly timing configuration) according to
their need.

Signed-off-by: Boris Brezillon <[email protected]>
Acked-by: Lee Jones <[email protected]>
---
Documentation/devicetree/bindings/mfd/atmel-smc.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/atmel-smc.txt

diff --git a/Documentation/devicetree/bindings/mfd/atmel-smc.txt b/Documentation/devicetree/bindings/mfd/atmel-smc.txt
new file mode 100644
index 0000000..26eeed3
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/atmel-smc.txt
@@ -0,0 +1,19 @@
+* Device tree bindings for Atmel SMC (Static Memory Controller)
+
+The SMC registers are used to configure Atmel EBI (External Bus Interface)
+to interface with standard memory devices (NAND, NOR, SRAM or specialized
+devices like FPGAs).
+
+Required properties:
+- compatible: Should be one of the following
+ "atmel,at91sam9260-smc", "syscon"
+ "atmel,sama5d3-smc", "syscon"
+- reg: Contains offset/length value of the SMC memory
+ region.
+
+Example:
+
+smc: smc@ffffc000 {
+ compatible = "atmel,sama5d3-smc", "syscon";
+ reg = <0xffffc000 0x1000>;
+};
--
1.9.1

2014-12-03 20:47:36

by Boris Brezillon

[permalink] [raw]

Subject: [PATCH v5 03/11] mfd: syscon: Add atmel-smc registers definition

Atmel AT91 SoCs have a memory range reserved for SMC (Static Memory
Controller) configuration.
Expose those registers so that drivers can make use of the smc syscon
declared in at91 DTs.

Signed-off-by: Boris Brezillon <[email protected]>
Acked-by: Lee Jones <[email protected]>
---
include/linux/mfd/syscon/atmel-smc.h | 173 +++++++++++++++++++++++++++++++++++
1 file changed, 173 insertions(+)
create mode 100644 include/linux/mfd/syscon/atmel-smc.h

diff --git a/include/linux/mfd/syscon/atmel-smc.h b/include/linux/mfd/syscon/atmel-smc.h
new file mode 100644
index 0000000..be6ebe6
--- /dev/null
+++ b/include/linux/mfd/syscon/atmel-smc.h
@@ -0,0 +1,173 @@
+/*
+ * Atmel SMC (Static Memory Controller) register offsets and bit definitions.
+ *
+ * Copyright (C) 2014 Atmel
+ * Copyright (C) 2014 Free Electrons
+ *
+ * Author: Boris Brezillon <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _LINUX_MFD_SYSCON_ATMEL_SMC_H_
+#define _LINUX_MFD_SYSCON_ATMEL_SMC_H_
+
+#include <linux/kernel.h>
+#include <linux/regmap.h>
+
+#define AT91SAM9_SMC_GENERIC 0x00
+#define AT91SAM9_SMC_GENERIC_BLK_SZ 0x10
+
+#define SAMA5_SMC_GENERIC 0x600
+#define SAMA5_SMC_GENERIC_BLK_SZ 0x14
+
+#define AT91SAM9_SMC_SETUP(o) ((o) + 0x00)
+#define AT91SAM9_SMC_NWESETUP(x) (x)
+#define AT91SAM9_SMC_NCS_WRSETUP(x) ((x) << 8)
+#define AT91SAM9_SMC_NRDSETUP(x) ((x) << 16)
+#define AT91SAM9_SMC_NCS_NRDSETUP(x) ((x) << 24)
+
+#define AT91SAM9_SMC_PULSE(o) ((o) + 0x04)
+#define AT91SAM9_SMC_NWEPULSE(x) (x)
+#define AT91SAM9_SMC_NCS_WRPULSE(x) ((x) << 8)
+#define AT91SAM9_SMC_NRDPULSE(x) ((x) << 16)
+#define AT91SAM9_SMC_NCS_NRDPULSE(x) ((x) << 24)
+
+#define AT91SAM9_SMC_CYCLE(o) ((o) + 0x08)
+#define AT91SAM9_SMC_NWECYCLE(x) (x)
+#define AT91SAM9_SMC_NRDCYCLE(x) ((x) << 16)
+
+#define AT91SAM9_SMC_MODE(o) ((o) + 0x0c)
+#define SAMA5_SMC_MODE(o) ((o) + 0x10)
+#define AT91_SMC_READMODE BIT(0)
+#define AT91_SMC_READMODE_NCS (0 << 0)
+#define AT91_SMC_READMODE_NRD (1 << 0)
+#define AT91_SMC_WRITEMODE BIT(1)
+#define AT91_SMC_WRITEMODE_NCS (0 << 1)
+#define AT91_SMC_WRITEMODE_NWE (1 << 1)
+#define AT91_SMC_EXNWMODE GENMASK(5, 4)
+#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
+#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
+#define AT91_SMC_EXNWMODE_READY (3 << 4)
+#define AT91_SMC_BAT BIT(8)
+#define AT91_SMC_BAT_SELECT (0 << 8)
+#define AT91_SMC_BAT_WRITE (1 << 8)
+#define AT91_SMC_DBW GENMASK(13, 12)
+#define AT91_SMC_DBW_8 (0 << 12)
+#define AT91_SMC_DBW_16 (1 << 12)
+#define AT91_SMC_DBW_32 (2 << 12)
+#define AT91_SMC_TDF GENMASK(19, 16)
+#define AT91_SMC_TDF_(x) ((((x) - 1) << 16) & AT91_SMC_TDF)
+#define AT91_SMC_TDF_MAX 16
+#define AT91_SMC_TDFMODE_OPTIMIZED BIT(20)
+#define AT91_SMC_PMEN BIT(24)
+#define AT91_SMC_PS GENMASK(29, 28)
+#define AT91_SMC_PS_4 (0 << 28)
+#define AT91_SMC_PS_8 (1 << 28)
+#define AT91_SMC_PS_16 (2 << 28)
+#define AT91_SMC_PS_32 (3 << 28)
+
+
+/*
+ * This function converts a setup timing expressed in nanoseconds into an
+ * encoded value that can be written in the SMC_SETUP register.
+ *
+ * The following formula is described in atmel datasheets (section
+ * "SMC Setup Register"):
+ *
+ * setup length = (128* SETUP[5] + SETUP[4:0])
+ *
+ * where setup length is the timing expressed in cycles.
+ */
+static inline u32 at91sam9_smc_setup_ns_to_cycles(unsigned int clk_rate,
+ u32 timing_ns)
+{
+ u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate);
+ u32 coded_cycles = 0;
+ u32 cycles;
+
+ cycles = DIV_ROUND_UP(timing_ns, clk_period);
+ if (cycles / 32) {
+ coded_cycles |= 1 << 5;
+ if (cycles < 128)
+ cycles = 0;
+ }
+
+ coded_cycles |= cycles % 32;
+
+ return coded_cycles;
+}
+
+/*
+ * This function converts a pulse timing expressed in nanoseconds into an
+ * encoded value that can be written in the SMC_PULSE register.
+ *
+ * The following formula is described in atmel datasheets (section
+ * "SMC Pulse Register"):
+ *
+ * pulse length = (256* PULSE[6] + PULSE[5:0])
+ *
+ * where pulse length is the timing expressed in cycles.
+ */
+static inline u32 at91sam9_smc_pulse_ns_to_cycles(unsigned int clk_rate,
+ u32 timing_ns)
+{
+ u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate);
+ u32 coded_cycles = 0;
+ u32 cycles;
+
+ cycles = DIV_ROUND_UP(timing_ns, clk_period);
+ if (cycles / 64) {
+ coded_cycles |= 1 << 6;
+ if (cycles < 256)
+ cycles = 0;
+ }
+
+ coded_cycles |= cycles % 64;
+
+ return coded_cycles;
+}
+
+/*
+ * This function converts a cycle timing expressed in nanoseconds into an
+ * encoded value that can be written in the SMC_CYCLE register.
+ *
+ * The following formula is described in atmel datasheets (section
+ * "SMC Cycle Register"):
+ *
+ * cycle length = (CYCLE[8:7]*256 + CYCLE[6:0])
+ *
+ * where cycle length is the timing expressed in cycles.
+ */
+static inline u32 at91sam9_smc_cycle_ns_to_cycles(unsigned int clk_rate,
+ u32 timing_ns)
+{
+ u32 clk_period = DIV_ROUND_UP(NSEC_PER_SEC, clk_rate);
+ u32 coded_cycles = 0;
+ u32 cycles;
+
+ cycles = DIV_ROUND_UP(timing_ns, clk_period);
+ if (cycles / 128) {
+ coded_cycles = cycles / 256;
+ cycles %= 256;
+ if (cycles >= 128) {
+ coded_cycles++;
+ cycles = 0;
+ }
+
+ if (coded_cycles > 0x3) {
+ coded_cycles = 0x3;
+ cycles = 0x7f;
+ }
+
+ coded_cycles <<= 7;
+ }
+
+ coded_cycles |= cycles % 128;
+
+ return coded_cycles;
+}
+
+#endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */
--
1.9.1

2014-12-03 20:47:58

by Boris Brezillon

[permalink] [raw]

Subject: [PATCH v5 01/11] mfd: syscon: Add atmel-matrix registers definition

AT91 SoCs have a memory range reserved for internal bus configuration.
Expose those registers so that drivers can make use of the matrix syscon
declared in at91 DTs.

Signed-off-by: Boris Brezillon <[email protected]>
Acked-by: Lee Jones <[email protected]>
---
include/linux/mfd/syscon/atmel-matrix.h | 117 ++++++++++++++++++++++++++++++++
1 file changed, 117 insertions(+)
create mode 100644 include/linux/mfd/syscon/atmel-matrix.h

diff --git a/include/linux/mfd/syscon/atmel-matrix.h b/include/linux/mfd/syscon/atmel-matrix.h
new file mode 100644
index 0000000..8293c3e
--- /dev/null
+++ b/include/linux/mfd/syscon/atmel-matrix.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2014 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _LINUX_MFD_SYSCON_ATMEL_MATRIX_H
+#define _LINUX_MFD_SYSCON_ATMEL_MATRIX_H
+
+#define AT91SAM9260_MATRIX_MCFG 0x00
+#define AT91SAM9260_MATRIX_SCFG 0x40
+#define AT91SAM9260_MATRIX_PRS 0x80
+#define AT91SAM9260_MATRIX_MRCR 0x100
+#define AT91SAM9260_MATRIX_EBICSA 0x11c
+
+#define AT91SAM9261_MATRIX_MRCR 0x0
+#define AT91SAM9261_MATRIX_SCFG 0x4
+#define AT91SAM9261_MATRIX_TCR 0x24
+#define AT91SAM9261_MATRIX_EBICSA 0x30
+#define AT91SAM9261_MATRIX_USBPUCR 0x34
+
+#define AT91SAM9263_MATRIX_MCFG 0x00
+#define AT91SAM9263_MATRIX_SCFG 0x40
+#define AT91SAM9263_MATRIX_PRS 0x80
+#define AT91SAM9263_MATRIX_MRCR 0x100
+#define AT91SAM9263_MATRIX_TCR 0x114
+#define AT91SAM9263_MATRIX_EBI0CSA 0x120
+#define AT91SAM9263_MATRIX_EBI1CSA 0x124
+
+#define AT91SAM9RL_MATRIX_MCFG 0x00
+#define AT91SAM9RL_MATRIX_SCFG 0x40
+#define AT91SAM9RL_MATRIX_PRS 0x80
+#define AT91SAM9RL_MATRIX_MRCR 0x100
+#define AT91SAM9RL_MATRIX_TCR 0x114
+#define AT91SAM9RL_MATRIX_EBICSA 0x120
+
+#define AT91SAM9G45_MATRIX_MCFG 0x00
+#define AT91SAM9G45_MATRIX_SCFG 0x40
+#define AT91SAM9G45_MATRIX_PRS 0x80
+#define AT91SAM9G45_MATRIX_MRCR 0x100
+#define AT91SAM9G45_MATRIX_TCR 0x110
+#define AT91SAM9G45_MATRIX_DDRMPR 0x118
+#define AT91SAM9G45_MATRIX_EBICSA 0x128
+
+#define AT91SAM9N12_MATRIX_MCFG 0x00
+#define AT91SAM9N12_MATRIX_SCFG 0x40
+#define AT91SAM9N12_MATRIX_PRS 0x80
+#define AT91SAM9N12_MATRIX_MRCR 0x100
+#define AT91SAM9N12_MATRIX_EBICSA 0x118
+
+#define AT91SAM9X5_MATRIX_MCFG 0x00
+#define AT91SAM9X5_MATRIX_SCFG 0x40
+#define AT91SAM9X5_MATRIX_PRS 0x80
+#define AT91SAM9X5_MATRIX_MRCR 0x100
+#define AT91SAM9X5_MATRIX_EBICSA 0x120
+
+#define SAMA5D3_MATRIX_MCFG 0x00
+#define SAMA5D3_MATRIX_SCFG 0x40
+#define SAMA5D3_MATRIX_PRS 0x80
+#define SAMA5D3_MATRIX_MRCR 0x100
+
+#define AT91_MATRIX_MCFG(o, x) ((o) + ((x) * 0x4))
+#define AT91_MATRIX_ULBT GENMASK(2, 0)
+#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+
+#define AT91_MATRIX_SCFG(o, x) ((o) + ((x) * 0x4))
+#define AT91_MATRIX_SLOT_CYCLE GENMASK(7, 0)
+#define AT91_MATRIX_DEFMSTR_TYPE GENMASK(17, 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR GENMASK(20, 18)
+#define AT91_MATRIX_ARBT GENMASK(25, 24)
+#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_ITCM_SIZE GENMASK(3, 0)
+#define AT91_MATRIX_ITCM_0 (0 << 0)
+#define AT91_MATRIX_ITCM_16 (5 << 0)
+#define AT91_MATRIX_ITCM_32 (6 << 0)
+#define AT91_MATRIX_ITCM_64 (7 << 0)
+#define AT91_MATRIX_DTCM_SIZE GENMASK(7, 4)
+#define AT91_MATRIX_DTCM_0 (0 << 4)
+#define AT91_MATRIX_DTCM_16 (5 << 4)
+#define AT91_MATRIX_DTCM_32 (6 << 4)
+#define AT91_MATRIX_DTCM_64 (7 << 4)
+
+#define AT91_MATRIX_PRAS(o, x) ((o) + ((x) * 0x8))
+#define AT91_MATRIX_PRBS(o, x) ((o) + ((x) * 0x8) + 0x4)
+#define AT91_MATRIX_MPR(x) GENMASK(((x) * 0x4) + 1, ((x) * 0x4))
+
+#define AT91_MATRIX_RCB(x) BIT(x)
+
+#define AT91_MATRIX_CSA(cs, val) (val << (cs))
+#define AT91_MATRIX_DBPUC BIT(8)
+#define AT91_MATRIX_DBPDC BIT(9)
+#define AT91_MATRIX_VDDIOMSEL BIT(16)
+#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
+#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
+#define AT91_MATRIX_EBI_IOSR BIT(17)
+#define AT91_MATRIX_DDR_IOSR BIT(18)
+#define AT91_MATRIX_NFD0_SELECT BIT(24)
+#define AT91_MATRIX_DDR_MP_EN BIT(25)
+#define AT91_MATRIX_EBI_NUM_CS 8
+
+#define AT91_MATRIX_USBPUCR_PUON BIT(30)
+
+#endif /* _LINUX_MFD_SYSCON_ATMEL_MATRIX_H */
--
1.9.1

2014-12-04 10:30:46

by Nicolas Ferre

[permalink] [raw]

Subject: Re: [PATCH v5 06/11] memory: atmel-ebi: add DT bindings documentation

Le 03/12/2014 21:44, Boris Brezillon a ?crit :
> The EBI (External Bus Interface) is used to access external peripherals
> (NOR, SRAM, NAND, and other specific devices like ethernet controllers).
> Each device is assigned a CS line and an address range and can have its
> own configuration (timings, access mode, bus width, ...).
> This driver provides a generic DT binding to configure a device according
> to its requirements.
> For specific device controllers (like the NAND one) the SMC timings
> should be configured by the controller driver through the matrix and smc
> syscon regmaps.
>
> Signed-off-by: Boris Brezillon <[email protected]>
> ---
> .../bindings/memory-controllers/atmel-ebi.txt | 155 +++++++++++++++++++++
> 1 file changed, 155 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt
> new file mode 100644
> index 0000000..3749ea1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt
> @@ -0,0 +1,155 @@
> +* Device tree bindings for Atmel EBI
> +
> +The External Bus Interface (EBI) controller is a bus where you can connect
> +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs).
> +The EBI provides a glue-less interface to asynchronous memories though the SMC
> +(Static Memory Controller).
> +Synchronous memories (and some asynchronous memories like NANDs) can be
> +attached to specialized controllers which are responsible for configuring the
> +bus appropriately according to the connected device.
> +In the other hand, the bus interface can be automated for simple asynchronous
> +devices.
> +
> +Required properties:
> +
> +- compatible: "atmel,at91sam9260-ebi"
> + "atmel,at91sam9261-ebi"
> + "atmel,at91sam9263-ebi0"
> + "atmel,at91sam9263-ebi1"
> + "atmel,at91sam9g45-ebi"
> + "atmel,at91sam9x5-ebi"
> + "atmel,sama5d3-ebi"
> +
> +- reg: Contains offset/length value for EBI memory mapping.
> + This property might contain several entries if the EBI
> + memory range is not contiguous
> +
> +- #address-cells: Must be 2.
> + The first cell encodes the CS.
> + The second cell encode the offset into the CS memory
> + range.
> +
> +- #size-cells: Must be set to 1.
> +
> +- ranges: Encodes CS to memory region association.
> +
> +- clocks: Clock feeding the EBI controller.
> + See clock-bindings.txt
> +
> +Child chip-select (cs) nodes contain the memory devices nodes connected to
> +such as NOR (e.g. cfi-flash) and NAND.
> +There might be board specific devices like FPGAs.
> +You'll define you device requirements in these child nodes.
> +
> +Required child cs node properties:
> +
> +- #address-cells: Must be 2.
> +
> +- #size-cells: Must be 1.
> +
> +- ranges: Empty property indicating that child nodes can inherit
> + memory layout.
> +
> +Optional child cs node properties:
> +- atmel,generic-dev boolean property specifying if the device is
> + a generic device.

Here, you mean: "atmel,specialized-logic" and the corresponding text...

> + The following properties are only parsed if
> + this property is present.
> + Specialized devices are attached to specialized
> + controllers which are responsible for
> + configuring the bus appropriately.
> + Here are some examples of specialized
> + controllers: NAND, CompactFlash, SDR-SDRAM.
> +
> +- atmel,bus-width: width of the asynchronous device's data bus
> + 8, 16 or 32.
> + 8 if not present.
> +
> +- atmel,byte-access-type "write" or "select" (see Atmel datasheet).
> + "select" if not present.
> +
> +- atmel,read-mode "nrd" or "ncs".
> + "ncs" is not present.
> +
> +- atmel,write-mode "nwe" or "ncs".
> + "ncs" is not present.
> +
> +- atmel,exnw-mode "disabled", "frozen" or "ready".
> + "disabled" if not present.
> +
> +- atmel,page-mode enable page mode if present. The provided value
> + defines the page size (supported values: 4, 8,
> + 16 and 32).
> +
> +Optional device timings expressed in nanoseconds (if the property is not
> +present 0 is assumed):
> +
> +- atmel,ncs-rd-setup-ns
> +- atmel,nrd-setup-ns
> +- atmel,ncs-wr-setup-ns
> +- atmel,nwe-setup-ns
> +- atmel,ncs-rd-pulse-ns
> +- atmel,nrd-pulse-ns
> +- atmel,ncs-wr-pulse-ns
> +- atmel,nwe-pulse-ns
> +- atmel,nwe-cycle-ns
> +- atmel,nrd-cycle-ns
> +- atmel,tdf-ns
> +
> +- atmel,tdf-optimized data float optimized mode. If present the data
> + float time is optimized depending on the next
> + device being accessed (next device setup
> + time is substracted to the current devive data
> + float time).
> +
> +
> +
> +Example:
> +
> + ebi: ebi@10000000 {
> + compatible = "atmel,sama5d3-ebi", "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + atmel,smc = <&hsmc>;
> + atmel,matrix = <&matrix>;
> + reg = <0x10000000 0x10000000
> + 0x40000000 0x30000000>;
> + ranges = <0x0 0x0 0x10000000 0x10000000
> + 0x1 0x0 0x40000000 0x10000000
> + 0x2 0x0 0x50000000 0x10000000
> + 0x3 0x0 0x60000000 0x10000000>;
> + clocks = <&mck>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ebi_addr>;
> +
> + cs@0 {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges;
> + atmel,generic-dev;

Ditto.

> + atmel,read-mode = "nrd";
> + atmel,write-mode = "nwe";
> + atmel,bus-width = <16>;
> + atmel,ncs-rd-setup-ns = <0>;
> + atmel,ncs-wr-setup-ns = <0>;
> + atmel,nwe-setup-ns = <8>;
> + atmel,nrd-setup-ns = <16>;
> + atmel,ncs-rd-pulse-ns = <84>;
> + atmel,ncs-wr-pulse-ns = <84>;
> + atmel,nrd-pulse-ns = <76>;
> + atmel,nwe-pulse-ns = <76>;
> + atmel,nrd-cycle-ns = <107>;
> + atmel,nwe-cycle-ns = <84>;
> + atmel,tdf-ns = <16>;
> +
> + nor: flash@0,0 {
> + compatible = "cfi-flash";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x0 0x0 0x1000000>;
> + bank-width = <2>;
> + };
> + };
> + };
> +
>

--
Nicolas Ferre

2014-12-04 10:34:31

by Nicolas Ferre

[permalink] [raw]

Subject: Re: [PATCH v5 07/11] ARM: at91: select ATMEL_EBI when compiling a kernel for at91sam9 or sama5d3

Le 03/12/2014 21:44, Boris Brezillon a ?crit :
> at91sam9* and sama5d* SoCs have an EBI (External Bus Interface).
> Select the ATMEL_EBI driver when support for these SoCs is selected.
>
> Signed-off-by: Boris Brezillon <[email protected]>
> ---
> .../bindings/memory-controllers/atmel-ebi.txt | 18 +++++++++---------
> arch/arm/mach-at91/Kconfig | 2 ++
> 2 files changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt
> index 3749ea1..68af1ad 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt
> +++ b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt
> @@ -16,6 +16,7 @@ Required properties:
> "atmel,at91sam9261-ebi"
> "atmel,at91sam9263-ebi0"
> "atmel,at91sam9263-ebi1"
> + "atmel,at91sam9rl-ebi"
> "atmel,at91sam9g45-ebi"
> "atmel,at91sam9x5-ebi"
> "atmel,sama5d3-ebi"
> @@ -51,15 +52,14 @@ Required child cs node properties:
> memory layout.
>
> Optional child cs node properties:
> -- atmel,generic-dev boolean property specifying if the device is
> - a generic device.
> +- atmel,specialized-logic boolean property specifying if the device is
> + a connected to a specialized logic:
> + NAND, Compact Flash, SDR-SDRAM.

Ah, ok, seen it here.

> The following properties are only parsed if
> - this property is present.
> - Specialized devices are attached to specialized
> - controllers which are responsible for
> - configuring the bus appropriately.
> - Here are some examples of specialized
> - controllers: NAND, CompactFlash, SDR-SDRAM.
> + this property is absent.
> + If this property is set, specialized controller
> + drivers are responsible for configuring the bus
> + appropriately.
>
> - atmel,bus-width: width of the asynchronous device's data bus
> 8, 16 or 32.
> @@ -99,7 +99,7 @@ present 0 is assumed):
> - atmel,tdf-optimized data float optimized mode. If present the data
> float time is optimized depending on the next
> device being accessed (next device setup
> - time is substracted to the current devive data
> + time is subtracted to the current device data
> float time).
>
>
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index 0e6d548..78b1412 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -49,6 +49,7 @@ config SOC_AT91SAM9
> select GENERIC_CLOCKEVENTS
> select MEMORY if USE_OF
> select ATMEL_SDRAMC if USE_OF
> + select ATMEL_EBI
>
> config SOC_SAMA5
> bool
> @@ -58,6 +59,7 @@ config SOC_SAMA5
> select USE_OF
> select MEMORY
> select ATMEL_SDRAMC
> + select ATMEL_EBI
>
> menu "Atmel AT91 System-on-Chip"
>
>

--
Nicolas Ferre

2014-12-04 10:36:03

by Nicolas Ferre

[permalink] [raw]

Subject: Re: [PATCH v5 00/11] memory: add Atmel EBI (External Bus Interface) driver

2014-12-04 10:48:06

by Boris Brezillon

[permalink] [raw]

Subject: Re: [PATCH v5 06/11] memory: atmel-ebi: add DT bindings documentation

On Thu, 4 Dec 2014 11:30:39 +0100
Nicolas Ferre <[email protected]> wrote:

> Le 03/12/2014 21:44, Boris Brezillon a écrit :
> > The EBI (External Bus Interface) is used to access external peripherals
> > (NOR, SRAM, NAND, and other specific devices like ethernet controllers).
> > Each device is assigned a CS line and an address range and can have its
> > own configuration (timings, access mode, bus width, ...).
> > This driver provides a generic DT binding to configure a device according
> > to its requirements.
> > For specific device controllers (like the NAND one) the SMC timings
> > should be configured by the controller driver through the matrix and smc
> > syscon regmaps.
> >
> > Signed-off-by: Boris Brezillon <[email protected]>
> > ---
> > .../bindings/memory-controllers/atmel-ebi.txt | 155 +++++++++++++++++++++
> > 1 file changed, 155 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt
> >
> > diff --git a/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt
> > new file mode 100644
> > index 0000000..3749ea1
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/memory-controllers/atmel-ebi.txt
> > @@ -0,0 +1,155 @@
> > +* Device tree bindings for Atmel EBI
> > +
> > +The External Bus Interface (EBI) controller is a bus where you can connect
> > +asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs).
> > +The EBI provides a glue-less interface to asynchronous memories though the SMC
> > +(Static Memory Controller).
> > +Synchronous memories (and some asynchronous memories like NANDs) can be
> > +attached to specialized controllers which are responsible for configuring the
> > +bus appropriately according to the connected device.
> > +In the other hand, the bus interface can be automated for simple asynchronous
> > +devices.
> > +
> > +Required properties:
> > +
> > +- compatible: "atmel,at91sam9260-ebi"
> > + "atmel,at91sam9261-ebi"
> > + "atmel,at91sam9263-ebi0"
> > + "atmel,at91sam9263-ebi1"
> > + "atmel,at91sam9g45-ebi"
> > + "atmel,at91sam9x5-ebi"
> > + "atmel,sama5d3-ebi"
> > +
> > +- reg: Contains offset/length value for EBI memory mapping.
> > + This property might contain several entries if the EBI
> > + memory range is not contiguous
> > +
> > +- #address-cells: Must be 2.
> > + The first cell encodes the CS.
> > + The second cell encode the offset into the CS memory
> > + range.
> > +
> > +- #size-cells: Must be set to 1.
> > +
> > +- ranges: Encodes CS to memory region association.
> > +
> > +- clocks: Clock feeding the EBI controller.
> > + See clock-bindings.txt
> > +
> > +Child chip-select (cs) nodes contain the memory devices nodes connected to
> > +such as NOR (e.g. cfi-flash) and NAND.
> > +There might be board specific devices like FPGAs.
> > +You'll define you device requirements in these child nodes.
> > +
> > +Required child cs node properties:
> > +
> > +- #address-cells: Must be 2.
> > +
> > +- #size-cells: Must be 1.
> > +
> > +- ranges: Empty property indicating that child nodes can inherit
> > + memory layout.
> > +
> > +Optional child cs node properties:
> > +- atmel,generic-dev boolean property specifying if the device is
> > + a generic device.
>
> Here, you mean: "atmel,specialized-logic" and the corresponding text...
>

Yep, apparently I squashed the doc fixes in the wrong commit :-(.
I'll fix that.

Thanks,

Boris

--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com