Replace the blackfin arch dependent style of bfin_read/bfin_write with
common readw/writew
Signed-off-by: Aaron Wu <[email protected]>
---
drivers/net/can/bfin_can.c | 126 +++++++++++++++++++++-----------------------
1 file changed, 60 insertions(+), 66 deletions(-)
diff --git a/drivers/net/can/bfin_can.c b/drivers/net/can/bfin_can.c
index 417d5099..0a5eff4 100644
--- a/drivers/net/can/bfin_can.c
+++ b/drivers/net/can/bfin_can.c
@@ -78,8 +78,8 @@ static int bfin_can_set_bittiming(struct net_device *dev)
if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
timing |= SAM;
- bfin_write(®->clock, clk);
- bfin_write(®->timing, timing);
+ writew(clk, ®->clock);
+ writew(timing, ®->timing);
netdev_info(dev, "setting CLOCK=0x%04x TIMING=0x%04x\n", clk, timing);
@@ -94,16 +94,14 @@ static void bfin_can_set_reset_mode(struct net_device *dev)
int i;
/* disable interrupts */
- bfin_write(®->mbim1, 0);
- bfin_write(®->mbim2, 0);
- bfin_write(®->gim, 0);
+ writew(0, ®->mbim1);
+ writew(0, ®->mbim2);
+ writew(0, ®->gim);
/* reset can and enter configuration mode */
- bfin_write(®->control, SRS | CCR);
- SSYNC();
- bfin_write(®->control, CCR);
- SSYNC();
- while (!(bfin_read(®->control) & CCA)) {
+ writew(SRS | CCR, ®->control);
+ writew(CCR, ®->control);
+ while (!(readw(®->control) & CCA)) {
udelay(10);
if (--timeout == 0) {
netdev_err(dev, "fail to enter configuration mode\n");
@@ -116,34 +114,33 @@ static void bfin_can_set_reset_mode(struct net_device *dev)
* by writing to CAN Mailbox Configuration Registers 1 and 2
* For all bits: 0 - Mailbox disabled, 1 - Mailbox enabled
*/
- bfin_write(®->mc1, 0);
- bfin_write(®->mc2, 0);
+ writew(0, ®->mc1);
+ writew(0, ®->mc2);
/* Set Mailbox Direction */
- bfin_write(®->md1, 0xFFFF); /* mailbox 1-16 are RX */
- bfin_write(®->md2, 0); /* mailbox 17-32 are TX */
+ writew(0xFFFF, ®->md1); /* mailbox 1-16 are RX */
+ writew(0, ®->md2); /* mailbox 17-32 are TX */
/* RECEIVE_STD_CHL */
for (i = 0; i < 2; i++) {
- bfin_write(®->chl[RECEIVE_STD_CHL + i].id0, 0);
- bfin_write(®->chl[RECEIVE_STD_CHL + i].id1, AME);
- bfin_write(®->chl[RECEIVE_STD_CHL + i].dlc, 0);
- bfin_write(®->msk[RECEIVE_STD_CHL + i].amh, 0x1FFF);
- bfin_write(®->msk[RECEIVE_STD_CHL + i].aml, 0xFFFF);
+ writew(0, ®->chl[RECEIVE_STD_CHL + i].id0);
+ writew(AME, ®->chl[RECEIVE_STD_CHL + i].id1);
+ writew(0, ®->chl[RECEIVE_STD_CHL + i].dlc);
+ writew(0x1FFF, ®->msk[RECEIVE_STD_CHL + i].amh);
+ writew(0xFFFF, ®->msk[RECEIVE_STD_CHL + i].aml);
}
/* RECEIVE_EXT_CHL */
for (i = 0; i < 2; i++) {
- bfin_write(®->chl[RECEIVE_EXT_CHL + i].id0, 0);
- bfin_write(®->chl[RECEIVE_EXT_CHL + i].id1, AME | IDE);
- bfin_write(®->chl[RECEIVE_EXT_CHL + i].dlc, 0);
- bfin_write(®->msk[RECEIVE_EXT_CHL + i].amh, 0x1FFF);
- bfin_write(®->msk[RECEIVE_EXT_CHL + i].aml, 0xFFFF);
+ writew(0, ®->chl[RECEIVE_EXT_CHL + i].id0);
+ writew(AME | IDE, ®->chl[RECEIVE_EXT_CHL + i].id1);
+ writew(0, ®->chl[RECEIVE_EXT_CHL + i].dlc);
+ writew(0x1FFF, ®->msk[RECEIVE_EXT_CHL + i].amh);
+ writew(0xFFFF, ®->msk[RECEIVE_EXT_CHL + i].aml);
}
- bfin_write(®->mc2, BIT(TRANSMIT_CHL - 16));
- bfin_write(®->mc1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL));
- SSYNC();
+ writew(BIT(TRANSMIT_CHL - 16), ®->mc2);
+ writew(BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL), ®->mc1);
priv->can.state = CAN_STATE_STOPPED;
}
@@ -157,9 +154,9 @@ static void bfin_can_set_normal_mode(struct net_device *dev)
/*
* leave configuration mode
*/
- bfin_write(®->control, bfin_read(®->control) & ~CCR);
+ writew(readw(®->control) & ~CCR, ®->control);
- while (bfin_read(®->status) & CCA) {
+ while (readw(®->status) & CCA) {
udelay(10);
if (--timeout == 0) {
netdev_err(dev, "fail to leave configuration mode\n");
@@ -170,26 +167,25 @@ static void bfin_can_set_normal_mode(struct net_device *dev)
/*
* clear _All_ tx and rx interrupts
*/
- bfin_write(®->mbtif1, 0xFFFF);
- bfin_write(®->mbtif2, 0xFFFF);
- bfin_write(®->mbrif1, 0xFFFF);
- bfin_write(®->mbrif2, 0xFFFF);
+ writew(0xFFFF, ®->mbtif1);
+ writew(0xFFFF, ®->mbtif2);
+ writew(0xFFFF, ®->mbrif1);
+ writew(0xFFFF, ®->mbrif2);
/*
* clear global interrupt status register
*/
- bfin_write(®->gis, 0x7FF); /* overwrites with '1' */
+ writew(0x7FF, ®->gis); /* overwrites with '1' */
/*
* Initialize Interrupts
* - set bits in the mailbox interrupt mask register
* - global interrupt mask
*/
- bfin_write(®->mbim1, BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL));
- bfin_write(®->mbim2, BIT(TRANSMIT_CHL - 16));
+ writew(BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL), ®->mbim1);
+ writew(BIT(TRANSMIT_CHL - 16), ®->mbim2);
- bfin_write(®->gim, EPIM | BOIM | RMLIM);
- SSYNC();
+ writew(EPIM | BOIM | RMLIM, ®->gim);
}
static void bfin_can_start(struct net_device *dev)
@@ -226,7 +222,7 @@ static int bfin_can_get_berr_counter(const struct net_device *dev,
struct bfin_can_priv *priv = netdev_priv(dev);
struct bfin_can_regs __iomem *reg = priv->membase;
- u16 cec = bfin_read(®->cec);
+ u16 cec = readw(®->cec);
bec->txerr = cec >> 8;
bec->rxerr = cec;
@@ -252,28 +248,28 @@ static int bfin_can_start_xmit(struct sk_buff *skb, struct net_device *dev)
/* fill id */
if (id & CAN_EFF_FLAG) {
- bfin_write(®->chl[TRANSMIT_CHL].id0, id);
+ writew(id, ®->chl[TRANSMIT_CHL].id0);
val = ((id & 0x1FFF0000) >> 16) | IDE;
} else
val = (id << 2);
if (id & CAN_RTR_FLAG)
val |= RTR;
- bfin_write(®->chl[TRANSMIT_CHL].id1, val | AME);
+ writew(val | AME, ®->chl[TRANSMIT_CHL].id1);
/* fill payload */
for (i = 0; i < 8; i += 2) {
val = ((7 - i) < dlc ? (data[7 - i]) : 0) +
((6 - i) < dlc ? (data[6 - i] << 8) : 0);
- bfin_write(®->chl[TRANSMIT_CHL].data[i], val);
+ writew(val, ®->chl[TRANSMIT_CHL].data[i]);
}
/* fill data length code */
- bfin_write(®->chl[TRANSMIT_CHL].dlc, dlc);
+ writew(dlc, ®->chl[TRANSMIT_CHL].dlc);
can_put_echo_skb(skb, dev, 0);
/* set transmit request */
- bfin_write(®->trs2, BIT(TRANSMIT_CHL - 16));
+ writew(BIT(TRANSMIT_CHL - 16), ®->trs2);
return 0;
}
@@ -296,26 +292,26 @@ static void bfin_can_rx(struct net_device *dev, u16 isrc)
/* get id */
if (isrc & BIT(RECEIVE_EXT_CHL)) {
/* extended frame format (EFF) */
- cf->can_id = ((bfin_read(®->chl[RECEIVE_EXT_CHL].id1)
+ cf->can_id = ((readw(®->chl[RECEIVE_EXT_CHL].id1)
& 0x1FFF) << 16)
- + bfin_read(®->chl[RECEIVE_EXT_CHL].id0);
+ + readw(®->chl[RECEIVE_EXT_CHL].id0);
cf->can_id |= CAN_EFF_FLAG;
obj = RECEIVE_EXT_CHL;
} else {
/* standard frame format (SFF) */
- cf->can_id = (bfin_read(®->chl[RECEIVE_STD_CHL].id1)
+ cf->can_id = (readw(®->chl[RECEIVE_STD_CHL].id1)
& 0x1ffc) >> 2;
obj = RECEIVE_STD_CHL;
}
- if (bfin_read(®->chl[obj].id1) & RTR)
+ if (readw(®->chl[obj].id1) & RTR)
cf->can_id |= CAN_RTR_FLAG;
/* get data length code */
- cf->can_dlc = get_can_dlc(bfin_read(®->chl[obj].dlc) & 0xF);
+ cf->can_dlc = get_can_dlc(readw(®->chl[obj].dlc) & 0xF);
/* get payload */
for (i = 0; i < 8; i += 2) {
- val = bfin_read(®->chl[obj].data[i]);
+ val = readw(®->chl[obj].data[i]);
cf->data[7 - i] = (7 - i) < cf->can_dlc ? val : 0;
cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0;
}
@@ -368,7 +364,7 @@ static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status)
if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING ||
state == CAN_STATE_ERROR_PASSIVE)) {
- u16 cec = bfin_read(®->cec);
+ u16 cec = readw(®->cec);
u8 rxerr = cec;
u8 txerr = cec >> 8;
@@ -419,23 +415,23 @@ static irqreturn_t bfin_can_interrupt(int irq, void *dev_id)
struct net_device_stats *stats = &dev->stats;
u16 status, isrc;
- if ((irq == priv->tx_irq) && bfin_read(®->mbtif2)) {
+ if ((irq == priv->tx_irq) && readw(®->mbtif2)) {
/* transmission complete interrupt */
- bfin_write(®->mbtif2, 0xFFFF);
+ writew(0xFFFF, ®->mbtif2);
stats->tx_packets++;
- stats->tx_bytes += bfin_read(®->chl[TRANSMIT_CHL].dlc);
+ stats->tx_bytes += readw(®->chl[TRANSMIT_CHL].dlc);
can_get_echo_skb(dev, 0);
netif_wake_queue(dev);
- } else if ((irq == priv->rx_irq) && bfin_read(®->mbrif1)) {
+ } else if ((irq == priv->rx_irq) && readw(®->mbrif1)) {
/* receive interrupt */
- isrc = bfin_read(®->mbrif1);
- bfin_write(®->mbrif1, 0xFFFF);
+ isrc = readw(®->mbrif1);
+ writew(0xFFFF, ®->mbrif1);
bfin_can_rx(dev, isrc);
- } else if ((irq == priv->err_irq) && bfin_read(®->gis)) {
+ } else if ((irq == priv->err_irq) && readw(®->gis)) {
/* error interrupt */
- isrc = bfin_read(®->gis);
- status = bfin_read(®->esr);
- bfin_write(®->gis, 0x7FF);
+ isrc = readw(®->gis);
+ status = readw(®->esr);
+ writew(0x7FF, ®->gis);
bfin_can_err(dev, isrc, status);
} else {
return IRQ_NONE;
@@ -640,9 +636,8 @@ static int bfin_can_suspend(struct platform_device *pdev, pm_message_t mesg)
if (netif_running(dev)) {
/* enter sleep mode */
- bfin_write(®->control, bfin_read(®->control) | SMR);
- SSYNC();
- while (!(bfin_read(®->intr) & SMACK)) {
+ writew(readw(®->control) | SMR, ®->control);
+ while (!(readw(®->intr) & SMACK)) {
udelay(10);
if (--timeout == 0) {
netdev_err(dev, "fail to enter sleep mode\n");
@@ -662,8 +657,7 @@ static int bfin_can_resume(struct platform_device *pdev)
if (netif_running(dev)) {
/* leave sleep mode */
- bfin_write(®->intr, 0);
- SSYNC();
+ writew(0, ®->intr);
}
return 0;
--
1.7.9.5
Blackfin was built without MMU, old driver code access the IO space by
physical address, introduce the ioremap approach to be compitable with
the common style supporting MMU enabled arch.
Signed-off-by: Aaron Wu <[email protected]>
---
drivers/net/can/bfin_can.c | 22 ++++++++--------------
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/drivers/net/can/bfin_can.c b/drivers/net/can/bfin_can.c
index 0a5eff4..259d09a 100644
--- a/drivers/net/can/bfin_can.c
+++ b/drivers/net/can/bfin_can.c
@@ -551,16 +551,10 @@ static int bfin_can_probe(struct platform_device *pdev)
goto exit;
}
- if (!request_mem_region(res_mem->start, resource_size(res_mem),
- dev_name(&pdev->dev))) {
- err = -EBUSY;
- goto exit;
- }
-
/* request peripheral pins */
err = peripheral_request_list(pdata, dev_name(&pdev->dev));
if (err)
- goto exit_mem_release;
+ goto exit;
dev = alloc_bfin_candev();
if (!dev) {
@@ -569,7 +563,13 @@ static int bfin_can_probe(struct platform_device *pdev)
}
priv = netdev_priv(dev);
- priv->membase = (void __iomem *)res_mem->start;
+
+ priv->membase = devm_ioremap_resource(&pdev->dev, res_mem);
+ if (IS_ERR(priv->membase)) {
+ err = PTR_ERR(priv->membase);
+ goto exit_peri_pin_free;
+ }
+
priv->rx_irq = rx_irq->start;
priv->tx_irq = tx_irq->start;
priv->err_irq = err_irq->start;
@@ -601,8 +601,6 @@ exit_candev_free:
free_candev(dev);
exit_peri_pin_free:
peripheral_free_list(pdata);
-exit_mem_release:
- release_mem_region(res_mem->start, resource_size(res_mem));
exit:
return err;
}
@@ -611,15 +609,11 @@ static int bfin_can_remove(struct platform_device *pdev)
{
struct net_device *dev = platform_get_drvdata(pdev);
struct bfin_can_priv *priv = netdev_priv(dev);
- struct resource *res;
bfin_can_set_reset_mode(dev);
unregister_candev(dev);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- release_mem_region(res->start, resource_size(res));
-
peripheral_free_list(priv->pin_list);
free_candev(dev);
--
1.7.9.5
Header file was in arch dependent location arch/blackfin/include/asm/bfin_can.h,
Now move and merge the useful contents of header file into driver code, note
the original header file is reserved for full registers set access test by other
code so it survives.
Signed-off-by: Aaron Wu <[email protected]>
---
drivers/net/can/bfin_can.c | 110 +++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 109 insertions(+), 1 deletion(-)
diff --git a/drivers/net/can/bfin_can.c b/drivers/net/can/bfin_can.c
index 259d09a..bb1d480 100644
--- a/drivers/net/can/bfin_can.c
+++ b/drivers/net/can/bfin_can.c
@@ -20,13 +20,121 @@
#include <linux/can/dev.h>
#include <linux/can/error.h>
-#include <asm/bfin_can.h>
#include <asm/portmux.h>
#define DRV_NAME "bfin_can"
#define BFIN_CAN_TIMEOUT 100
#define TX_ECHO_SKB_MAX 1
+/* transmit and receive channels */
+#define TRANSMIT_CHL 24
+#define RECEIVE_STD_CHL 0
+#define RECEIVE_EXT_CHL 4
+#define RECEIVE_RTR_CHL 8
+#define RECEIVE_EXT_RTR_CHL 12
+#define MAX_CHL_NUMBER 32
+
+/* All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits. So use a helper macro to streamline this
+*/
+#define __BFP(m) u16 m; u16 __pad_##m
+
+/* bfin can registers layout */
+struct bfin_can_mask_regs {
+ __BFP(aml);
+ __BFP(amh);
+};
+
+struct bfin_can_channel_regs {
+ /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
+ u16 data[8];
+ __BFP(dlc);
+ __BFP(tsv);
+ __BFP(id0);
+ __BFP(id1);
+};
+
+struct bfin_can_regs {
+ /* global control and status registers */
+ __BFP(mc1); /* offset 0x00 */
+ __BFP(md1); /* offset 0x04 */
+ __BFP(trs1); /* offset 0x08 */
+ __BFP(trr1); /* offset 0x0c */
+ __BFP(ta1); /* offset 0x10 */
+ __BFP(aa1); /* offset 0x14 */
+ __BFP(rmp1); /* offset 0x18 */
+ __BFP(rml1); /* offset 0x1c */
+ __BFP(mbtif1); /* offset 0x20 */
+ __BFP(mbrif1); /* offset 0x24 */
+ __BFP(mbim1); /* offset 0x28 */
+ __BFP(rfh1); /* offset 0x2c */
+ __BFP(opss1); /* offset 0x30 */
+ u32 __pad1[3];
+ __BFP(mc2); /* offset 0x40 */
+ __BFP(md2); /* offset 0x44 */
+ __BFP(trs2); /* offset 0x48 */
+ __BFP(trr2); /* offset 0x4c */
+ __BFP(ta2); /* offset 0x50 */
+ __BFP(aa2); /* offset 0x54 */
+ __BFP(rmp2); /* offset 0x58 */
+ __BFP(rml2); /* offset 0x5c */
+ __BFP(mbtif2); /* offset 0x60 */
+ __BFP(mbrif2); /* offset 0x64 */
+ __BFP(mbim2); /* offset 0x68 */
+ __BFP(rfh2); /* offset 0x6c */
+ __BFP(opss2); /* offset 0x70 */
+ u32 __pad2[3];
+ __BFP(clock); /* offset 0x80 */
+ __BFP(timing); /* offset 0x84 */
+ __BFP(debug); /* offset 0x88 */
+ __BFP(status); /* offset 0x8c */
+ __BFP(cec); /* offset 0x90 */
+ __BFP(gis); /* offset 0x94 */
+ __BFP(gim); /* offset 0x98 */
+ __BFP(gif); /* offset 0x9c */
+ __BFP(control); /* offset 0xa0 */
+ __BFP(intr); /* offset 0xa4 */
+ __BFP(version); /* offset 0xa8 */
+ __BFP(mbtd); /* offset 0xac */
+ __BFP(ewr); /* offset 0xb0 */
+ __BFP(esr); /* offset 0xb4 */
+ u32 __pad3[2];
+ __BFP(ucreg); /* offset 0xc0 */
+ __BFP(uccnt); /* offset 0xc4 */
+ __BFP(ucrc); /* offset 0xc8 */
+ __BFP(uccnf); /* offset 0xcc */
+ u32 __pad4[1];
+ __BFP(version2); /* offset 0xd4 */
+ u32 __pad5[10];
+
+ /* channel(mailbox) mask and message registers */
+ struct bfin_can_mask_regs msk[MAX_CHL_NUMBER]; /* offset 0x100 */
+ struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */
+};
+
+#undef __BFP
+
+#define SRS 0x0001 /* Software Reset */
+#define SER 0x0008 /* Stuff Error */
+#define BOIM 0x0008 /* Enable Bus Off Interrupt */
+#define CCR 0x0080 /* CAN Configuration Mode Request */
+#define CCA 0x0080 /* Configuration Mode Acknowledge */
+#define SAM 0x0080 /* Sampling */
+#define AME 0x8000 /* Acceptance Mask Enable */
+#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
+#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
+#define RTR 0x4000 /* Remote Frame Transmission Request */
+#define BOIS 0x0008 /* Bus Off IRQ Status */
+#define IDE 0x2000 /* Identifier Extension */
+#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
+#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
+#define EWTIS 0x0001 /* TX Error Count IRQ Status */
+#define EWRIS 0x0002 /* RX Error Count IRQ Status */
+#define BEF 0x0040 /* Bit Error Flag */
+#define FER 0x0080 /* Form Error Flag */
+#define SMR 0x0020 /* Sleep Mode Request */
+#define SMACK 0x0008 /* Sleep Mode Acknowledge */
+
/*
* bfin can private data
*/
--
1.7.9.5
On 02/06/2015 11:14 AM, Aaron Wu wrote:
> Header file was in arch dependent location arch/blackfin/include/asm/bfin_can.h,
> Now move and merge the useful contents of header file into driver code, note
> the original header file is reserved for full registers set access test by other
> code so it survives.
>
> Signed-off-by: Aaron Wu <[email protected]>
> ---
> drivers/net/can/bfin_can.c | 110 +++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 109 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/can/bfin_can.c b/drivers/net/can/bfin_can.c
> index 259d09a..bb1d480 100644
> --- a/drivers/net/can/bfin_can.c
> +++ b/drivers/net/can/bfin_can.c
> @@ -20,13 +20,121 @@
> #include <linux/can/dev.h>
> #include <linux/can/error.h>
>
> -#include <asm/bfin_can.h>
> #include <asm/portmux.h>
>
> #define DRV_NAME "bfin_can"
> #define BFIN_CAN_TIMEOUT 100
> #define TX_ECHO_SKB_MAX 1
>
> +/* transmit and receive channels */
> +#define TRANSMIT_CHL 24
> +#define RECEIVE_STD_CHL 0
> +#define RECEIVE_EXT_CHL 4
> +#define RECEIVE_RTR_CHL 8
> +#define RECEIVE_EXT_RTR_CHL 12
> +#define MAX_CHL_NUMBER 32
> +
> +/* All Blackfin system MMRs are padded to 32bits even if the register
> + * itself is only 16bits. So use a helper macro to streamline this
> +*/
> +#define __BFP(m) u16 m; u16 __pad_##m
> +
> +/* bfin can registers layout */
> +struct bfin_can_mask_regs {
> + __BFP(aml);
> + __BFP(amh);
> +};
> +
> +struct bfin_can_channel_regs {
> + /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
> + u16 data[8];
> + __BFP(dlc);
> + __BFP(tsv);
> + __BFP(id0);
> + __BFP(id1);
> +};
> +
> +struct bfin_can_regs {
> + /* global control and status registers */
> + __BFP(mc1); /* offset 0x00 */
> + __BFP(md1); /* offset 0x04 */
> + __BFP(trs1); /* offset 0x08 */
> + __BFP(trr1); /* offset 0x0c */
> + __BFP(ta1); /* offset 0x10 */
> + __BFP(aa1); /* offset 0x14 */
> + __BFP(rmp1); /* offset 0x18 */
> + __BFP(rml1); /* offset 0x1c */
> + __BFP(mbtif1); /* offset 0x20 */
> + __BFP(mbrif1); /* offset 0x24 */
> + __BFP(mbim1); /* offset 0x28 */
> + __BFP(rfh1); /* offset 0x2c */
> + __BFP(opss1); /* offset 0x30 */
> + u32 __pad1[3];
> + __BFP(mc2); /* offset 0x40 */
> + __BFP(md2); /* offset 0x44 */
> + __BFP(trs2); /* offset 0x48 */
> + __BFP(trr2); /* offset 0x4c */
> + __BFP(ta2); /* offset 0x50 */
> + __BFP(aa2); /* offset 0x54 */
> + __BFP(rmp2); /* offset 0x58 */
> + __BFP(rml2); /* offset 0x5c */
> + __BFP(mbtif2); /* offset 0x60 */
> + __BFP(mbrif2); /* offset 0x64 */
> + __BFP(mbim2); /* offset 0x68 */
> + __BFP(rfh2); /* offset 0x6c */
> + __BFP(opss2); /* offset 0x70 */
> + u32 __pad2[3];
> + __BFP(clock); /* offset 0x80 */
> + __BFP(timing); /* offset 0x84 */
> + __BFP(debug); /* offset 0x88 */
> + __BFP(status); /* offset 0x8c */
> + __BFP(cec); /* offset 0x90 */
> + __BFP(gis); /* offset 0x94 */
> + __BFP(gim); /* offset 0x98 */
> + __BFP(gif); /* offset 0x9c */
> + __BFP(control); /* offset 0xa0 */
> + __BFP(intr); /* offset 0xa4 */
> + __BFP(version); /* offset 0xa8 */
> + __BFP(mbtd); /* offset 0xac */
> + __BFP(ewr); /* offset 0xb0 */
> + __BFP(esr); /* offset 0xb4 */
> + u32 __pad3[2];
> + __BFP(ucreg); /* offset 0xc0 */
> + __BFP(uccnt); /* offset 0xc4 */
> + __BFP(ucrc); /* offset 0xc8 */
> + __BFP(uccnf); /* offset 0xcc */
> + u32 __pad4[1];
> + __BFP(version2); /* offset 0xd4 */
> + u32 __pad5[10];
> +
> + /* channel(mailbox) mask and message registers */
> + struct bfin_can_mask_regs msk[MAX_CHL_NUMBER]; /* offset 0x100 */
> + struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */
> +};
> +
> +#undef __BFP
> +
> +#define SRS 0x0001 /* Software Reset */
^^
please use a single space here (and below), as in the rest of the file.
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |