As a new x86 CPU Vendor, Shanghai Zhaoxin Semiconductor Co., Ltd.
("Zhaoxin") provide high performance general-purpose x86 processors.
CPU Vendor ID "Shanghai" belongs to Zhaoxin.
To enable the supports of Linux kernel to Zhaoxin's CPUs, add a new vendor
type (X86_VENDOR_ZHAOXIN, with value of 10) in
arch/x86/include/asm/processor.h.
To enable the support of Linux kernel's specific configuration to
Zhaoxin's CPUs, add a new file arch/x86/kernel/cpu/zhaoxin.c.
This patch series have been applied and tested successfully on Zhaoxin's
Soc silicon. Also tested on other processors, it works fine and makes no
harm to the existing codes.
v1->v2:
- Rebased on 5.2.0-rc2 and tested against it.
- remove GPL "boilerplate" text in the patch.
- adjust signed-off-by: line match From: line.
- run patch series through checkpatch.pl.
v1:
- Rebased on 5.2.0-rc1 and tested against it.
- Split the patch set to small series of patches.
- Rework patch descriptions.
TonyWWang (3):
x86/cpu: Create Zhaoxin processors architecture support file
ACPI, x86: add Zhaoxin processors support for NONSTOP TSC
x86/acpi/cstate: add Zhaoxin processors support for cache flush policy
in C3
MAINTAINERS | 6 ++
arch/x86/Kconfig.cpu | 13 ++++
arch/x86/include/asm/processor.h | 3 +-
arch/x86/kernel/acpi/cstate.c | 15 ++++
arch/x86/kernel/cpu/Makefile | 1 +
arch/x86/kernel/cpu/zhaoxin.c | 164 +++++++++++++++++++++++++++++++++++++++
drivers/acpi/acpi_pad.c | 1 +
drivers/acpi/processor_idle.c | 1 +
8 files changed, 203 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/kernel/cpu/zhaoxin.c
--
2.7.4
Tony,
On Tue, 28 May 2019, Tony W Wang-oc wrote:
> As a new x86 CPU Vendor, Shanghai Zhaoxin Semiconductor Co., Ltd.
> ("Zhaoxin") provide high performance general-purpose x86 processors.
>
> CPU Vendor ID "Shanghai" belongs to Zhaoxin.
>
> To enable the supports of Linux kernel to Zhaoxin's CPUs, add a new vendor
> type (X86_VENDOR_ZHAOXIN, with value of 10) in
> arch/x86/include/asm/processor.h.
>
> To enable the support of Linux kernel's specific configuration to
> Zhaoxin's CPUs, add a new file arch/x86/kernel/cpu/zhaoxin.c.
>
> This patch series have been applied and tested successfully on Zhaoxin's
> Soc silicon. Also tested on other processors, it works fine and makes no
> harm to the existing codes.
>
> v1->v2:
> - Rebased on 5.2.0-rc2 and tested against it.
> - remove GPL "boilerplate" text in the patch.
> - adjust signed-off-by: line match From: line.
> - run patch series through checkpatch.pl.
>
> v1:
> - Rebased on 5.2.0-rc1 and tested against it.
> - Split the patch set to small series of patches.
> - Rework patch descriptions.
>
> TonyWWang (3):
> x86/cpu: Create Zhaoxin processors architecture support file
> ACPI, x86: add Zhaoxin processors support for NONSTOP TSC
> x86/acpi/cstate: add Zhaoxin processors support for cache flush policy
> in C3
I only got 0/3 and 1/3 of Version 2. Please always send the complete set.
Thanks,
tglx