Hi,
Since v2, this series has changed a lot. We postponed the introduction
of regmap into the Berlin clock driver (and some parts of the clock
framework) to first take care of the Berlin DT reorganisation of the
chip and system controllers.
Marvell Berlin SoCs have a chip control register set providing several
individual registers dealing with various controllers (pinctrl, reset,
clk). This chip controller is described by a single DT node since the
individual registers are spread among the chip control register bank.
Marvell Berlin also have a system control register set providing several
individual registers for pinctrl or adc.
A series was sent[1] to correctly handle these two nodes, by using
simple-mfd. The series converted the existing pin-controller and reset
drivers to take the changes into account.
This series moves the clock DT bindings into their own sub-node of the
chip controller node, and make minor changes into the Berlin clock
driver to take this change into account.
This series has been tested on the Marvell Berlin BG2Q DMP.
This series is based on v4.0-rc1 and [1].
Thanks!
Antoine
[1] https://lkml.org/lkml/2015/3/6/511
Changes since v2:
- Removed all regmap related changes and kept only minor
needed changes in the Berlin clock driver.
Changes since v1:
- Rebased of top of the new version of [1].
- Removed now useless chip and system ctrl compatibles.
Antoine Tenart (9):
clk: berlin: move to a dedicated sub-node
Documentation: bindings: move the Berlin clock documentation
ARM: berlin: rework the clock node for BG2
ARM: berlin: rework the clock node for BG2CD
ARM: berlin: rework the clock node for BG2Q
Documentation: bindings: update the berlin chip and system ctrl doc
ARM: berlin: remove useless chip and system ctrl compatibles in BG2
ARM: berlin: remove useless chip and system ctrl compatibles in BG2CD
ARM: berlin: remove useless chip and system ctrl compatibles in BG2Q
.../devicetree/bindings/arm/marvell,berlin.txt | 43 +++-------------
.../devicetree/bindings/clock/marvell,berlin.txt | 31 ++++++++++++
arch/arm/boot/dts/berlin2.dtsi | 47 ++++++++++--------
arch/arm/boot/dts/berlin2cd.dtsi | 43 ++++++++--------
arch/arm/boot/dts/berlin2q.dtsi | 57 ++++++++++++----------
drivers/clk/berlin/bg2.c | 7 ++-
drivers/clk/berlin/bg2q.c | 7 +--
7 files changed, 127 insertions(+), 108 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/marvell,berlin.txt
--
2.3.5
The Berlin clock driver was sharing a DT node with the pin controller
and the reset driver. All these devices are now sub-nodes of the chip
controller. This patch rework the Berlin clock driver to allow moving
the Berlin clock DT bindings into their own sub-node of the chip
controller node.
Signed-off-by: Antoine Tenart <[email protected]>
---
drivers/clk/berlin/bg2.c | 7 +++----
drivers/clk/berlin/bg2q.c | 7 ++++---
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c
index 515fb133495c..3bfb3aede9f4 100644
--- a/drivers/clk/berlin/bg2.c
+++ b/drivers/clk/berlin/bg2.c
@@ -502,12 +502,13 @@ static const struct berlin2_gate_data bg2_gates[] __initconst = {
static void __init berlin2_clock_setup(struct device_node *np)
{
+ struct device_node *parent_np = of_get_parent(np);
const char *parent_names[9];
struct clk *clk;
u8 avpll_flags = 0;
int n;
- gbase = of_iomap(np, 0);
+ gbase = of_iomap(parent_np, 0);
if (!gbase)
return;
@@ -685,7 +686,5 @@ static void __init berlin2_clock_setup(struct device_node *np)
bg2_fail:
iounmap(gbase);
}
-CLK_OF_DECLARE(berlin2_clock, "marvell,berlin2-chip-ctrl",
- berlin2_clock_setup);
-CLK_OF_DECLARE(berlin2cd_clock, "marvell,berlin2cd-chip-ctrl",
+CLK_OF_DECLARE(berlin2_clock, "marvell,berlin2-clk",
berlin2_clock_setup);
diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c
index 440ef81ab15c..72a50ded145a 100644
--- a/drivers/clk/berlin/bg2q.c
+++ b/drivers/clk/berlin/bg2q.c
@@ -290,18 +290,19 @@ static const struct berlin2_gate_data bg2q_gates[] __initconst = {
static void __init berlin2q_clock_setup(struct device_node *np)
{
+ struct device_node *parent_np = of_get_parent(np);
const char *parent_names[9];
struct clk *clk;
int n;
- gbase = of_iomap(np, 0);
+ gbase = of_iomap(parent_np, 0);
if (!gbase) {
pr_err("%s: Unable to map global base\n", np->full_name);
return;
}
/* BG2Q CPU PLL is not part of global registers */
- cpupll_base = of_iomap(np, 1);
+ cpupll_base = of_iomap(parent_np, 1);
if (!cpupll_base) {
pr_err("%s: Unable to map cpupll base\n", np->full_name);
iounmap(gbase);
@@ -384,5 +385,5 @@ bg2q_fail:
iounmap(cpupll_base);
iounmap(gbase);
}
-CLK_OF_DECLARE(berlin2q_clock, "marvell,berlin2q-chip-ctrl",
+CLK_OF_DECLARE(berlin2q_clock, "marvell,berlin2q-clk",
berlin2q_clock_setup);
--
2.3.5
The Berlin clock documentation was part of the Marvell Berlin SoC
documentation because the Berlin clock configuration was inside the
chip controller. With the recent rework of the chip and system
controller handling (now all sub-devices of the soc and system
controller nodes are registred with simple-mfd, and each device has its
own sub-node), the documentation of the Berlin clock driver can be moved
to the generic clock documentation directory.
Signed-off-by: Antoine Tenart <[email protected]>
---
.../devicetree/bindings/arm/marvell,berlin.txt | 27 +++----------------
.../devicetree/bindings/clock/marvell,berlin.txt | 31 ++++++++++++++++++++++
2 files changed, 35 insertions(+), 23 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/marvell,berlin.txt
diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
index ece73c6ad973..4a8ff8e14cb7 100644
--- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -75,37 +75,18 @@ Required properties:
"simple-mfd", "syscon"
- reg: address and length of the system control register set
-* Clock provider binding
-
-As clock related registers are spread among the chip control registers, the
-chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)
-SoCs share the same IP for PLLs and clocks, with some minor differences in
-features and register layout.
-
-Required properties:
-- #clock-cells: shall be set to 1
-- clocks: clock specifiers referencing the core clock input clocks
-- clock-names: array of strings describing the input clock specifiers above.
- Allowed clock-names for the reference clocks are
- "refclk" for the SoCs osciallator input on all SoCs,
- and SoC-specific input clocks for
- BG2/BG2CD: "video_ext0" for the external video clock input
-
-Clocks provided by core clocks shall be referenced by a clock specifier
-indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
-for the corresponding index mapping.
-
Example:
chip: chip-control@ea0000 {
compatible = "marvell,berlin2-chip-ctrl", "simple-mfd", "syscon";
- #clock-cells = <1>;
reg = <0xea0000 0x400>;
- clocks = <&refclk>, <&externaldev 0>;
- clock-names = "refclk", "video_ext0";
+
+ /* sub-device nodes */
};
sysctrl: system-controller@d000 {
compatible = "marvell,berlin2-system-ctrl", "simple-mfd", "syscon";
reg = <0xd000 0x100>;
+
+ /* sub-device nodes */
};
diff --git a/Documentation/devicetree/bindings/clock/marvell,berlin.txt b/Documentation/devicetree/bindings/clock/marvell,berlin.txt
new file mode 100644
index 000000000000..c611c495f3ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/marvell,berlin.txt
@@ -0,0 +1,31 @@
+Device Tree Clock bindings for Marvell Berlin
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Clock related registers are spread among the chip control registers. Berlin
+clock node should be a sub-node of the chip controller node. Marvell Berlin2
+(BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some
+minor differences in features and register layout.
+
+Required properties:
+- compatible: must be "marvell,berlin2-clk" or "marvell,berlin2q-clk"
+- #clock-cells: must be 1
+- clocks: must be the input parent clock phandle
+- clock-names: name of the input parent clock
+ Allowed clock-names for the reference clocks are
+ "refclk" for the SoCs oscillator input on all SoCs,
+ and SoC-specific input clocks for
+ BG2/BG2CD: "video_ext0" for the external video clock input
+
+
+Example:
+
+chip_clk: clock {
+ compatible = "marvell,berlin2q-clk";
+
+ #clock-cells = <1>;
+ clocks = <&refclk>;
+ clock-names = "refclk";
+};
--
2.3.5
With the introduction of the Berlin mfd controller driver, all drivers
previously sharing the chip and system controller nodes now have their
own sub-node.
Signed-off-by: Antoine Tenart <[email protected]>
---
arch/arm/boot/dts/berlin2.dtsi | 43 +++++++++++++++++++++++-------------------
1 file changed, 24 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index fbe5c6b6502d..0cbe99da16dc 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -56,7 +56,7 @@
sdhci0: sdhci@ab0000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>;
- clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
+ clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
clock-names = "io", "core";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -65,7 +65,7 @@
sdhci1: sdhci@ab0800 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0800 0x200>;
- clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
+ clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
clock-names = "io", "core";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -75,7 +75,7 @@
compatible = "mrvl,pxav3-mmc";
reg = <0xab1000 0x200>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
+ clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
clock-names = "io", "core";
pinctrl-0 = <&emmc_pmux>;
pinctrl-names = "default";
@@ -105,13 +105,13 @@
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&chip CLKID_TWD>;
+ clocks = <&chip_clk CLKID_TWD>;
};
eth1: ethernet@b90000 {
compatible = "marvell,pxa168-eth";
reg = <0xb90000 0x10000>;
- clocks = <&chip CLKID_GETH1>;
+ clocks = <&chip_clk CLKID_GETH1>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */
local-mac-address = [00 00 00 00 00 00];
@@ -134,7 +134,7 @@
eth0: ethernet@e50000 {
compatible = "marvell,pxa168-eth";
reg = <0xe50000 0x10000>;
- clocks = <&chip CLKID_GETH0>;
+ clocks = <&chip_clk CLKID_GETH0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */
local-mac-address = [00 00 00 00 00 00];
@@ -233,7 +233,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>;
interrupts = <8>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "okay";
};
@@ -242,7 +242,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>;
interrupts = <9>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "okay";
};
@@ -251,7 +251,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>;
interrupts = <10>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -260,7 +260,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>;
interrupts = <11>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -269,7 +269,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>;
interrupts = <12>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -278,7 +278,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>;
interrupts = <13>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -287,7 +287,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>;
interrupts = <14>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -296,7 +296,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>;
interrupts = <15>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -315,7 +315,7 @@
compatible = "marvell,berlin2-ahci", "generic-ahci";
reg = <0xe90000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&chip CLKID_SATA>;
+ clocks = <&chip_clk CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
@@ -335,7 +335,7 @@
sata_phy: phy@e900a0 {
compatible = "marvell,berlin2-sata-phy";
reg = <0xe900a0 0x200>;
- clocks = <&chip CLKID_SATA>;
+ clocks = <&chip_clk CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
@@ -353,9 +353,14 @@
chip: chip-controller@ea0000 {
compatible = "marvell,berlin2-chip-ctrl", "simple-mfd", "syscon";
reg = <0xea0000 0x400>;
- #clock-cells = <1>;
- clocks = <&refclk>;
- clock-names = "refclk";
+
+ chip_clk: clock {
+ compatible = "marvell,berlin2-clk";
+
+ #clock-cells = <1>;
+ clocks = <&refclk>;
+ clock-names = "refclk";
+ };
soc_pinctrl: pin-controller {
compatible = "marvell,berlin2-soc-pinctrl";
--
2.3.5
With the introduction of the Berlin mfd controller driver, all drivers
previously sharing the chip and system controller nodes now have their
own sub-node.
Signed-off-by: Antoine Tenart <[email protected]>
---
arch/arm/boot/dts/berlin2cd.dtsi | 39 ++++++++++++++++++++++-----------------
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 4bca01ee94d6..240bfe24ae83 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -53,7 +53,7 @@
sdhci0: sdhci@ab0000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>;
- clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
+ clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
clock-names = "io", "core";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -77,7 +77,7 @@
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
- clocks = <&chip CLKID_TWD>;
+ clocks = <&chip_clk CLKID_TWD>;
};
usb_phy0: usb-phy@b74000 {
@@ -99,7 +99,7 @@
eth1: ethernet@b90000 {
compatible = "marvell,pxa168-eth";
reg = <0xb90000 0x10000>;
- clocks = <&chip CLKID_GETH1>;
+ clocks = <&chip_clk CLKID_GETH1>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */
local-mac-address = [00 00 00 00 00 00];
@@ -117,7 +117,7 @@
eth0: ethernet@e50000 {
compatible = "marvell,pxa168-eth";
reg = <0xe50000 0x10000>;
- clocks = <&chip CLKID_GETH0>;
+ clocks = <&chip_clk CLKID_GETH0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */
local-mac-address = [00 00 00 00 00 00];
@@ -216,7 +216,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>;
interrupts = <8>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "okay";
};
@@ -225,7 +225,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>;
interrupts = <9>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "okay";
};
@@ -234,7 +234,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>;
interrupts = <10>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -243,7 +243,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>;
interrupts = <11>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -252,7 +252,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>;
interrupts = <12>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -261,7 +261,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>;
interrupts = <13>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -270,7 +270,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>;
interrupts = <14>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -279,7 +279,7 @@
compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>;
interrupts = <15>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -297,9 +297,14 @@
chip: chip-controller@ea0000 {
compatible = "marvell,berlin2cd-chip-ctrl", "simple-mfd", "syscon";
reg = <0xea0000 0x400>;
- #clock-cells = <1>;
- clocks = <&refclk>;
- clock-names = "refclk";
+
+ chip_clk: clock {
+ compatible = "marvell,berlin2-clk";
+
+ #clock-cells = <1>;
+ clocks = <&refclk>;
+ clock-names = "refclk";
+ };
soc_pinctrl: pin-controller {
compatible = "marvell,berlin2cd-soc-pinctrl";
@@ -320,7 +325,7 @@
compatible = "chipidea,usb2";
reg = <0xed0000 0x200>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&chip CLKID_USB0>;
+ clocks = <&chip_clk CLKID_USB0>;
phys = <&usb_phy0>;
phy-names = "usb-phy";
status = "disabled";
@@ -330,7 +335,7 @@
compatible = "chipidea,usb2";
reg = <0xee0000 0x200>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&chip CLKID_USB1>;
+ clocks = <&chip_clk CLKID_USB1>;
phys = <&usb_phy1>;
phy-names = "usb-phy";
status = "disabled";
--
2.3.5
With the introduction of the Berlin mfd controller driver, all drivers
previously sharing the chip and system controller nodes now have their
own sub-node.
Signed-off-by: Antoine Tenart <[email protected]>
---
arch/arm/boot/dts/berlin2q.dtsi | 53 ++++++++++++++++++++++-------------------
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 006d382d44ff..9000eb2ebc45 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -74,7 +74,7 @@
sdhci0: sdhci@ab0000 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0000 0x200>;
- clocks = <&chip CLKID_SDIO1XIN>;
+ clocks = <&chip_clk CLKID_SDIO1XIN>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -82,7 +82,7 @@
sdhci1: sdhci@ab0800 {
compatible = "mrvl,pxav3-mmc";
reg = <0xab0800 0x200>;
- clocks = <&chip CLKID_SDIO1XIN>;
+ clocks = <&chip_clk CLKID_SDIO1XIN>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -91,7 +91,7 @@
compatible = "mrvl,pxav3-mmc";
reg = <0xab1000 0x200>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
+ clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
clock-names = "io", "core";
status = "disabled";
};
@@ -112,7 +112,7 @@
local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
- clocks = <&chip CLKID_TWD>;
+ clocks = <&chip_clk CLKID_TWD>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
@@ -135,7 +135,7 @@
compatible = "chipidea,usb2";
reg = <0xa30000 0x10000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&chip CLKID_USB2>;
+ clocks = <&chip_clk CLKID_USB2>;
phys = <&usb_phy2>;
phy-names = "usb-phy";
status = "disabled";
@@ -153,14 +153,14 @@
compatible = "marvell,berlin2-usb-phy";
reg = <0xb78000 0x128>;
#phy-cells = <0>;
- resets = <&chip 0x104 13>;
+ resets = <&chip_rst 0x104 13>;
status = "disabled";
};
eth0: ethernet@b90000 {
compatible = "marvell,pxa168-eth";
reg = <0xb90000 0x10000>;
- clocks = <&chip CLKID_GETH0>;
+ clocks = <&chip_clk CLKID_GETH0>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
/* set by bootloader */
local-mac-address = [00 00 00 00 00 00];
@@ -267,7 +267,7 @@
reg = <0x1400 0x100>;
interrupt-parent = <&aic>;
interrupts = <4>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
pinctrl-0 = <&twsi0_pmux>;
pinctrl-names = "default";
status = "disabled";
@@ -280,7 +280,7 @@
reg = <0x1800 0x100>;
interrupt-parent = <&aic>;
interrupts = <5>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
pinctrl-0 = <&twsi1_pmux>;
pinctrl-names = "default";
status = "disabled";
@@ -289,7 +289,7 @@
timer0: timer@2c00 {
compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
interrupts = <8>;
};
@@ -297,14 +297,14 @@
timer1: timer@2c14 {
compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
};
timer2: timer@2c28 {
compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -312,7 +312,7 @@
timer3: timer@2c3c {
compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -320,7 +320,7 @@
timer4: timer@2c50 {
compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -328,7 +328,7 @@
timer5: timer@2c64 {
compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -336,7 +336,7 @@
timer6: timer@2c78 {
compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -344,7 +344,7 @@
timer7: timer@2c8c {
compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>;
- clocks = <&chip CLKID_CFG>;
+ clocks = <&chip_clk CLKID_CFG>;
clock-names = "timer";
status = "disabled";
};
@@ -362,9 +362,14 @@
chip: chip-controller@ea0000 {
compatible = "marvell,berlin2q-chip-ctrl", "simple-mfd", "syscon";
reg = <0xea0000 0x400>, <0xdd0170 0x10>;
- #clock-cells = <1>;
- clocks = <&refclk>;
- clock-names = "refclk";
+
+ chip_clk: clock {
+ compatible = "marvell,berlin2q-clk";
+
+ #clock-cells = <1>;
+ clocks = <&refclk>;
+ clock-names = "refclk";
+ };
soc_pinctrl: pin-controller {
compatible = "marvell,berlin2q-soc-pinctrl";
@@ -390,7 +395,7 @@
compatible = "marvell,berlin2q-ahci", "generic-ahci";
reg = <0xe90000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&chip CLKID_SATA>;
+ clocks = <&chip_clk CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
@@ -410,7 +415,7 @@
sata_phy: phy@e900a0 {
compatible = "marvell,berlin2q-sata-phy";
reg = <0xe900a0 0x200>;
- clocks = <&chip CLKID_SATA>;
+ clocks = <&chip_clk CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
@@ -429,7 +434,7 @@
compatible = "chipidea,usb2";
reg = <0xed0000 0x10000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&chip CLKID_USB0>;
+ clocks = <&chip_clk CLKID_USB0>;
phys = <&usb_phy0>;
phy-names = "usb-phy";
status = "disabled";
@@ -439,7 +444,7 @@
compatible = "chipidea,usb2";
reg = <0xee0000 0x10000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&chip CLKID_USB1>;
+ clocks = <&chip_clk CLKID_USB1>;
phys = <&usb_phy1>;
phy-names = "usb-phy";
status = "disabled";
--
2.3.5
Now that the rework to have one sub-node per device in the chip and
system controllers is done, their dedicated compatible can be removed.
Signed-off-by: Antoine Tenart <[email protected]>
---
Documentation/devicetree/bindings/arm/marvell,berlin.txt | 16 ++++------------
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
index 4a8ff8e14cb7..b76838ab4f51 100644
--- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt
+++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt
@@ -50,11 +50,7 @@ different functions which are described below.
Required properties:
- compatible:
- * the first value should be one of:
- "marvell,berlin2-chip-ctrl" for BG2
- "marvell,berlin2cd-chip-ctrl" for BG2CD
- "marvell,berlin2q-chip-ctrl" for BG2Q
- * the second and third values must be:
+ * the first and second values must be:
"simple-mfd", "syscon"
- reg: address and length of following register sets for
BG2/BG2CD: chip control register set
@@ -67,25 +63,21 @@ individual registers dealing with pinmux, padmux, and reset.
Required properties:
- compatible:
- * the first value should be one of:
- "marvell,berlin2-system-ctrl" for BG2
- "marvell,berlin2cd-system-ctrl" for BG2CD
- "marvell,berlin2q-system-ctrl" for BG2Q
- * the second and third values must be:
+ * the first and second values must be:
"simple-mfd", "syscon"
- reg: address and length of the system control register set
Example:
chip: chip-control@ea0000 {
- compatible = "marvell,berlin2-chip-ctrl", "simple-mfd", "syscon";
+ compatible = "simple-mfd", "syscon";
reg = <0xea0000 0x400>;
/* sub-device nodes */
};
sysctrl: system-controller@d000 {
- compatible = "marvell,berlin2-system-ctrl", "simple-mfd", "syscon";
+ compatible = "simple-mfd", "syscon";
reg = <0xd000 0x100>;
/* sub-device nodes */
--
2.3.5
Now that the rework to have one sub-node per device in the chip and
system controllers is done, their dedicated compatible can be removed.
Signed-off-by: Antoine Tenart <[email protected]>
---
arch/arm/boot/dts/berlin2.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 0cbe99da16dc..a80611999b37 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -351,7 +351,7 @@
};
chip: chip-controller@ea0000 {
- compatible = "marvell,berlin2-chip-ctrl", "simple-mfd", "syscon";
+ compatible = "simple-mfd", "syscon";
reg = <0xea0000 0x400>;
chip_clk: clock {
@@ -455,7 +455,7 @@
};
sysctrl: system-controller@d000 {
- compatible = "marvell,berlin2-system-ctrl", "simple-mfd", "syscon";
+ compatible = "simple-mfd", "syscon";
reg = <0xd000 0x100>;
sys_pinctrl: pin-controller {
--
2.3.5
Now that the rework to have one sub-node per device in the chip and
system controllers is done, their dedicated compatible can be removed.
Signed-off-by: Antoine Tenart <[email protected]>
---
arch/arm/boot/dts/berlin2cd.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 240bfe24ae83..7dff8497606b 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -295,7 +295,7 @@
};
chip: chip-controller@ea0000 {
- compatible = "marvell,berlin2cd-chip-ctrl", "simple-mfd", "syscon";
+ compatible = "simple-mfd", "syscon";
reg = <0xea0000 0x400>;
chip_clk: clock {
@@ -402,7 +402,7 @@
};
sysctrl: system-controller@d000 {
- compatible = "marvell,berlin2cd-system-ctrl", "simple-mfd", "syscon";
+ compatible = "simple-mfd", "syscon";
reg = <0xd000 0x100>;
sys_pinctrl: pin-controller {
--
2.3.5
Now that the rework to have one sub-node per device in the chip and
system controllers is done, their dedicated compatible can be removed.
Signed-off-by: Antoine Tenart <[email protected]>
---
arch/arm/boot/dts/berlin2q.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 9000eb2ebc45..187d056f7ad2 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -360,7 +360,7 @@
};
chip: chip-controller@ea0000 {
- compatible = "marvell,berlin2q-chip-ctrl", "simple-mfd", "syscon";
+ compatible = "simple-mfd", "syscon";
reg = <0xea0000 0x400>, <0xdd0170 0x10>;
chip_clk: clock {
@@ -539,7 +539,7 @@
};
sysctrl: system-controller@d000 {
- compatible = "marvell,berlin2q-system-ctrl", "simple-mfd", "syscon";
+ compatible = "simple-mfd", "syscon";
reg = <0xd000 0x100>;
sys_pinctrl: pin-controller {
--
2.3.5
On 07.04.2015 16:45, Antoine Tenart wrote:
> The Berlin clock driver was sharing a DT node with the pin controller
> and the reset driver. All these devices are now sub-nodes of the chip
> controller. This patch rework the Berlin clock driver to allow moving
> the Berlin clock DT bindings into their own sub-node of the chip
> controller node.
>
> Signed-off-by: Antoine Tenart <[email protected]>
Mike, Stephen,
would you mind to give your Acked-by for this patch and let me take
this through Berlin and ARM-SoC tree? The patch only touches berlin-
specific subdirectories in clk/ so there should be no merge issues
expected.
Sebastian
> ---
> drivers/clk/berlin/bg2.c | 7 +++----
> drivers/clk/berlin/bg2q.c | 7 ++++---
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c
> index 515fb133495c..3bfb3aede9f4 100644
> --- a/drivers/clk/berlin/bg2.c
> +++ b/drivers/clk/berlin/bg2.c
> @@ -502,12 +502,13 @@ static const struct berlin2_gate_data bg2_gates[] __initconst = {
>
> static void __init berlin2_clock_setup(struct device_node *np)
> {
> + struct device_node *parent_np = of_get_parent(np);
> const char *parent_names[9];
> struct clk *clk;
> u8 avpll_flags = 0;
> int n;
>
> - gbase = of_iomap(np, 0);
> + gbase = of_iomap(parent_np, 0);
> if (!gbase)
> return;
>
> @@ -685,7 +686,5 @@ static void __init berlin2_clock_setup(struct device_node *np)
> bg2_fail:
> iounmap(gbase);
> }
> -CLK_OF_DECLARE(berlin2_clock, "marvell,berlin2-chip-ctrl",
> - berlin2_clock_setup);
> -CLK_OF_DECLARE(berlin2cd_clock, "marvell,berlin2cd-chip-ctrl",
> +CLK_OF_DECLARE(berlin2_clock, "marvell,berlin2-clk",
> berlin2_clock_setup);
> diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c
> index 440ef81ab15c..72a50ded145a 100644
> --- a/drivers/clk/berlin/bg2q.c
> +++ b/drivers/clk/berlin/bg2q.c
> @@ -290,18 +290,19 @@ static const struct berlin2_gate_data bg2q_gates[] __initconst = {
>
> static void __init berlin2q_clock_setup(struct device_node *np)
> {
> + struct device_node *parent_np = of_get_parent(np);
> const char *parent_names[9];
> struct clk *clk;
> int n;
>
> - gbase = of_iomap(np, 0);
> + gbase = of_iomap(parent_np, 0);
> if (!gbase) {
> pr_err("%s: Unable to map global base\n", np->full_name);
> return;
> }
>
> /* BG2Q CPU PLL is not part of global registers */
> - cpupll_base = of_iomap(np, 1);
> + cpupll_base = of_iomap(parent_np, 1);
> if (!cpupll_base) {
> pr_err("%s: Unable to map cpupll base\n", np->full_name);
> iounmap(gbase);
> @@ -384,5 +385,5 @@ bg2q_fail:
> iounmap(cpupll_base);
> iounmap(gbase);
> }
> -CLK_OF_DECLARE(berlin2q_clock, "marvell,berlin2q-chip-ctrl",
> +CLK_OF_DECLARE(berlin2q_clock, "marvell,berlin2q-clk",
> berlin2q_clock_setup);
>
On 28.04.2015 13:32, Sebastian Hesselbarth wrote:
> On 07.04.2015 16:45, Antoine Tenart wrote:
>> The Berlin clock driver was sharing a DT node with the pin controller
>> and the reset driver. All these devices are now sub-nodes of the chip
>> controller. This patch rework the Berlin clock driver to allow moving
>> the Berlin clock DT bindings into their own sub-node of the chip
>> controller node.
>>
>> Signed-off-by: Antoine Tenart <[email protected]>
>
> Mike, Stephen,
>
> would you mind to give your Acked-by for this patch and let me take
> this through Berlin and ARM-SoC tree? The patch only touches berlin-
> specific subdirectories in clk/ so there should be no merge issues
> expected.
Gentle ping.
Mike, Stephen,
I'd like to see this in v4.2-rc and it has been around for at least
a cycle.
Sebastian
>> ---
>> drivers/clk/berlin/bg2.c | 7 +++----
>> drivers/clk/berlin/bg2q.c | 7 ++++---
>> 2 files changed, 7 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/clk/berlin/bg2.c b/drivers/clk/berlin/bg2.c
>> index 515fb133495c..3bfb3aede9f4 100644
>> --- a/drivers/clk/berlin/bg2.c
>> +++ b/drivers/clk/berlin/bg2.c
>> @@ -502,12 +502,13 @@ static const struct berlin2_gate_data
>> bg2_gates[] __initconst = {
>>
>> static void __init berlin2_clock_setup(struct device_node *np)
>> {
>> + struct device_node *parent_np = of_get_parent(np);
>> const char *parent_names[9];
>> struct clk *clk;
>> u8 avpll_flags = 0;
>> int n;
>>
>> - gbase = of_iomap(np, 0);
>> + gbase = of_iomap(parent_np, 0);
>> if (!gbase)
>> return;
>>
>> @@ -685,7 +686,5 @@ static void __init berlin2_clock_setup(struct
>> device_node *np)
>> bg2_fail:
>> iounmap(gbase);
>> }
>> -CLK_OF_DECLARE(berlin2_clock, "marvell,berlin2-chip-ctrl",
>> - berlin2_clock_setup);
>> -CLK_OF_DECLARE(berlin2cd_clock, "marvell,berlin2cd-chip-ctrl",
>> +CLK_OF_DECLARE(berlin2_clock, "marvell,berlin2-clk",
>> berlin2_clock_setup);
>> diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c
>> index 440ef81ab15c..72a50ded145a 100644
>> --- a/drivers/clk/berlin/bg2q.c
>> +++ b/drivers/clk/berlin/bg2q.c
>> @@ -290,18 +290,19 @@ static const struct berlin2_gate_data
>> bg2q_gates[] __initconst = {
>>
>> static void __init berlin2q_clock_setup(struct device_node *np)
>> {
>> + struct device_node *parent_np = of_get_parent(np);
>> const char *parent_names[9];
>> struct clk *clk;
>> int n;
>>
>> - gbase = of_iomap(np, 0);
>> + gbase = of_iomap(parent_np, 0);
>> if (!gbase) {
>> pr_err("%s: Unable to map global base\n", np->full_name);
>> return;
>> }
>>
>> /* BG2Q CPU PLL is not part of global registers */
>> - cpupll_base = of_iomap(np, 1);
>> + cpupll_base = of_iomap(parent_np, 1);
>> if (!cpupll_base) {
>> pr_err("%s: Unable to map cpupll base\n", np->full_name);
>> iounmap(gbase);
>> @@ -384,5 +385,5 @@ bg2q_fail:
>> iounmap(cpupll_base);
>> iounmap(gbase);
>> }
>> -CLK_OF_DECLARE(berlin2q_clock, "marvell,berlin2q-chip-ctrl",
>> +CLK_OF_DECLARE(berlin2q_clock, "marvell,berlin2q-clk",
>> berlin2q_clock_setup);
>>
>
On 04/07, Antoine Tenart wrote:
> The Berlin clock driver was sharing a DT node with the pin controller
> and the reset driver. All these devices are now sub-nodes of the chip
> controller. This patch rework the Berlin clock driver to allow moving
> the Berlin clock DT bindings into their own sub-node of the chip
> controller node.
>
> Signed-off-by: Antoine Tenart <[email protected]>
> ---
Acked-by: Stephen Boyd <[email protected]>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 04/07, Antoine Tenart wrote:
> The Berlin clock documentation was part of the Marvell Berlin SoC
> documentation because the Berlin clock configuration was inside the
> chip controller. With the recent rework of the chip and system
> controller handling (now all sub-devices of the soc and system
> controller nodes are registred with simple-mfd, and each device has its
> own sub-node), the documentation of the Berlin clock driver can be moved
> to the generic clock documentation directory.
>
> Signed-off-by: Antoine Tenart <[email protected]>
> ---
Acked-by: Stephen Boyd <[email protected]>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project