According to the technical reference manual for AM35xx system
controller module (SCM) PADCONFS core registers are divided in two
regions: 0x48002030..0x48002268 and 0x480025d8..0x480025FC.
First region is the same for all omap3 SoC and is described in omap3.dtsi.
The second region is the same as in omap34xx (see omap34xx.dtsi)
and omap35xx. The patch adds missing description for the second region.
This patch was tested on AM3517.
Signed-off-by: Andrey Skvortsov <[email protected]>
---
Commit 3d495383648a ("ARM: dts: Split omap3 pinmux core device") notes that
Nishanth Menon <[email protected]> said that 3517 does not have padconf2 region.
Unfortunately I couldn't find reference to his post on mailing list.
This patch was tested on AM3517 SoC and original vendor code contains
pinmuxing for this second region as well.
arch/arm/boot/dts/am3517.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index c90724b..2534500 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -60,5 +60,16 @@
dma-names = "tx", "rx";
clock-frequency = <48000000>;
};
+
+ omap3_pmx_core2: pinmux@480025D8 {
+ compatible = "ti,omap3-padconf", "pinctrl-single";
+ reg = <0x480025D8 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0xff1f>;
+ };
};
};
--
2.1.4
On 05/10/2015 04:27 PM, Andrey Skvortsov wrote:
> According to the technical reference manual for AM35xx system
> controller module (SCM) PADCONFS core registers are divided in two
> regions: 0x48002030..0x48002268 and 0x480025d8..0x480025FC.
> First region is the same for all omap3 SoC and is described in omap3.dtsi.
> The second region is the same as in omap34xx (see omap34xx.dtsi)
> and omap35xx. The patch adds missing description for the second region.
> This patch was tested on AM3517.
>
> Signed-off-by: Andrey Skvortsov <[email protected]>
> ---
>
> Commit 3d495383648a ("ARM: dts: Split omap3 pinmux core device") notes that
> Nishanth Menon <[email protected]> said that 3517 does not have padconf2 region.
> Unfortunately I couldn't find reference to his post on mailing list.
> This patch was tested on AM3517 SoC and original vendor code contains
> pinmuxing for this second region as well.
http://www.ti.com/lit/ug/sprugr0c/sprugr0c.pdf
CONTROL_PADCONF_ETK_CLK is indeed at 0x480025D8
Apologies on missing it :(
>
> arch/arm/boot/dts/am3517.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
> index c90724b..2534500 100644
> --- a/arch/arm/boot/dts/am3517.dtsi
> +++ b/arch/arm/boot/dts/am3517.dtsi
> @@ -60,5 +60,16 @@
> dma-names = "tx", "rx";
> clock-frequency = <48000000>;
> };
> +
> + omap3_pmx_core2: pinmux@480025D8 {
> + compatible = "ti,omap3-padconf", "pinctrl-single";
> + reg = <0x480025D8 0x24>;
b8845074cfbbd1d1b46720a1b563d7b4240dac21 ("ARM: dts: omap3: add minimal
l4 bus layout with control module support") moves omap3_pmx_core under
scm -> should'nt we do the same here?
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + pinctrl-single,register-width = <16>;
> + pinctrl-single,function-mask = <0xff1f>;
> + };
> };
> };
>
--
Regards,
Nishanth Menon
According to the technical reference manual for AM35xx system
controller module (SCM) PADCONFS core registers are divided in two
regions: 0x48002030..0x48002268 and 0x480025D8..0x480025FC.
First region is the same for all omap3 SoC and is described in
omap3.dtsi.
The second region is the same as in omap34xx and omap35xx.
The patch adds missing description for the second region.
This patch was tested on AM3517.
Signed-off-by: Andrey Skvortsov <[email protected]>
---
v2:
move omap3_pmx_core2 under l4_core -> scm
arch/arm/boot/dts/am3517.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index f164dce..99b322e 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -63,6 +63,20 @@
};
};
+&scm {
+ omap3_pmx_core2: pinmux@05D8 {
+ compatible = "ti,omap3-padconf",
+ "pinctrl-single";
+ reg = <0x05D8 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0xff1f>;
+ };
+};
+
&iva {
status = "disabled";
};
--
2.1.4
* Andrey Skvortsov <[email protected]> [150510 14:29]:
> According to the technical reference manual for AM35xx system
> controller module (SCM) PADCONFS core registers are divided in two
> regions: 0x48002030..0x48002268 and 0x480025d8..0x480025FC.
> First region is the same for all omap3 SoC and is described in omap3.dtsi.
> The second region is the same as in omap34xx (see omap34xx.dtsi)
> and omap35xx. The patch adds missing description for the second region.
> This patch was tested on AM3517.
>
> Signed-off-by: Andrey Skvortsov <[email protected]>
Applying into omap-for-v4.2/dt thanks.
Tony
> Commit 3d495383648a ("ARM: dts: Split omap3 pinmux core device") notes that
> Nishanth Menon <[email protected]> said that 3517 does not have padconf2 region.
> Unfortunately I couldn't find reference to his post on mailing list.
> This patch was tested on AM3517 SoC and original vendor code contains
> pinmuxing for this second region as well.
>
> arch/arm/boot/dts/am3517.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
> index c90724b..2534500 100644
> --- a/arch/arm/boot/dts/am3517.dtsi
> +++ b/arch/arm/boot/dts/am3517.dtsi
> @@ -60,5 +60,16 @@
> dma-names = "tx", "rx";
> clock-frequency = <48000000>;
> };
> +
> + omap3_pmx_core2: pinmux@480025D8 {
> + compatible = "ti,omap3-padconf", "pinctrl-single";
> + reg = <0x480025D8 0x24>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + pinctrl-single,register-width = <16>;
> + pinctrl-single,function-mask = <0xff1f>;
> + };
> };
> };