Changes in version 2 incorporate Olof's comments regarding:
* the removal of all "Reviewed-by" lines not occurring on external
mailing lists
* reordering of s-o-b lines
* modification of the device tree file to use labels when enabling
* increated description of the modification to the MAINTAINERS entry
Also, modifying the "to" and "cc" recepients so that everyone is
receving all of the patches.
--
This patch series adds support for the Broadcom Northstar Plus family of
SoCs. NSP is a Cortex A9 based SoC under the Broadcom iProc family.
Jon Mason (5):
dt-bindings: Create Documentation for NSP DT bindings
ARM: NSP: add minimal Northstar Plus device tree
ARM: NSP: Add basic support for Broadcom Northstar Plus SoC
ARM: multi_v7_defconfig: Add NSP to defconfig
MAINTAINERS: add entry for the Broadcom Northstar Plus SoCs
.../devicetree/bindings/arm/bcm/brcm,nsp.txt | 34 +++++++
MAINTAINERS | 12 ++-
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/bcm-nsp.dtsi | 105 +++++++++++++++++++++
arch/arm/boot/dts/bcm958625k.dts | 57 +++++++++++
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/mach-bcm/Kconfig | 14 +++
arch/arm/mach-bcm/Makefile | 5 +-
arch/arm/mach-bcm/bcm_nsp.c | 25 +++++
9 files changed, 252 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt
create mode 100644 arch/arm/boot/dts/bcm-nsp.dtsi
create mode 100644 arch/arm/boot/dts/bcm958625k.dts
create mode 100644 arch/arm/mach-bcm/bcm_nsp.c
--
1.9.1
Add the documentation for the Broadcom Northstar Plus device tree
bindings.
Signed-off-by: Jon Mason <[email protected]>
---
.../devicetree/bindings/arm/bcm/brcm,nsp.txt | 34 ++++++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt
new file mode 100644
index 0000000..eae53e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt
@@ -0,0 +1,34 @@
+Broadcom Northstar Plus device tree bindings
+--------------------------------------------
+
+Broadcom Northstar Plus family of SoCs are used for switching control
+and management applications as well as residential router/gateway
+applications. The SoC features dual core Cortex A9 ARM CPUs, integrating
+several peripheral interfaces including multiple Gigabit Ethernet PHYs,
+DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
+SATA and several other IO controllers.
+
+Boards with Northstar Plus SoCs shall have the following properties:
+
+Required root node property:
+
+BCM58522
+compatible = "brcm,bcm58522", "brcm,nsp";
+
+BCM58525
+compatible = "brcm,bcm58525", "brcm,nsp";
+
+BCM58535
+compatible = "brcm,bcm58535", "brcm,nsp";
+
+BCM58622
+compatible = "brcm,bcm58622", "brcm,nsp";
+
+BCM58623
+compatible = "brcm,bcm58623", "brcm,nsp";
+
+BCM58625
+compatible = "brcm,bcm58625", "brcm,nsp";
+
+BCM88312
+compatible = "brcm,bcm88312", "brcm,nsp";
--
1.9.1
Add a very minimalistic set of Northstar Plus Device Tree files which
describes the SoC and the BCM958625 implementation. The perpherials
described are:
ARM Cortex A9 CPU
2 8250 UARTs
ARM GIC
PL310 L2 Cache
ARM A9 Global timer
Signed-off-by: Kapil Hali <[email protected]>
Signed-off-by: Jon Mason <[email protected]>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/bcm-nsp.dtsi | 105 +++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/bcm958625k.dts | 57 +++++++++++++++++++++
3 files changed, 164 insertions(+)
create mode 100644 arch/arm/boot/dts/bcm-nsp.dtsi
create mode 100644 arch/arm/boot/dts/bcm958625k.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 246473a..adb5732 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -82,6 +82,8 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
dtb-$(CONFIG_ARCH_BCM_MOBILE) += \
bcm28155-ap.dtb \
bcm21664-garnet.dtb
+dtb-$(CONFIG_ARCH_BCM_NSP) += \
+ bcm958625k.dtb
dtb-$(CONFIG_ARCH_BERLIN) += \
berlin2-sony-nsz-gs7.dtb \
berlin2cd-google-chromecast.dtb \
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
new file mode 100644
index 0000000..77f9bfc
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -0,0 +1,105 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,nsp";
+ model = "Broadcom Northstar Plus SoC";
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ reg = <0x0>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ periph_clk: periph_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <500000000>;
+ };
+ };
+
+ uart0: serial@18000300 {
+ compatible = "ns16550a";
+ reg = <0x18000300 0x100>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <62499840>;
+ status = "disabled";
+ };
+
+ uart1: serial@18000400 {
+ compatible = "ns16550a";
+ reg = <0x18000400 0x100>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <62499840>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@19021000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x19021000 0x1000>,
+ <0x19020100 0x100>;
+ };
+
+ L2: l2-cache {
+ compatible = "arm,pl310-cache";
+ reg = <0x19022000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ timer@19020200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x19020200 0x100>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&periph_clk>;
+ };
+};
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
new file mode 100644
index 0000000..16303db
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -0,0 +1,57 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm-nsp.dtsi"
+
+/ {
+ model = "NorthStar Plus SVK (BCM958625K)";
+ compatible = "brcm,bcm58625", "brcm,nsp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
--
1.9.1
Broadcom Northstar Plus family of SoCs are used for switching
control and management applications as well as residential
router/gateway applications. The SoC features dual core Cortex
A9 ARM CPUs, integrating several peripheral interfaces including
multiple Gigabit Ethernet PHYs, DDR3 memory, PCIE Gen-2, USB 2.0
and USB 3.0, serial and NAND flash, SATA and several other IO
controllers.
Signed-off-by: Kapil Hali <[email protected]>
Signed-off-by: Jon Mason <[email protected]>
---
arch/arm/mach-bcm/Kconfig | 14 ++++++++++++++
arch/arm/mach-bcm/Makefile | 5 ++++-
arch/arm/mach-bcm/bcm_nsp.c | 25 +++++++++++++++++++++++++
3 files changed, 43 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-bcm/bcm_nsp.c
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 0ac9e4b3..22c85b1 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -35,6 +35,20 @@ config ARCH_BCM_CYGNUS
BCM11300, BCM11320, BCM11350, BCM11360,
BCM58300, BCM58302, BCM58303, BCM58305.
+config ARCH_BCM_NSP
+ bool "Broadcom Northstar Plus SoC Support" if ARCH_MULTI_V7
+ select ARCH_BCM_IPROC
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_775420
+ help
+ Support for Broadcom Northstar Plus SoC.
+ Broadcom Northstar Plus family of SoCs are used for switching control
+ and management applications as well as residential router/gateway
+ applications. The SoC features dual core Cortex A9 ARM CPUs,
+ integrating several peripheral interfaces including multiple Gigabit
+ Ethernet PHYs, DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and
+ NAND flash, SATA and several other IO controllers.
+
config ARCH_BCM_5301X
bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
select ARCH_BCM_IPROC
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 4fb0da4..786d720 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2012-2014 Broadcom Corporation
+# Copyright (C) 2012-2015 Broadcom Corporation
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
@@ -13,6 +13,9 @@
# Cygnus
obj-$(CONFIG_ARCH_BCM_CYGNUS) += bcm_cygnus.o
+# Northstar Plus
+obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
+
# BCM281XX
obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
diff --git a/arch/arm/mach-bcm/bcm_nsp.c b/arch/arm/mach-bcm/bcm_nsp.c
new file mode 100644
index 0000000..a1101a3
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_nsp.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/mach/arch.h>
+
+static const char *const bcm_nsp_dt_compat[] __initconst = {
+ "brcm,nsp",
+ NULL,
+};
+
+DT_MACHINE_START(NSP_DT, "Broadcom Northstar Plus SoC")
+ .l2c_aux_val = 0,
+ .l2c_aux_mask = ~0,
+ .dt_compat = bcm_nsp_dt_compat,
+MACHINE_END
--
1.9.1
Add the Broadcom Northstar Plus SoC to the multi_v7_defconfig
Signed-off-by: Jon Mason <[email protected]>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 5fd8df6..3fd46f7 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -25,6 +25,7 @@ CONFIG_SOC_SAMA5D3=y
CONFIG_SOC_SAMA5D4=y
CONFIG_ARCH_BCM=y
CONFIG_ARCH_BCM_CYGNUS=y
+CONFIG_ARCH_BCM_NSP=y
CONFIG_ARCH_BCM_21664=y
CONFIG_ARCH_BCM_281XX=y
CONFIG_ARCH_BCM_5301X=y
--
1.9.1
Modify the iProc MAINTAINER to cover the Nortstar Plus SoCs, and add me
to the list of people responsible for it. Since iProc is a family of
SoCs that includes more than just Cygnus (i.e., Northstar (BCM5301X),
Northstar Plus, Northstar 2, and a number of other platforms), remove it
from the title to avoid any future confusion.
Signed-off-by: Jon Mason <[email protected]>
Acked-by: Scott Branden <[email protected]>
---
MAINTAINERS | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a9ae6c1..4b851f5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2315,19 +2315,27 @@ L: [email protected]
S: Supported
F: drivers/scsi/bnx2i/
-BROADCOM CYGNUS/IPROC ARM ARCHITECTURE
+BROADCOM IPROC ARM ARCHITECTURE
M: Ray Jui <[email protected]>
M: Scott Branden <[email protected]>
+M: Jon Mason <[email protected]>
L: [email protected] (moderated for non-subscribers)
L: [email protected]
T: git git://github.com/broadcom/cygnus-linux.git
S: Maintained
N: iproc
N: cygnus
+N: nsp
N: bcm9113*
N: bcm9583*
-N: bcm583*
+N: bcm9585*
+N: bcm9586*
+N: bcm988312
N: bcm113*
+N: bcm583*
+N: bcm585*
+N: bcm586*
+N: bcm88312
BROADCOM BRCMSTB GPIO DRIVER
M: Gregory Fong <[email protected]>
--
1.9.1
Patchset all look good.
Acked-by: Scott Branden <[email protected]>
On 15-08-26 03:35 PM, Jon Mason wrote:
>
> Changes in version 2 incorporate Olof's comments regarding:
> * the removal of all "Reviewed-by" lines not occurring on external
> mailing lists
> * reordering of s-o-b lines
> * modification of the device tree file to use labels when enabling
> * increated description of the modification to the MAINTAINERS entry
>
> Also, modifying the "to" and "cc" recepients so that everyone is
> receving all of the patches.
>
> --
>
> This patch series adds support for the Broadcom Northstar Plus family of
> SoCs. NSP is a Cortex A9 based SoC under the Broadcom iProc family.
>
> Jon Mason (5):
> dt-bindings: Create Documentation for NSP DT bindings
> ARM: NSP: add minimal Northstar Plus device tree
> ARM: NSP: Add basic support for Broadcom Northstar Plus SoC
> ARM: multi_v7_defconfig: Add NSP to defconfig
> MAINTAINERS: add entry for the Broadcom Northstar Plus SoCs
>
> .../devicetree/bindings/arm/bcm/brcm,nsp.txt | 34 +++++++
> MAINTAINERS | 12 ++-
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/bcm-nsp.dtsi | 105 +++++++++++++++++++++
> arch/arm/boot/dts/bcm958625k.dts | 57 +++++++++++
> arch/arm/configs/multi_v7_defconfig | 1 +
> arch/arm/mach-bcm/Kconfig | 14 +++
> arch/arm/mach-bcm/Makefile | 5 +-
> arch/arm/mach-bcm/bcm_nsp.c | 25 +++++
> 9 files changed, 252 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp.txt
> create mode 100644 arch/arm/boot/dts/bcm-nsp.dtsi
> create mode 100644 arch/arm/boot/dts/bcm958625k.dts
> create mode 100644 arch/arm/mach-bcm/bcm_nsp.c
>
On 26/08/15 15:35, Jon Mason wrote:
> Broadcom Northstar Plus family of SoCs are used for switching
> control and management applications as well as residential
> router/gateway applications. The SoC features dual core Cortex
> A9 ARM CPUs, integrating several peripheral interfaces including
> multiple Gigabit Ethernet PHYs, DDR3 memory, PCIE Gen-2, USB 2.0
> and USB 3.0, serial and NAND flash, SATA and several other IO
> controllers.
>
> Signed-off-by: Kapil Hali <[email protected]>
> Signed-off-by: Jon Mason <[email protected]>
Applied to soc/next at github.com/stblinux, thanks!
This is a little late for 4.3, so this will be queued for 4.4, thanks!
--
Florian
On 26/08/15 15:35, Jon Mason wrote:
> Add the documentation for the Broadcom Northstar Plus device tree
> bindings.
>
> Signed-off-by: Jon Mason <[email protected]>
Applied to devicetree/next, thanks!
--
Florian
On 26/08/15 15:35, Jon Mason wrote:
> Add a very minimalistic set of Northstar Plus Device Tree files which
> describes the SoC and the BCM958625 implementation. The perpherials
> described are:
>
> ARM Cortex A9 CPU
> 2 8250 UARTs
> ARM GIC
> PL310 L2 Cache
> ARM A9 Global timer
>
> Signed-off-by: Kapil Hali <[email protected]>
> Signed-off-by: Jon Mason <[email protected]>
Applied to devicetree/next, thanks!
--
Florian
On 26/08/15 15:35, Jon Mason wrote:
> Modify the iProc MAINTAINER to cover the Nortstar Plus SoCs, and add me
> to the list of people responsible for it. Since iProc is a family of
> SoCs that includes more than just Cygnus (i.e., Northstar (BCM5301X),
> Northstar Plus, Northstar 2, and a number of other platforms), remove it
> from the title to avoid any future confusion.
>
> Signed-off-by: Jon Mason <[email protected]>
> Acked-by: Scott Branden <[email protected]>
Applied to maintainers/next, thanks!
--
Florian
On 26/08/15 15:35, Jon Mason wrote:
> Add the Broadcom Northstar Plus SoC to the multi_v7_defconfig
>
> Signed-off-by: Jon Mason <[email protected]>
Applied to defconfig/next, thanks!
--
Florian
On Wed, Aug 26, 2015 at 5:35 PM, Jon Mason <[email protected]> wrote:
> Add a very minimalistic set of Northstar Plus Device Tree files which
> describes the SoC and the BCM958625 implementation. The perpherials
> described are:
>
> ARM Cortex A9 CPU
> 2 8250 UARTs
> ARM GIC
> PL310 L2 Cache
> ARM A9 Global timer
>
> Signed-off-by: Kapil Hali <[email protected]>
> Signed-off-by: Jon Mason <[email protected]>
> ---
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/bcm-nsp.dtsi | 105 +++++++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/bcm958625k.dts | 57 +++++++++++++++++++++
> 3 files changed, 164 insertions(+)
> create mode 100644 arch/arm/boot/dts/bcm-nsp.dtsi
> create mode 100644 arch/arm/boot/dts/bcm958625k.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 246473a..adb5732 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -82,6 +82,8 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
> dtb-$(CONFIG_ARCH_BCM_MOBILE) += \
> bcm28155-ap.dtb \
> bcm21664-garnet.dtb
> +dtb-$(CONFIG_ARCH_BCM_NSP) += \
> + bcm958625k.dtb
> dtb-$(CONFIG_ARCH_BERLIN) += \
> berlin2-sony-nsz-gs7.dtb \
> berlin2cd-google-chromecast.dtb \
> diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
> new file mode 100644
> index 0000000..77f9bfc
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm-nsp.dtsi
> @@ -0,0 +1,105 @@
> +/*
> + * BSD LICENSE
> + *
> + * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + *
> + * * Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * * Redistributions in binary form must reproduce the above copyright
> + * notice, this list of conditions and the following disclaimer in
> + * the documentation and/or other materials provided with the
> + * distribution.
> + * * Neither the name of Broadcom Corporation nor the names of its
> + * contributors may be used to endorse or promote products derived
> + * from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +#include "skeleton.dtsi"
> +
> +/ {
> + compatible = "brcm,nsp";
> + model = "Broadcom Northstar Plus SoC";
> + interrupt-parent = <&gic>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + next-level-cache = <&L2>;
> + reg = <0x0>;
> + };
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + periph_clk: periph_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <500000000>;
> + };
> + };
> +
> + uart0: serial@18000300 {
All these devices should go under a bus node.
> + compatible = "ns16550a";
> + reg = <0x18000300 0x100>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <62499840>;
> + status = "disabled";
> + };
> +
> + uart1: serial@18000400 {
> + compatible = "ns16550a";
> + reg = <0x18000400 0x100>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <62499840>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller@19021000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x19021000 0x1000>,
> + <0x19020100 0x100>;
> + };
> +
> + L2: l2-cache {
> + compatible = "arm,pl310-cache";
> + reg = <0x19022000 0x1000>;
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> + timer@19020200 {
> + compatible = "arm,cortex-a9-global-timer";
> + reg = <0x19020200 0x100>;
> + interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&periph_clk>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
> new file mode 100644
> index 0000000..16303db
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm958625k.dts
> @@ -0,0 +1,57 @@
> +/*
> + * BSD LICENSE
> + *
> + * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + *
> + * * Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * * Redistributions in binary form must reproduce the above copyright
> + * notice, this list of conditions and the following disclaimer in
> + * the documentation and/or other materials provided with the
> + * distribution.
> + * * Neither the name of Broadcom Corporation nor the names of its
> + * contributors may be used to endorse or promote products derived
> + * from this software without specific prior written permission.
> + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
> + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/dts-v1/;
> +
> +#include "bcm-nsp.dtsi"
> +
> +/ {
> + model = "NorthStar Plus SVK (BCM958625K)";
> + compatible = "brcm,bcm58625", "brcm,nsp";
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> --
> 1.9.1
>
On 28/08/15 08:41, Rob Herring wrote:
> On Wed, Aug 26, 2015 at 5:35 PM, Jon Mason <[email protected]> wrote:
>> Add a very minimalistic set of Northstar Plus Device Tree files which
>> describes the SoC and the BCM958625 implementation. The perpherials
>> described are:
>>
>> ARM Cortex A9 CPU
>> 2 8250 UARTs
>> ARM GIC
>> PL310 L2 Cache
>> ARM A9 Global timer
>>
>> Signed-off-by: Kapil Hali <[email protected]>
>> Signed-off-by: Jon Mason <[email protected]>
>> ---
[snip]
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + periph_clk: periph_clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <500000000>;
>> + };
>> + };
>> +
>> + uart0: serial@18000300 {
>
> All these devices should go under a bus node.
Jon, you can send a replacement patch and I would drop this one. Thanks!
--
Florian