Hi,
Switch to use the new eDMA bindings and enable DMA for MMC0, SPI1.
Add node for MMC1.
Regards,
Peter
---
Peter Ujfalusi (6):
ARM: DTS: da850: fix edma0 reg space
ARM: DTS: da850: Use the new DT bindings for the eDMA3
ARM: DTS: da850: Enable eDMA1
ARM: DTS: da850: Enable DMA use for MMC0
ARM: DTS: da850: Add node for mmc1
ARM: DTS: da850: Enable DMA for SPI1
arch/arm/boot/dts/da850-enbw-cmc.dts | 9 ++++++
arch/arm/boot/dts/da850-evm.dts | 9 ++++++
arch/arm/boot/dts/da850.dtsi | 59 ++++++++++++++++++++++++++++++++----
3 files changed, 71 insertions(+), 6 deletions(-)
--
2.6.3
The size of the eDMA0 CC register space is 0x8000 and not 0x10000.
Signed-off-by: Peter Ujfalusi <[email protected]>
---
arch/arm/boot/dts/da850.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 0bd98cd00816..e73f5efb3aa3 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -152,7 +152,8 @@
};
edma0: edma@01c00000 {
compatible = "ti,edma3";
- reg = <0x0 0x10000>;
+ /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
+ reg = <0x0 0x8000>;
interrupts = <11 13 12>;
#dma-cells = <1>;
};
--
2.6.3
Switch to use the ti,edma3-tpcc and ti,edma3-tptc binding for the eDMA3.
With the new bindings boards can customize and tweak the DMA channel
priority to match their needs. With the new binding the memcpy is safe
to be used since with the old binding it was not possible for a driver
to know which channel is allowed to be used as non HW triggered channel.
Using the new binding will allow us to reserve PaRAM slots to be used by
the DSP which was not possible before and prevented the da850 boards to be
moved to DT only.
Signed-off-by: Peter Ujfalusi <[email protected]>
---
arch/arm/boot/dts/da850-enbw-cmc.dts | 5 +++++
arch/arm/boot/dts/da850-evm.dts | 5 +++++
arch/arm/boot/dts/da850.dtsi | 27 ++++++++++++++++++++++-----
3 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts
index e750ab9086d5..ca9117624cf9 100644
--- a/arch/arm/boot/dts/da850-enbw-cmc.dts
+++ b/arch/arm/boot/dts/da850-enbw-cmc.dts
@@ -28,3 +28,8 @@
};
};
};
+
+&edma0 {
+ ti,edma-reserved-slot-ranges = /bits/ 16 <32 50>;
+ ti,edma-memcpy-channels = /bits/ 16 <20 21>;
+};
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index d807285a61cd..33467feb272a 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -243,3 +243,8 @@
tx-num-evt = <32>;
rx-num-evt = <32>;
};
+
+&edma0 {
+ ti,edma-reserved-slot-ranges = /bits/ 16 <32 50>;
+ ti,edma-memcpy-channels = /bits/ 16 <20 21>;
+};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index e73f5efb3aa3..9e46eb51a8da 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -151,11 +151,28 @@
};
edma0: edma@01c00000 {
- compatible = "ti,edma3";
+ compatible = "ti,edma3-tpcc";
/* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
reg = <0x0 0x8000>;
- interrupts = <11 13 12>;
- #dma-cells = <1>;
+ reg-names = "edma3_cc";
+ interrupts = <11 12>;
+ interrupt-names = "edma3_ccint", "edma3_ccerrint";
+ #dma-cells = <2>;
+
+ ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
+ ti,edma-memcpy-channels = /bits/ 16 <20 21>;
+ };
+ edma0_tptc0: tptc@01c08000 {
+ compatible = "ti,edma3-tptc";
+ reg = <0x8000 0x400>;
+ interrupts = <13>;
+ interrupt-names = "edm3_tcerrint";
+ };
+ edma0_tptc1: tptc@01c08400 {
+ compatible = "ti,edma3-tptc";
+ reg = <0x8400 0x400>;
+ interrupts = <32>;
+ interrupt-names = "edm3_tcerrint";
};
serial0: serial@1c42000 {
compatible = "ns16550a";
@@ -286,8 +303,8 @@
interrupts = <54>;
interrupt-names = "common";
status = "disabled";
- dmas = <&edma0 1>,
- <&edma0 0>;
+ dmas = <&edma0 1 1>,
+ <&edma0 0 1>;
dma-names = "tx", "rx";
};
};
--
2.6.3
The eDMA1 in da850 has only one TPTC and for example MMC1 is HW events are
handled by it.
Signed-off-by: Peter Ujfalusi <[email protected]>
---
arch/arm/boot/dts/da850-enbw-cmc.dts | 4 ++++
arch/arm/boot/dts/da850-evm.dts | 4 ++++
arch/arm/boot/dts/da850.dtsi | 17 +++++++++++++++++
3 files changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts
index ca9117624cf9..44f0dd1866f9 100644
--- a/arch/arm/boot/dts/da850-enbw-cmc.dts
+++ b/arch/arm/boot/dts/da850-enbw-cmc.dts
@@ -33,3 +33,7 @@
ti,edma-reserved-slot-ranges = /bits/ 16 <32 50>;
ti,edma-memcpy-channels = /bits/ 16 <20 21>;
};
+
+&edma1 {
+ ti,edma-reserved-slot-ranges = /bits/ 16 <32 90>;
+};
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 33467feb272a..70ef9c642ac9 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -248,3 +248,7 @@
ti,edma-reserved-slot-ranges = /bits/ 16 <32 50>;
ti,edma-memcpy-channels = /bits/ 16 <20 21>;
};
+
+&edma1 {
+ ti,edma-reserved-slot-ranges = /bits/ 16 <32 90>;
+};
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 9e46eb51a8da..e311d73a5265 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -174,6 +174,23 @@
interrupts = <32>;
interrupt-names = "edm3_tcerrint";
};
+ edma1: edma@01e30000 {
+ compatible = "ti,edma3-tpcc";
+ /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
+ reg = <0x230000 0x8000>;
+ reg-names = "edma3_cc";
+ interrupts = <93 94>;
+ interrupt-names = "edma3_ccint", "edma3_ccerrint";
+ #dma-cells = <2>;
+
+ ti,tptcs = <&edma1_tptc0 7>;
+ };
+ edma1_tptc0: tptc@01e38000 {
+ compatible = "ti,edma3-tptc";
+ reg = <0x238000 0x400>;
+ interrupts = <95>;
+ interrupt-names = "edm3_tcerrint";
+ };
serial0: serial@1c42000 {
compatible = "ns16550a";
reg = <0x42000 0x100>;
--
2.6.3
Add the needed bindings for MMC0 in order to be able to utilize the DMA
instead of PIO mode.
Signed-off-by: Peter Ujfalusi <[email protected]>
---
arch/arm/boot/dts/da850.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index e311d73a5265..ccaaf2746aca 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -236,6 +236,8 @@
compatible = "ti,da830-mmc";
reg = <0x40000 0x1000>;
interrupts = <16>;
+ dmas = <&edma0 16 0>, <&edma0 17 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
ehrpwm0: ehrpwm@01f00000 {
--
2.6.3
da850 has two MMC controller, MMCSD1 is served by eDMA1
Signed-off-by: Peter Ujfalusi <[email protected]>
---
arch/arm/boot/dts/da850.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index ccaaf2746aca..edaf69ec03a9 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -240,6 +240,14 @@
dma-names = "rx", "tx";
status = "disabled";
};
+ mmc1: mmc@1e1b000 {
+ compatible = "ti,da830-mmc";
+ reg = <0x21b000 0x1000>;
+ interrupts = <72>;
+ dmas = <&edma1 28 0>, <&edma1 29 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
ehrpwm0: ehrpwm@01f00000 {
compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
--
2.6.3
Add the needed bindings so the SPI driver can use DMA with SPI1.
Signed-off-by: Peter Ujfalusi <[email protected]>
---
arch/arm/boot/dts/da850.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index edaf69ec03a9..fc7866657a4e 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -286,6 +286,8 @@
num-cs = <4>;
ti,davinci-spi-intr-line = <1>;
interrupts = <56>;
+ dmas = <&edma0 18 0>, <&edma0 19 0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
mdio: mdio@1e24000 {
--
2.6.3
Sekhar,
On 12/04/2015 03:53 PM, Peter Ujfalusi wrote:
> Hi,
>
> Switch to use the new eDMA bindings and enable DMA for MMC0, SPI1.
> Add node for MMC1.
Can you hold on this one for a bit since the eDMA bindings might change still.
>
> Regards,
> Peter
> ---
> Peter Ujfalusi (6):
> ARM: DTS: da850: fix edma0 reg space
> ARM: DTS: da850: Use the new DT bindings for the eDMA3
> ARM: DTS: da850: Enable eDMA1
> ARM: DTS: da850: Enable DMA use for MMC0
> ARM: DTS: da850: Add node for mmc1
> ARM: DTS: da850: Enable DMA for SPI1
>
> arch/arm/boot/dts/da850-enbw-cmc.dts | 9 ++++++
> arch/arm/boot/dts/da850-evm.dts | 9 ++++++
> arch/arm/boot/dts/da850.dtsi | 59 ++++++++++++++++++++++++++++++++----
> 3 files changed, 71 insertions(+), 6 deletions(-)
>
--
P?ter
On Wednesday 09 December 2015 12:49 PM, Peter Ujfalusi wrote:
> Sekhar,
>
> On 12/04/2015 03:53 PM, Peter Ujfalusi wrote:
>> Hi,
>>
>> Switch to use the new eDMA bindings and enable DMA for MMC0, SPI1.
>> Add node for MMC1.
>
> Can you hold on this one for a bit since the eDMA bindings might change still.
Sure, no problem!
Thanks,
Sekhar
On Friday 04 December 2015 07:23 PM, Peter Ujfalusi wrote:
> Hi,
>
> Switch to use the new eDMA bindings and enable DMA for MMC0, SPI1.
> Add node for MMC1.
Tested MMC0 and SPI1 for DMA transfer using these patches on DA850 EVM.
You can add:
Tested-by: Sushaanth Srirangapathi <[email protected]>
Regards,
Sushaanth
Hi Peter,
On Friday 04 December 2015 07:23 PM, Peter Ujfalusi wrote:
> Switch to use the ti,edma3-tpcc and ti,edma3-tptc binding for the eDMA3.
> With the new bindings boards can customize and tweak the DMA channel
> priority to match their needs. With the new binding the memcpy is safe
> to be used since with the old binding it was not possible for a driver
> to know which channel is allowed to be used as non HW triggered channel.
> Using the new binding will allow us to reserve PaRAM slots to be used by
> the DSP which was not possible before and prevented the da850 boards to be
> moved to DT only.
>
> Signed-off-by: Peter Ujfalusi <[email protected]>
> ---
> arch/arm/boot/dts/da850-enbw-cmc.dts | 5 +++++
> arch/arm/boot/dts/da850-evm.dts | 5 +++++
> arch/arm/boot/dts/da850.dtsi | 27 ++++++++++++++++++++++-----
> 3 files changed, 32 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts
> index e750ab9086d5..ca9117624cf9 100644
> --- a/arch/arm/boot/dts/da850-enbw-cmc.dts
> +++ b/arch/arm/boot/dts/da850-enbw-cmc.dts
> @@ -28,3 +28,8 @@
> };
> };
> };
> +
> +&edma0 {
> + ti,edma-reserved-slot-ranges = /bits/ 16 <32 50>;
> + ti,edma-memcpy-channels = /bits/ 16 <20 21>;
> +};
> diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
> index d807285a61cd..33467feb272a 100644
> --- a/arch/arm/boot/dts/da850-evm.dts
> +++ b/arch/arm/boot/dts/da850-evm.dts
> @@ -243,3 +243,8 @@
> tx-num-evt = <32>;
> rx-num-evt = <32>;
> };
> +
> +&edma0 {
> + ti,edma-reserved-slot-ranges = /bits/ 16 <32 50>;
> + ti,edma-memcpy-channels = /bits/ 16 <20 21>;
These correspond to PRU events. It is true that most likely they will
never be used for peripheral DMA and can be dedicated as memcpy
channels. However, since this is being encoded in DT, we need to be sure
that they will never be used for peripheral DMA on this board.
So, I would prefer if you do not reserve any channels for memcpy until
there is a real need/usecase for them. I know the board file has these
reserved but board file could be updated as you liked. With DT we need
to maintain backward compatibility. So I would rather do it when there
is an actual need for it.
In future, if/when we gain QDMA support, the QDMA channels could be used
for memcopy.
> +};
> diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
> index e73f5efb3aa3..9e46eb51a8da 100644
> --- a/arch/arm/boot/dts/da850.dtsi
> +++ b/arch/arm/boot/dts/da850.dtsi
> @@ -151,11 +151,28 @@
>
> };
> edma0: edma@01c00000 {
> - compatible = "ti,edma3";
> + compatible = "ti,edma3-tpcc";
> /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
> reg = <0x0 0x8000>;
> - interrupts = <11 13 12>;
> - #dma-cells = <1>;
> + reg-names = "edma3_cc";
> + interrupts = <11 12>;
> + interrupt-names = "edma3_ccint", "edma3_ccerrint";
> + #dma-cells = <2>;
> +
> + ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
> + ti,edma-memcpy-channels = /bits/ 16 <20 21>;
Same here. I would drop this.
Thanks,
Sekhar
On 12/15/2015 11:38 AM, Sekhar Nori wrote:
> Hi Peter,
>
> On Friday 04 December 2015 07:23 PM, Peter Ujfalusi wrote:
>> Switch to use the ti,edma3-tpcc and ti,edma3-tptc binding for the eDMA3.
>> With the new bindings boards can customize and tweak the DMA channel
>> priority to match their needs. With the new binding the memcpy is safe
>> to be used since with the old binding it was not possible for a driver
>> to know which channel is allowed to be used as non HW triggered channel.
>> Using the new binding will allow us to reserve PaRAM slots to be used by
>> the DSP which was not possible before and prevented the da850 boards to be
>> moved to DT only.
>>
>> Signed-off-by: Peter Ujfalusi <[email protected]>
>> ---
>> arch/arm/boot/dts/da850-enbw-cmc.dts | 5 +++++
>> arch/arm/boot/dts/da850-evm.dts | 5 +++++
>> arch/arm/boot/dts/da850.dtsi | 27 ++++++++++++++++++++++-----
>> 3 files changed, 32 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts
>> index e750ab9086d5..ca9117624cf9 100644
>> --- a/arch/arm/boot/dts/da850-enbw-cmc.dts
>> +++ b/arch/arm/boot/dts/da850-enbw-cmc.dts
>> @@ -28,3 +28,8 @@
>> };
>> };
>> };
>> +
>> +&edma0 {
>> + ti,edma-reserved-slot-ranges = /bits/ 16 <32 50>;
>> + ti,edma-memcpy-channels = /bits/ 16 <20 21>;
>> +};
>> diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
>> index d807285a61cd..33467feb272a 100644
>> --- a/arch/arm/boot/dts/da850-evm.dts
>> +++ b/arch/arm/boot/dts/da850-evm.dts
>> @@ -243,3 +243,8 @@
>> tx-num-evt = <32>;
>> rx-num-evt = <32>;
>> };
>> +
>> +&edma0 {
>> + ti,edma-reserved-slot-ranges = /bits/ 16 <32 50>;
>> + ti,edma-memcpy-channels = /bits/ 16 <20 21>;
>
> These correspond to PRU events. It is true that most likely they will
> never be used for peripheral DMA and can be dedicated as memcpy
> channels. However, since this is being encoded in DT, we need to be sure
> that they will never be used for peripheral DMA on this board.
>
> So, I would prefer if you do not reserve any channels for memcpy until
> there is a real need/usecase for them. I know the board file has these
> reserved but board file could be updated as you liked. With DT we need
> to maintain backward compatibility. So I would rather do it when there
> is an actual need for it.
If we do not reserve channels for memcpy then you will have no support for
memcpy on these boards. Not sure if we use memcpy in any of our drivers in
daVinci, so it might be just fine to not have DMA memcpy support at all.
But how about using edma1's reserved channels as memcpy (19-23, 30-31)? I
don't know which channels the DSP would use on these boards, so it is never
going to be safe from that point.
> In future, if/when we gain QDMA support, the QDMA channels could be used
> for memcopy.
Well, in short there is no way to get the qDMA working in a different way
either. qDMA channel is in essence using 'normal' eDMA channel. This means
that we still need to reserve the eDMA channel to be used for memcpy, but
instead of SW triggering it (as we do it right now), we would need to use the
channel as qDMA and set things up accordingly. I don't really see the benefit
for qDMA mode to be honest.
>
>> +};
>> diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
>> index e73f5efb3aa3..9e46eb51a8da 100644
>> --- a/arch/arm/boot/dts/da850.dtsi
>> +++ b/arch/arm/boot/dts/da850.dtsi
>> @@ -151,11 +151,28 @@
>>
>> };
>> edma0: edma@01c00000 {
>> - compatible = "ti,edma3";
>> + compatible = "ti,edma3-tpcc";
>> /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
>> reg = <0x0 0x8000>;
>> - interrupts = <11 13 12>;
>> - #dma-cells = <1>;
>> + reg-names = "edma3_cc";
>> + interrupts = <11 12>;
>> + interrupt-names = "edma3_ccint", "edma3_ccerrint";
>> + #dma-cells = <2>;
>> +
>> + ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
>> + ti,edma-memcpy-channels = /bits/ 16 <20 21>;
>
> Same here. I would drop this.
OK, I'll drop this part.
>
> Thanks,
> Sekhar
>
--
P?ter
On Tuesday 15 December 2015 05:14 PM, Peter Ujfalusi wrote:
> On 12/15/2015 11:38 AM, Sekhar Nori wrote:
>> Hi Peter,
>>
>> On Friday 04 December 2015 07:23 PM, Peter Ujfalusi wrote:
>>> Switch to use the ti,edma3-tpcc and ti,edma3-tptc binding for the eDMA3.
>>> With the new bindings boards can customize and tweak the DMA channel
>>> priority to match their needs. With the new binding the memcpy is safe
>>> to be used since with the old binding it was not possible for a driver
>>> to know which channel is allowed to be used as non HW triggered channel.
>>> Using the new binding will allow us to reserve PaRAM slots to be used by
>>> the DSP which was not possible before and prevented the da850 boards to be
>>> moved to DT only.
>>>
>>> Signed-off-by: Peter Ujfalusi <[email protected]>
>>> ---
>>> arch/arm/boot/dts/da850-enbw-cmc.dts | 5 +++++
>>> arch/arm/boot/dts/da850-evm.dts | 5 +++++
>>> arch/arm/boot/dts/da850.dtsi | 27 ++++++++++++++++++++++-----
>>> 3 files changed, 32 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts
>>> index e750ab9086d5..ca9117624cf9 100644
>>> --- a/arch/arm/boot/dts/da850-enbw-cmc.dts
>>> +++ b/arch/arm/boot/dts/da850-enbw-cmc.dts
>>> @@ -28,3 +28,8 @@
>>> };
>>> };
>>> };
>>> +
>>> +&edma0 {
>>> + ti,edma-reserved-slot-ranges = /bits/ 16 <32 50>;
>>> + ti,edma-memcpy-channels = /bits/ 16 <20 21>;
>>> +};
>>> diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
>>> index d807285a61cd..33467feb272a 100644
>>> --- a/arch/arm/boot/dts/da850-evm.dts
>>> +++ b/arch/arm/boot/dts/da850-evm.dts
>>> @@ -243,3 +243,8 @@
>>> tx-num-evt = <32>;
>>> rx-num-evt = <32>;
>>> };
>>> +
>>> +&edma0 {
>>> + ti,edma-reserved-slot-ranges = /bits/ 16 <32 50>;
>>> + ti,edma-memcpy-channels = /bits/ 16 <20 21>;
>>
>> These correspond to PRU events. It is true that most likely they will
>> never be used for peripheral DMA and can be dedicated as memcpy
>> channels. However, since this is being encoded in DT, we need to be sure
>> that they will never be used for peripheral DMA on this board.
>>
>> So, I would prefer if you do not reserve any channels for memcpy until
>> there is a real need/usecase for them. I know the board file has these
>> reserved but board file could be updated as you liked. With DT we need
>> to maintain backward compatibility. So I would rather do it when there
>> is an actual need for it.
>
> If we do not reserve channels for memcpy then you will have no support for
> memcpy on these boards. Not sure if we use memcpy in any of our drivers in
> daVinci, so it might be just fine to not have DMA memcpy support at all.
Not that I know of. No driver uses DMA memcpy
> But how about using edma1's reserved channels as memcpy (19-23, 30-31)? I
I think this is much more reasonable.
> don't know which channels the DSP would use on these boards, so it is never
> going to be safe from that point.
Yeah, and thats why I think its better to add it as and when there is a
real need for it. At least at that point we are sure of the usecase.
>
>> In future, if/when we gain QDMA support, the QDMA channels could be used
>> for memcopy.
>
> Well, in short there is no way to get the qDMA working in a different way
> either. qDMA channel is in essence using 'normal' eDMA channel. This means
> that we still need to reserve the eDMA channel to be used for memcpy, but
> instead of SW triggering it (as we do it right now), we would need to use the
> channel as qDMA and set things up accordingly. I don't really see the benefit
> for qDMA mode to be honest.
I guess the only advantage is that they will not clash with peripheral
mode usage. But even then, some sort of reservation is needed. So I
guess QDMA is no better than the EDMA reserved channels?
>>
>>> +};
>>> diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
>>> index e73f5efb3aa3..9e46eb51a8da 100644
>>> --- a/arch/arm/boot/dts/da850.dtsi
>>> +++ b/arch/arm/boot/dts/da850.dtsi
>>> @@ -151,11 +151,28 @@
>>>
>>> };
>>> edma0: edma@01c00000 {
>>> - compatible = "ti,edma3";
>>> + compatible = "ti,edma3-tpcc";
>>> /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
>>> reg = <0x0 0x8000>;
>>> - interrupts = <11 13 12>;
>>> - #dma-cells = <1>;
>>> + reg-names = "edma3_cc";
>>> + interrupts = <11 12>;
>>> + interrupt-names = "edma3_ccint", "edma3_ccerrint";
>>> + #dma-cells = <2>;
>>> +
>>> + ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
>>> + ti,edma-memcpy-channels = /bits/ 16 <20 21>;
>>
>> Same here. I would drop this.
>
> OK, I'll drop this part.
For now, I think its better to not add any reservation. It can be added
when its really needed.
Thanks,
Sekhar
On 12/15/2015 03:48 PM, Sekhar Nori wrote:
>>> These correspond to PRU events. It is true that most likely they will
>>> never be used for peripheral DMA and can be dedicated as memcpy
>>> channels. However, since this is being encoded in DT, we need to be sure
>>> that they will never be used for peripheral DMA on this board.
>>>
>>> So, I would prefer if you do not reserve any channels for memcpy until
>>> there is a real need/usecase for them. I know the board file has these
>>> reserved but board file could be updated as you liked. With DT we need
>>> to maintain backward compatibility. So I would rather do it when there
>>> is an actual need for it.
>>
>> If we do not reserve channels for memcpy then you will have no support for
>> memcpy on these boards. Not sure if we use memcpy in any of our drivers in
>> daVinci, so it might be just fine to not have DMA memcpy support at all.
>
> Not that I know of. No driver uses DMA memcpy
>
>> But how about using edma1's reserved channels as memcpy (19-23, 30-31)? I
>
> I think this is much more reasonable.
>
>> don't know which channels the DSP would use on these boards, so it is never
>> going to be safe from that point.
>
> Yeah, and thats why I think its better to add it as and when there is a
> real need for it. At least at that point we are sure of the usecase.
OK, I'll disable the memcpy for now.
>>> In future, if/when we gain QDMA support, the QDMA channels could be used
>>> for memcopy.
>>
>> Well, in short there is no way to get the qDMA working in a different way
>> either. qDMA channel is in essence using 'normal' eDMA channel. This means
>> that we still need to reserve the eDMA channel to be used for memcpy, but
>> instead of SW triggering it (as we do it right now), we would need to use the
>> channel as qDMA and set things up accordingly. I don't really see the benefit
>> for qDMA mode to be honest.
>
> I guess the only advantage is that they will not clash with peripheral
> mode usage. But even then, some sort of reservation is needed. So I
> guess QDMA is no better than the EDMA reserved channels?
It will clash with the peripheral mode use since it needs to take one of the
eDMA channels. qDMA mode is basically differs from the mode we are using by
how the channel is triggered. Currently we start the memcpy with SW trigger.
In qDMA mode we can select a paRAM parameter which if it is updated will do
the triggering. It is useful if you have mostly constant memcpy parameters and
you only need to change one thing in there (reusing the paRAM slot), like you
change the dst address. In this case you just update the dst and the qDMA will
be triggered. I don't think we can take advantage of this feature via dmaengine.
--
P?ter
On Tuesday 15 December 2015 07:35 PM, Peter Ujfalusi wrote:
> On 12/15/2015 03:48 PM, Sekhar Nori wrote:
>>>> In future, if/when we gain QDMA support, the QDMA channels could be used
>>>> for memcopy.
>>>
>>> Well, in short there is no way to get the qDMA working in a different way
>>> either. qDMA channel is in essence using 'normal' eDMA channel. This means
>>> that we still need to reserve the eDMA channel to be used for memcpy, but
>>> instead of SW triggering it (as we do it right now), we would need to use the
>>> channel as qDMA and set things up accordingly. I don't really see the benefit
>>> for qDMA mode to be honest.
>>
>> I guess the only advantage is that they will not clash with peripheral
>> mode usage. But even then, some sort of reservation is needed. So I
>> guess QDMA is no better than the EDMA reserved channels?
>
> It will clash with the peripheral mode use since it needs to take one of the
> eDMA channels. qDMA mode is basically differs from the mode we are using by
> how the channel is triggered. Currently we start the memcpy with SW trigger.
Alright, so I was missing this detail. Thanks for clarifying it on IRC.
The EDMA specification makes it look like 8 additional QDMA channels can
be used over 32 DMA channels, but in reality they are not additional
channels since TCC is only valid between 0-31.
So, I agree. QDMA does not buy us any parallel transfers.
Thanks,
Sekhar