This patchset add the support for Device Tree source for Samsung ARTIK5 module[1]
based on Exynos3250 SoC and development board[2]. The ARTIK5 module includes
the follwoing devices:
- Application Processor (Samsung Exynos3250)
- WiFi/BT Combo chip
- PMIC (Samsung S2MPS14)
- eMMC (4GB)
- DRAM LPDDR3 (512MB)
- Connectors pin (60 Pins x 3 set)
Also, this patchset add the ARTIK5 development board[2] dts file which includes
the ARTIK5 module[1] and have the devices such as sound codec, sd card port,
ethernet port, uart port and so on.
[1] https://www.artik.io/hardware/artik-5
[2] http://www.digikey.com/product-detail/en/SIP-KITNXB001/1510-1316-ND/5825102
Chanwoo Choi (6):
clk: samsung: exynos3250: Add MMC2 clock
ARM: dts: Add MSHC2 dt node for Exynos3250 SoC
ARM: dts: Add exynos3250-artik5 dtsi file for ARTIK5 module
ARM: dts: Add thermal zone and cpufreq node for exynos3250-artik5 module
ARM: dts: Add rtc and adc dt node for exynos3250-artik5 module
ARM: dts: Add PPMU node for exynos3250-artik5 module
Jaehoon Chung (2):
ARM: dts: Add MSHC0 dt node for eMMC device for exynos3250-artik5 module
ARM: dts: Add MSHC2 dt node for SD card for exynos3250-artik5-devel board
Pankaj Dubey (2):
clk: samsung: exynos3250: Add UART2 clock
ARM: dts: Add UART2 dt node for Exynos3250 SoC
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos3250-artik5-devel.dts | 42 +++
arch/arm/boot/dts/exynos3250-artik5.dtsi | 372 ++++++++++++++++++++++++++
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 42 +++
arch/arm/boot/dts/exynos3250.dtsi | 25 ++
drivers/clk/samsung/clk-exynos3250.c | 15 ++
include/dt-bindings/clock/exynos3250.h | 11 +-
7 files changed, 507 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/exynos3250-artik5-devel.dts
create mode 100644 arch/arm/boot/dts/exynos3250-artik5.dtsi
--
1.9.1
This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC.
Cc: Sylwester Nawrocki <[email protected]>
Cc: Tomasz Figa <[email protected]>
Signed-off-by: Chanwoo Choi <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
drivers/clk/samsung/clk-exynos3250.c | 9 +++++++++
include/dt-bindings/clock/exynos3250.h | 7 ++++++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index bc60e399d1bc..16575ee874cb 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -302,6 +302,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
/* SRC_FSYS */
MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
+ MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
@@ -390,6 +391,11 @@ static struct samsung_div_clock div_clks[] __initdata = {
CLK_SET_RATE_PARENT, 0),
DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
+ /* DIV_FSYS2 */
+ DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
+ CLK_SET_RATE_PARENT, 0),
+ DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+
/* DIV_PERIL0 */
DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
@@ -540,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
+ GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
+ GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
@@ -635,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
+ GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index ddb874130d86..c796ff02ceeb 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -80,6 +80,7 @@
#define CLK_MOUT_APLL 59
#define CLK_MOUT_ACLK_266_SUB 60
#define CLK_MOUT_UART2 61
+#define CLK_MOUT_MMC2 62
/* Dividers */
#define CLK_DIV_GPL 64
@@ -129,6 +130,8 @@
#define CLK_DIV_HPM 108
#define CLK_DIV_COPY 109
#define CLK_DIV_UART2 110
+#define CLK_DIV_MMC2_PRE 111
+#define CLK_DIV_MMC2 112
/* Gates */
#define CLK_ASYNC_G3D 128
@@ -226,6 +229,7 @@
#define CLK_BLOCK_CAM 220
#define CLK_SMIES 221
#define CLK_UART2 222
+#define CLK_SDMMC2 223
/* Special clocks */
#define CLK_SCLK_JPEG 224
@@ -253,12 +257,13 @@
#define CLK_SCLK_UART1 246
#define CLK_SCLK_UART0 247
#define CLK_SCLK_UART2 248
+#define CLK_SCLK_MMC2 249
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
-#define CLK_NR_CLKS 249
+#define CLK_NR_CLKS 250
/*
* CMU DMC
--
1.9.1
This patch adds the support for Device Tree source for Samsung ARTIK5 module[1]
based on Exynos3250 SoC. The ARTIK5 module includes the follwoing devices:
- Application Processor (Samsung Exynos3250)
- WiFi/BT Combo chip (Broadcom4354)
- PMIC (Samsung S2MPS14)
- eMMC (4GB)
- DRAM LPDDR3 (512MB)
- Connectors pin (60 Pins x 3 set)
Also, this patch adds the ARTIK5 development board[2] dts file which includes
the ARTIK5 module[1] and have the devices such as sound codec, sd card port,
ethernet port, uart port and so on.
[1] https://www.artik.io/hardware/artik-5
[2] http://www.digikey.com/product-search/en?FV=ffecca14
Signed-off-by: Chanwoo Choi <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/exynos3250-artik5-devel.dts | 26 +++
arch/arm/boot/dts/exynos3250-artik5.dtsi | 282 ++++++++++++++++++++++++++
3 files changed, 309 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos3250-artik5-devel.dts
create mode 100644 arch/arm/boot/dts/exynos3250-artik5.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a4a6d70e8b26..f2de160828e8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -108,6 +108,7 @@ dtb-$(CONFIG_ARCH_DIGICOLOR) += \
dtb-$(CONFIG_ARCH_EFM32) += \
efm32gg-dk3750.dtb
dtb-$(CONFIG_ARCH_EXYNOS3) += \
+ exynos3250-artik5-devel.dtb \
exynos3250-monk.dtb \
exynos3250-rinato.dtb
dtb-$(CONFIG_ARCH_EXYNOS4) += \
diff --git a/arch/arm/boot/dts/exynos3250-artik5-devel.dts b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
new file mode 100644
index 000000000000..d17c28969118
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
@@ -0,0 +1,26 @@
+/*
+ * Samsung's Exynos3250 based ARTIK5 development board device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Device tree source file for Samsung's ARTIK5 development board
+ * which is based on Samsung Exynos3250 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "exynos3250-artik5.dtsi"
+
+/ {
+ model = "Samsung ARTIK5 development board";
+ compatible = "samsung,artik5-devel", "samsung,artik5",
+ "samsung,exynos3250", "samsung,exynos3";
+};
+
+&serial_2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
new file mode 100644
index 000000000000..97d0087efb9f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -0,0 +1,282 @@
+/*
+ * Samsung's Exynos3250 based ARTIK5 module device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Device tree source file for Samsung's ARTIK5 module which is based on
+ * Samsung Exynos3250 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "exynos3250.dtsi"
+#include <dt-bindings/clock/samsung,s2mps11.h>
+
+/ {
+ compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3";
+
+
+ chosen {
+ linux,stdout = &serial_2;
+ };
+
+ memory {
+ reg = <0x40000000 0x1ff00000>;
+ };
+
+ firmware@0205F000 {
+ compatible = "samsung,secure-firmware";
+ reg = <0x0205F000 0x1000>;
+ };
+};
+
+&i2c_0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ samsung,i2c-sda-delay = <100>;
+ samsung,i2c-slave-addr = <0x10>;
+ samsung,i2c-max-bus-freq = <100000>;
+ status = "okay";
+
+ s2mps14_pmic@66 {
+ compatible = "samsung,s2mps14-pmic";
+ interrupt-parent = <&gpx3>;
+ interrupts = <5 0>;
+ reg = <0x66>;
+ wakeup;
+
+ s2mps14_osc: clocks {
+ compatible = "samsung,s2mps14-clk";
+ #clock-cells = <1>;
+ clock-output-names = "s2mps14_ap", "unused",
+ "s2mps14_bt";
+ };
+
+ regulators {
+ ldo1_reg: LDO1 {
+ /* VDD_ALIVE15x */
+ regulator-name = "VLDO1_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ /* VDDQM176 ~ VDDQM185 */
+ regulator-name = "VLDO2_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ /*
+ * VDD1_E106 ~ VDD1_E111
+ * DVDD_RTC_AP, DVDD_MMC2_AP
+ */
+ regulator-name = "VLDO3_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ /* AVDD_PLL1120 ~ AVDD_PLL11201 */
+ regulator-name = "VLDO4_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo5_reg: LDO5 {
+ /* VDDI_PLL_ISO141 ~ VDDI_PLL_ISO142 */
+ regulator-name = "VLDO5_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ /* VDD_USB, VDD10_HSIC */
+ regulator-name = "VLDO6_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ ldo7_reg: LDO7 {
+ /*
+ * VDD18P, AVDD18_TS, AVDD18_HSIC, AVDD_PLL2,
+ * AVDD_ADC, AVDD_ABB_0, M4S_VDD18
+ */
+ regulator-name = "VLDO7_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo8_reg: LDO8 {
+ /* AVDD33_UOTG */
+ regulator-name = "VLDO8_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ };
+
+ ldo9_reg: LDO9 {
+ /* VDDQ_E86 ~ VDDQ_E105*/
+ regulator-name = "VLDO_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-name = "VLDO10_1.0V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ ldo11_reg: LDO11 {
+ /* VDD_MMC */
+ regulator-name = "VLDO11_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo12_reg: LDO12 {
+ /* VDD72 ~ VDD73 */
+ regulator-name = "VLDO12_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-always-on;
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-name = "VLDO13_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-name = "VLDO14_2.7V";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-name = "VLDO_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-name = "VLDO16_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-name = "VLDO17_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo18_reg: LDO18 {
+ /* DVDD_MMC2_AP */
+ regulator-name = "VLDO18_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo19_reg: LDO19 {
+ regulator-name = "VLDO19_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo20_reg: LDO20 {
+ regulator-name = "VLDO20_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo21_reg: LDO21 {
+ regulator-name = "VLDO21_1.25V";
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ };
+
+ ldo22_reg: LDO22 {
+ regulator-name = "VLDO22_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo23_reg: LDO23 {
+ /* Xi2c3_SDA/SCL, Xi2c7_SDA/SCL, WLAN_SDIO */
+ regulator-name = "VLDO23_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo24_reg: LDO24 {
+ regulator-name = "VLDO24_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo25_reg: LDO25 {
+ regulator-name = "VLDO25_3.0V";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ buck1_reg: BUCK1 {
+ /* VDD_MIF */
+ regulator-name = "VBUCK1_1.0V";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ buck2_reg: BUCK2 {
+ /* VDD_CPU */
+ regulator-name = "VBUCK2_1.2V";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ buck3_reg: BUCK3 {
+ /* VDD_G3D */
+ regulator-name = "VBUCK3_1.0V";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "VBUCK4_1.95V";
+ regulator-min-microvolt = <1950000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "VBUCK5_1.35V";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&xusbxti {
+ clock-frequency = <24000000>;
+};
--
1.9.1
From: Jaehoon Chung <[email protected]>
This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos3250
SoC. MSHC is an interface between the system and the eMMC device.
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
Signed-off-by: Chanwoo Choi <[email protected]>
---
arch/arm/boot/dts/exynos3250-artik5.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
index 97d0087efb9f..75b291c10cdc 100644
--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -277,6 +277,25 @@
};
};
+&mshc_0 {
+ num-slots = <1>;
+ broken-cd;
+ non-removable;
+ cap-mmc-highspeed;
+ desc-num = <4>;
+ card-detect-delay = <200>;
+ vmmc-supply = <&ldo11_reg>;
+ clock-frequency = <100000000>;
+ clock-freq-min-max = <400000 100000000>;
+ samsung,dw-mshc-ciu-div = <1>;
+ samsung,dw-mshc-sdr-timing = <0 1>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+ bus-width = <8>;
+ status = "okay";
+};
+
&xusbxti {
clock-frequency = <24000000>;
};
--
1.9.1
This patch adds PPMU (Platform Performance Monitoring Unit) Device Tree node
for Exynos3250 based ARTIK5 module. The PPMU node is used to get the
utilization of DMC0/DMC1/LEFTBUS/RIGHTBUS Block.
Signed-off-by: Chanwoo Choi <[email protected]>
---
arch/arm/boot/dts/exynos3250-artik5.dtsi | 36 ++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
index 673883fda480..995356708b7d 100644
--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -321,6 +321,42 @@
status = "okay";
};
+&ppmu_dmc0 {
+ status = "okay";
+ events {
+ ppmu_dmc0_3: ppmu-event3-dmc0 {
+ event-name = "ppmu-event3-dmc0";
+ };
+ };
+};
+
+&ppmu_dmc1 {
+ status = "okay";
+ events {
+ ppmu_dmc1_3: ppmu-event3-dmc1 {
+ event-name = "ppmu-event3-dmc1";
+ };
+ };
+};
+
+&ppmu_leftbus {
+ status = "okay";
+ events {
+ ppmu_leftbus_3: ppmu-event3-leftbus {
+ event-name = "ppmu-event3-leftbus";
+ };
+ };
+};
+
+&ppmu_rightbus {
+ status = "okay";
+ events {
+ ppmu_rightbus_3: ppmu-event3-rightbus {
+ event-name = "ppmu-event3-rightbus";
+ };
+ };
+};
+
&tmu {
status = "okay";
};
--
1.9.1
From: Jaehoon Chung <[email protected]>
This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos3250
SoC. MSHC is an interface between the system and the eMMC device.
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
Signed-off-by: Chanwoo Choi <[email protected]>
---
arch/arm/boot/dts/exynos3250-artik5.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
index 97d0087efb9f..75b291c10cdc 100644
--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -277,6 +277,25 @@
};
};
+&mshc_0 {
+ num-slots = <1>;
+ broken-cd;
+ non-removable;
+ cap-mmc-highspeed;
+ desc-num = <4>;
+ card-detect-delay = <200>;
+ vmmc-supply = <&ldo11_reg>;
+ clock-frequency = <100000000>;
+ clock-freq-min-max = <400000 100000000>;
+ samsung,dw-mshc-ciu-div = <1>;
+ samsung,dw-mshc-sdr-timing = <0 1>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+ bus-width = <8>;
+ status = "okay";
+};
+
&xusbxti {
clock-frequency = <24000000>;
};
--
1.9.1
From: Pankaj Dubey <[email protected]>
This patch add the uart2 devicetree node for Exynos3250 SoC.
Cc: Kukjin Kim <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Pankaj Dubey <[email protected]>
Signed-off-by: Chanwoo Choi <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 7 +++++++
arch/arm/boot/dts/exynos3250.dtsi | 12 ++++++++++++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index ecf79386e891..54c587f27265 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -158,6 +158,13 @@
samsung,pin-drv = <0>;
};
+ uart2_data: uart2-data {
+ samsung,pins = "gpa1-0", "gpa1-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <0>;
+ };
+
i2c3_bus: i2c3-bus {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <3>;
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 18e3deffbf48..076677384d20 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -42,6 +42,7 @@
i2c7 = &i2c_7;
serial0 = &serial_0;
serial1 = &serial_1;
+ serial2 = &serial_2;
};
cpus {
@@ -465,6 +466,17 @@
status = "disabled";
};
+ serial_2: serial@13820000 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x13820000 0x100>;
+ interrupts = <0 111 0>;
+ clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
+ clock-names = "uart", "clk_uart_baud0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_data>;
+ status = "disabled";
+ };
+
i2c_0: i2c@13860000 {
#address-cells = <1>;
#size-cells = <0>;
--
1.9.1
This patch adds the RTC (Real Time Clock) and ADC (Analog Digital Converter)
Device Tree node for exynos3250-artik5 module. The RTC is used for wakeup
source and the ADC is used to read the analog data such as battery temperature.
ADC need to connect the some H/W device such as battery. So, this patch just
adds the default setting (clock, regulator).
Signed-off-by: Chanwoo Choi <[email protected]>
---
arch/arm/boot/dts/exynos3250-artik5.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
index 877e4827df83..673883fda480 100644
--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -48,6 +48,12 @@
};
};
+&adc {
+ vdd-supply = <&ldo7_reg>;
+ assigned-clocks = <&cmu CLK_SCLK_TSADC>;
+ assigned-clock-rates = <6000000>;
+};
+
&cpu0 {
cpu0-supply = <&buck2_reg>;
};
@@ -319,6 +325,12 @@
status = "okay";
};
+&rtc {
+ clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>;
+ clock-names = "rtc", "rtc_src";
+ status = "okay";
+};
+
&xusbxti {
clock-frequency = <24000000>;
};
--
1.9.1
From: Jaehoon Chung <[email protected]>
This patch adds MSHC (Mobile Storage Host Controller) dt node for
Exynos3250 SoC. MSHC is an interface between the system and the SD card
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Chanwoo Choi <[email protected]>
---
arch/arm/boot/dts/exynos3250-artik5-devel.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-artik5-devel.dts b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
index d17c28969118..a371baf8536d 100644
--- a/arch/arm/boot/dts/exynos3250-artik5-devel.dts
+++ b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
@@ -21,6 +21,22 @@
"samsung,exynos3250", "samsung,exynos3";
};
+&mshc_2 {
+ num-slots = <1>;
+ cap-sd-highspeed;
+ disable-wp;
+ card-detect-delay = <200>;
+ clock-frequency = <100000000>;
+ clock-freq-min-max = <400000 100000000>;
+ samsung,dw-mshc-ciu-div = <1>;
+ samsung,dw-mshc-sdr-timing = <0 1>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
+ bus-width = <4>;
+ status = "okay";
+};
+
&serial_2 {
status = "okay";
};
--
1.9.1
This patch adds the MSHC2 (Mobile Storage Host Controller) Device Tree node for
Exynos3250 SoC.
Cc: Kukjin Kim <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Chanwoo Choi <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 35 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos3250.dtsi | 13 ++++++++++++
2 files changed, 48 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 54c587f27265..40ea7de44933 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -490,6 +490,41 @@
samsung,pin-drv = <3>;
};
+ sd2_clk: sd2-clk {
+ samsung,pins = "gpk2-0";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cmd: sd2-cmd {
+ samsung,pins = "gpk2-1";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <0>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_cd: sd2-cd {
+ samsung,pins = "gpk2-2";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus1: sd2-bus-width1 {
+ samsung,pins = "gpk2-3";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
+ sd2_bus4: sd2-bus-width4 {
+ samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <3>;
+ };
+
cam_port_b_io: cam-port-b-io {
samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
"gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 076677384d20..2fead5730879 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -30,6 +30,7 @@
pinctrl1 = &pinctrl_1;
mshc0 = &mshc_0;
mshc1 = &mshc_1;
+ mshc2 = &mshc_2;
spi0 = &spi_0;
spi1 = &spi_1;
i2c0 = &i2c_0;
@@ -371,6 +372,18 @@
status = "disabled";
};
+ mshc_2: mshc@12530000 {
+ compatible = "samsung,exynos5250-dw-mshc";
+ reg = <0x12530000 0x1000>;
+ interrupts = <0 144 0>;
+ clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
exynos_usbphy: exynos-usbphy@125B0000 {
compatible = "samsung,exynos3250-usb2-phy";
reg = <0x125B0000 0x100>;
--
1.9.1
From: Pankaj Dubey <[email protected]>
This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC.
Cc: Sylwester Nawrocki <[email protected]>
Cc: Tomasz Figa <[email protected]>
Signed-off-by: Pankaj Dubey <[email protected]>
Signed-off-by: Chanwoo Choi <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
drivers/clk/samsung/clk-exynos3250.c | 6 ++++++
include/dt-bindings/clock/exynos3250.h | 6 +++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index fdd41b17a24f..bc60e399d1bc 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -306,6 +306,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
/* SRC_PERIL0 */
+ MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4),
MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4),
MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4),
@@ -390,6 +391,7 @@ static struct samsung_div_clock div_clks[] __initdata = {
DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
/* DIV_PERIL0 */
+ DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
@@ -552,6 +554,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre",
GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0),
+
+ GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
+ GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0),
GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
@@ -649,6 +654,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0),
GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0),
GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0),
+ GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0),
GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0),
GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0),
};
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index 63d01c15d2b3..ddb874130d86 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -79,6 +79,7 @@
#define CLK_MOUT_CORE 58
#define CLK_MOUT_APLL 59
#define CLK_MOUT_ACLK_266_SUB 60
+#define CLK_MOUT_UART2 61
/* Dividers */
#define CLK_DIV_GPL 64
@@ -127,6 +128,7 @@
#define CLK_DIV_CORE 107
#define CLK_DIV_HPM 108
#define CLK_DIV_COPY 109
+#define CLK_DIV_UART2 110
/* Gates */
#define CLK_ASYNC_G3D 128
@@ -223,6 +225,7 @@
#define CLK_BLOCK_MFC 219
#define CLK_BLOCK_CAM 220
#define CLK_SMIES 221
+#define CLK_UART2 222
/* Special clocks */
#define CLK_SCLK_JPEG 224
@@ -249,12 +252,13 @@
#define CLK_SCLK_SPI0 245
#define CLK_SCLK_UART1 246
#define CLK_SCLK_UART0 247
+#define CLK_SCLK_UART2 248
/*
* Total number of clocks of main CMU.
* NOTE: Must be equal to last clock ID increased by one.
*/
-#define CLK_NR_CLKS 248
+#define CLK_NR_CLKS 249
/*
* CMU DMC
--
1.9.1
This patch enables the CPU frequency scaling for exynos3250-artik5 module
and adds the thernal zones with cpu cooling device to prevent the overheat
temperature.
Signed-off-by: Chanwoo Choi <[email protected]>
---
arch/arm/boot/dts/exynos3250-artik5.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
index 75b291c10cdc..877e4827df83 100644
--- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
+++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
@@ -31,6 +31,25 @@
compatible = "samsung,secure-firmware";
reg = <0x0205F000 0x1000>;
};
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ cooling-maps {
+ map0 {
+ /* Corresponds to 500MHz */
+ cooling-device = <&cpu0 5 5>;
+ };
+ map1 {
+ /* Corresponds to 200MHz */
+ cooling-device = <&cpu0 8 8>;
+ };
+ };
+ };
+ };
+};
+
+&cpu0 {
+ cpu0-supply = <&buck2_reg>;
};
&i2c_0 {
@@ -296,6 +315,10 @@
status = "okay";
};
+&tmu {
+ status = "okay";
+};
+
&xusbxti {
clock-frequency = <24000000>;
};
--
1.9.1
Dear all,
It is my mistake. Please ignore only this patch.
This patch is duplicate with patch[1].
[1] [PATCH 06/10] ARM: dts: Add MSHC0 dt node for eMMC device for exynos3250-artik5 module
Best Regards,
Chanwoo Choi
On 2016년 03월 14일 11:04, Chanwoo Choi wrote:
> From: Jaehoon Chung <[email protected]>
>
> This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos3250
> SoC. MSHC is an interface between the system and the eMMC device.
>
> Signed-off-by: Jaehoon Chung <[email protected]>
> Signed-off-by: Andi Shyti <[email protected]>
> Signed-off-by: Chanwoo Choi <[email protected]>
> ---
> arch/arm/boot/dts/exynos3250-artik5.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
> index 97d0087efb9f..75b291c10cdc 100644
> --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
> +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
> @@ -277,6 +277,25 @@
> };
> };
>
> +&mshc_0 {
> + num-slots = <1>;
> + broken-cd;
> + non-removable;
> + cap-mmc-highspeed;
> + desc-num = <4>;
> + card-detect-delay = <200>;
> + vmmc-supply = <&ldo11_reg>;
> + clock-frequency = <100000000>;
> + clock-freq-min-max = <400000 100000000>;
> + samsung,dw-mshc-ciu-div = <1>;
> + samsung,dw-mshc-sdr-timing = <0 1>;
> + samsung,dw-mshc-ddr-timing = <1 2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
> + bus-width = <8>;
> + status = "okay";
> +};
> +
> &xusbxti {
> clock-frequency = <24000000>;
> };
>
On 14.03.2016 11:04, Chanwoo Choi wrote:
> This patch adds the MSHC2 (Mobile Storage Host Controller) Device Tree node for
> Exynos3250 SoC.
>
> Cc: Kukjin Kim <[email protected]>
> Cc: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Chanwoo Choi <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> ---
> arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 35 +++++++++++++++++++++++++++++++
> arch/arm/boot/dts/exynos3250.dtsi | 13 ++++++++++++
> 2 files changed, 48 insertions(+)
After looking at your other patch ("ARM: dts: Add initial pin
configuration for exynos3250-rinato") I have doubts. The Monk will be
affected.
Here you are configuring all the gpk2 GPIOS for EMMC2 mode. Then on
Rinato you are setting it back to default non-used state. However the
Monk board will remain with this new configuration... so you would have
to add initial-state also for Monk.
But how about doing opposite? Configure here the pins to unused state
and enable them only for Artik board?
What do you think?
Best regards,
Krzysztof
On 14.03.2016 11:04, Chanwoo Choi wrote:
> This patch adds the support for Device Tree source for Samsung ARTIK5 module[1]
> based on Exynos3250 SoC. The ARTIK5 module includes the follwoing devices:
> - Application Processor (Samsung Exynos3250)
> - WiFi/BT Combo chip (Broadcom4354)
> - PMIC (Samsung S2MPS14)
> - eMMC (4GB)
> - DRAM LPDDR3 (512MB)
> - Connectors pin (60 Pins x 3 set)
>
> Also, this patch adds the ARTIK5 development board[2] dts file which includes
> the ARTIK5 module[1] and have the devices such as sound codec, sd card port,
> ethernet port, uart port and so on.
>
> [1] https://www.artik.io/hardware/artik-5
> [2] http://www.digikey.com/product-search/en?FV=ffecca14
>
> Signed-off-by: Chanwoo Choi <[email protected]>
> Signed-off-by: Andi Shyti <[email protected]>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/exynos3250-artik5-devel.dts | 26 +++
> arch/arm/boot/dts/exynos3250-artik5.dtsi | 282 ++++++++++++++++++++++++++
Plus changes in
Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt.
> 3 files changed, 309 insertions(+)
> create mode 100644 arch/arm/boot/dts/exynos3250-artik5-devel.dts
> create mode 100644 arch/arm/boot/dts/exynos3250-artik5.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index a4a6d70e8b26..f2de160828e8 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -108,6 +108,7 @@ dtb-$(CONFIG_ARCH_DIGICOLOR) += \
> dtb-$(CONFIG_ARCH_EFM32) += \
> efm32gg-dk3750.dtb
> dtb-$(CONFIG_ARCH_EXYNOS3) += \
> + exynos3250-artik5-devel.dtb \
> exynos3250-monk.dtb \
> exynos3250-rinato.dtb
> dtb-$(CONFIG_ARCH_EXYNOS4) += \
> diff --git a/arch/arm/boot/dts/exynos3250-artik5-devel.dts b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
> new file mode 100644
> index 000000000000..d17c28969118
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
> @@ -0,0 +1,26 @@
> +/*
> + * Samsung's Exynos3250 based ARTIK5 development board device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * Device tree source file for Samsung's ARTIK5 development board
> + * which is based on Samsung Exynos3250 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/dts-v1/;
> +#include "exynos3250-artik5.dtsi"
> +
> +/ {
> + model = "Samsung ARTIK5 development board";
> + compatible = "samsung,artik5-devel", "samsung,artik5",
> + "samsung,exynos3250", "samsung,exynos3";
> +};
> +
> +&serial_2 {
> + status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
> new file mode 100644
> index 000000000000..97d0087efb9f
> --- /dev/null
> +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
> @@ -0,0 +1,282 @@
> +/*
> + * Samsung's Exynos3250 based ARTIK5 module device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com
> + *
> + * Device tree source file for Samsung's ARTIK5 module which is based on
> + * Samsung Exynos3250 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "exynos3250.dtsi"
> +#include <dt-bindings/clock/samsung,s2mps11.h>
> +
> +/ {
> + compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3";
> +
> +
Leave only one blank line.
> + chosen {
> + linux,stdout = &serial_2;
'stdout-path' should be used (linux,stdout is deprecated).
> + };
> +
> + memory {
> + reg = <0x40000000 0x1ff00000>;
Just one space after '='.
> + };
> +
> + firmware@0205F000 {
> + compatible = "samsung,secure-firmware";
> + reg = <0x0205F000 0x1000>;
Let stick to one convention of letter case for hex numbers. Lower-case
maybe, so 0205f000?
> + };
> +};
> +
> +&i2c_0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + samsung,i2c-sda-delay = <100>;
> + samsung,i2c-slave-addr = <0x10>;
> + samsung,i2c-max-bus-freq = <100000>;
> + status = "okay";
> +
> + s2mps14_pmic@66 {
> + compatible = "samsung,s2mps14-pmic";
> + interrupt-parent = <&gpx3>;
> + interrupts = <5 0>;
IRQ_TYPE_NONE
> + reg = <0x66>;
> + wakeup;
This is not valid property and is ignored. Probably you meant
'wakeup_source' (which would still be ignored by sec-core driver by the
way... fixing this is waiting on Exynos mainline todo list :) ).
Best regards,
Krzysztof
On 14.03.2016 11:04, Chanwoo Choi wrote:
> From: Jaehoon Chung <[email protected]>
>
> This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos3250
> SoC. MSHC is an interface between the system and the eMMC device.
>
> Signed-off-by: Jaehoon Chung <[email protected]>
> Signed-off-by: Andi Shyti <[email protected]>
> Signed-off-by: Chanwoo Choi <[email protected]>
> ---
> arch/arm/boot/dts/exynos3250-artik5.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
> index 97d0087efb9f..75b291c10cdc 100644
> --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
> +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
> @@ -277,6 +277,25 @@
> };
> };
>
> +&mshc_0 {
> + num-slots = <1>;
> + broken-cd;
> + non-removable;
Broken or non-removable, not both.
> + cap-mmc-highspeed;
> + desc-num = <4>;
> + card-detect-delay = <200>;
> + vmmc-supply = <&ldo11_reg>;
Isn't this vqmmc-supply?
BTW, both MMC0 regulators (ldo11, ldo12) are marked as always-on. Why
they cannot be controlled by XMMC0CDN (just like on Rinato)?
What is the benefit of making this patch separate from "Add
exynos3250-artik5 dtsi file for ARTIK5 module"? Does the board boot
properly without this patch?
Best regards,
Krzysztof
> + clock-frequency = <100000000>;
> + clock-freq-min-max = <400000 100000000>;
> + samsung,dw-mshc-ciu-div = <1>;
> + samsung,dw-mshc-sdr-timing = <0 1>;
> + samsung,dw-mshc-ddr-timing = <1 2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
> + bus-width = <8>;
> + status = "okay";
> +};
> +
> &xusbxti {
> clock-frequency = <24000000>;
> };
>
Hi Krzysztof,
On 2016년 03월 14일 15:42, Krzysztof Kozlowski wrote:
> On 14.03.2016 11:04, Chanwoo Choi wrote:
>> This patch adds the support for Device Tree source for Samsung ARTIK5 module[1]
>> based on Exynos3250 SoC. The ARTIK5 module includes the follwoing devices:
>> - Application Processor (Samsung Exynos3250)
>> - WiFi/BT Combo chip (Broadcom4354)
>> - PMIC (Samsung S2MPS14)
>> - eMMC (4GB)
>> - DRAM LPDDR3 (512MB)
>> - Connectors pin (60 Pins x 3 set)
>>
>> Also, this patch adds the ARTIK5 development board[2] dts file which includes
>> the ARTIK5 module[1] and have the devices such as sound codec, sd card port,
>> ethernet port, uart port and so on.
>>
>> [1] https://www.artik.io/hardware/artik-5
>> [2] http://www.digikey.com/product-search/en?FV=ffecca14
>>
>> Signed-off-by: Chanwoo Choi <[email protected]>
>> Signed-off-by: Andi Shyti <[email protected]>
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/exynos3250-artik5-devel.dts | 26 +++
>> arch/arm/boot/dts/exynos3250-artik5.dtsi | 282 ++++++++++++++++++++++++++
>
> Plus changes in
> Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt.
>
>> 3 files changed, 309 insertions(+)
>> create mode 100644 arch/arm/boot/dts/exynos3250-artik5-devel.dts
>> create mode 100644 arch/arm/boot/dts/exynos3250-artik5.dtsi
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index a4a6d70e8b26..f2de160828e8 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -108,6 +108,7 @@ dtb-$(CONFIG_ARCH_DIGICOLOR) += \
>> dtb-$(CONFIG_ARCH_EFM32) += \
>> efm32gg-dk3750.dtb
>> dtb-$(CONFIG_ARCH_EXYNOS3) += \
>> + exynos3250-artik5-devel.dtb \
>> exynos3250-monk.dtb \
>> exynos3250-rinato.dtb
>> dtb-$(CONFIG_ARCH_EXYNOS4) += \
>> diff --git a/arch/arm/boot/dts/exynos3250-artik5-devel.dts b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>> new file mode 100644
>> index 000000000000..d17c28969118
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>> @@ -0,0 +1,26 @@
>> +/*
>> + * Samsung's Exynos3250 based ARTIK5 development board device tree source
>> + *
>> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * Device tree source file for Samsung's ARTIK5 development board
>> + * which is based on Samsung Exynos3250 SoC.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +/dts-v1/;
>> +#include "exynos3250-artik5.dtsi"
>> +
>> +/ {
>> + model = "Samsung ARTIK5 development board";
>> + compatible = "samsung,artik5-devel", "samsung,artik5",
>> + "samsung,exynos3250", "samsung,exynos3";
>> +};
>> +
>> +&serial_2 {
>> + status = "okay";
>> +};
>> diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> new file mode 100644
>> index 000000000000..97d0087efb9f
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> @@ -0,0 +1,282 @@
>> +/*
>> + * Samsung's Exynos3250 based ARTIK5 module device tree source
>> + *
>> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com
>> + *
>> + * Device tree source file for Samsung's ARTIK5 module which is based on
>> + * Samsung Exynos3250 SoC.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include "exynos3250.dtsi"
>> +#include <dt-bindings/clock/samsung,s2mps11.h>
>> +
>> +/ {
>> + compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3";
>> +
>> +
>
> Leave only one blank line.
>
>> + chosen {
>> + linux,stdout = &serial_2;
>
> 'stdout-path' should be used (linux,stdout is deprecated).
>
>> + };
>> +
>> + memory {
>> + reg = <0x40000000 0x1ff00000>;
>
> Just one space after '='.
>
>> + };
>> +
>> + firmware@0205F000 {
>> + compatible = "samsung,secure-firmware";
>> + reg = <0x0205F000 0x1000>;
>
> Let stick to one convention of letter case for hex numbers. Lower-case
> maybe, so 0205f000?
I'm sorry about coding style issue.
I'll fix them you mentioned.
>
>> + };
>> +};
>> +
>> +&i2c_0 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + samsung,i2c-sda-delay = <100>;
>> + samsung,i2c-slave-addr = <0x10>;
>> + samsung,i2c-max-bus-freq = <100000>;
>> + status = "okay";
>> +
>> + s2mps14_pmic@66 {
>> + compatible = "samsung,s2mps14-pmic";
>> + interrupt-parent = <&gpx3>;
>> + interrupts = <5 0>;
>
> IRQ_TYPE_NONE
OK, I'll modify it.
>
>> + reg = <0x66>;
>> + wakeup;
>
> This is not valid property and is ignored. Probably you meant
> 'wakeup_source' (which would still be ignored by sec-core driver by the
> way... fixing this is waiting on Exynos mainline todo list :) ).
OK. I'll remove it.
Thanks for your review.
Best Regards,
Chanwoo Choi
On 14.03.2016 11:04, Chanwoo Choi wrote:
> This patch enables the CPU frequency scaling for exynos3250-artik5 module
> and adds the thernal zones with cpu cooling device to prevent the overheat
> temperature.
>
> Signed-off-by: Chanwoo Choi <[email protected]>
> ---
> arch/arm/boot/dts/exynos3250-artik5.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
The patch looks good but just squash it with 5/10 unless there is some
benefit by splitting the features for many patches. The benefit would be
for example submitting the work partially, in steps, following principle
release-early-release-often... but this is not the case. You have
everything ready and tested.
BR,
Krzysztof
>
> diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
> index 75b291c10cdc..877e4827df83 100644
> --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
> +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
> @@ -31,6 +31,25 @@
> compatible = "samsung,secure-firmware";
> reg = <0x0205F000 0x1000>;
> };
> +
> + thermal-zones {
> + cpu_thermal: cpu-thermal {
> + cooling-maps {
> + map0 {
> + /* Corresponds to 500MHz */
> + cooling-device = <&cpu0 5 5>;
> + };
> + map1 {
> + /* Corresponds to 200MHz */
> + cooling-device = <&cpu0 8 8>;
> + };
> + };
> + };
> + };
> +};
> +
> +&cpu0 {
> + cpu0-supply = <&buck2_reg>;
> };
>
> &i2c_0 {
> @@ -296,6 +315,10 @@
> status = "okay";
> };
>
> +&tmu {
> + status = "okay";
> +};
> +
> &xusbxti {
> clock-frequency = <24000000>;
> };
>
On 14.03.2016 11:04, Chanwoo Choi wrote:
> This patch adds the RTC (Real Time Clock) and ADC (Analog Digital Converter)
> Device Tree node for exynos3250-artik5 module. The RTC is used for wakeup
> source and the ADC is used to read the analog data such as battery temperature.
>
> ADC need to connect the some H/W device such as battery. So, this patch just
> adds the default setting (clock, regulator).
>
> Signed-off-by: Chanwoo Choi <[email protected]>
> ---
> arch/arm/boot/dts/exynos3250-artik5.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
> index 877e4827df83..673883fda480 100644
> --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
> +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
> @@ -48,6 +48,12 @@
> };
> };
>
> +&adc {
> + vdd-supply = <&ldo7_reg>;
> + assigned-clocks = <&cmu CLK_SCLK_TSADC>;
> + assigned-clock-rates = <6000000>;
> +};
No thermistors, status non-okay. What is provided here?
> +
> &cpu0 {
> cpu0-supply = <&buck2_reg>;
> };
> @@ -319,6 +325,12 @@
> status = "okay";
> };
>
> +&rtc {
> + clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>;
> + clock-names = "rtc", "rtc_src";
> + status = "okay";
> +};
Same comment as for previous patch - just squash it. Splitting brings no
benefits and makes it more difficult to see bigger picture.
BR,
Krzysztof
> +
> &xusbxti {
> clock-frequency = <24000000>;
> };
>
On 2016년 03월 14일 16:06, Krzysztof Kozlowski wrote:
> On 14.03.2016 11:04, Chanwoo Choi wrote:
>> This patch enables the CPU frequency scaling for exynos3250-artik5 module
>> and adds the thernal zones with cpu cooling device to prevent the overheat
>> temperature.
>>
>> Signed-off-by: Chanwoo Choi <[email protected]>
>> ---
>> arch/arm/boot/dts/exynos3250-artik5.dtsi | 23 +++++++++++++++++++++++
>> 1 file changed, 23 insertions(+)
>
> The patch looks good but just squash it with 5/10 unless there is some
> benefit by splitting the features for many patches. The benefit would be
> for example submitting the work partially, in steps, following principle
> release-early-release-often... but this is not the case. You have
> everything ready and tested.
OK. I'll merge this patch with 5/10 patch.
Best Regards,
Chanwoo Choi
>
> BR,
> Krzysztof
>
>>
>> diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> index 75b291c10cdc..877e4827df83 100644
>> --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> @@ -31,6 +31,25 @@
>> compatible = "samsung,secure-firmware";
>> reg = <0x0205F000 0x1000>;
>> };
>> +
>> + thermal-zones {
>> + cpu_thermal: cpu-thermal {
>> + cooling-maps {
>> + map0 {
>> + /* Corresponds to 500MHz */
>> + cooling-device = <&cpu0 5 5>;
>> + };
>> + map1 {
>> + /* Corresponds to 200MHz */
>> + cooling-device = <&cpu0 8 8>;
>> + };
>> + };
>> + };
>> + };
>> +};
>> +
>> +&cpu0 {
>> + cpu0-supply = <&buck2_reg>;
>> };
>>
>> &i2c_0 {
>> @@ -296,6 +315,10 @@
>> status = "okay";
>> };
>>
>> +&tmu {
>> + status = "okay";
>> +};
>> +
>> &xusbxti {
>> clock-frequency = <24000000>;
>> };
>>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to [email protected]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
>
On 2016년 03월 14일 16:12, Krzysztof Kozlowski wrote:
> On 14.03.2016 11:04, Chanwoo Choi wrote:
>> This patch adds the RTC (Real Time Clock) and ADC (Analog Digital Converter)
>> Device Tree node for exynos3250-artik5 module. The RTC is used for wakeup
>> source and the ADC is used to read the analog data such as battery temperature.
>>
>> ADC need to connect the some H/W device such as battery. So, this patch just
>> adds the default setting (clock, regulator).
>>
>> Signed-off-by: Chanwoo Choi <[email protected]>
>> ---
>> arch/arm/boot/dts/exynos3250-artik5.dtsi | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> index 877e4827df83..673883fda480 100644
>> --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> @@ -48,6 +48,12 @@
>> };
>> };
>>
>> +&adc {
>> + vdd-supply = <&ldo7_reg>;
>> + assigned-clocks = <&cmu CLK_SCLK_TSADC>;
>> + assigned-clock-rates = <6000000>;
>> +};
>
> No thermistors, status non-okay. What is provided here?
The some device are not connected for ADC line on artik5-eval board.
This dt node just initialize the basic setting (clock,regulator) ADC of exynos3250 SoC.
(I'll change the board name from artik5-devel to artik5-eval on v2 patchset)
The vdd-supply for ADC is already fixed on artik5 module.
>
>> +
>> &cpu0 {
>> cpu0-supply = <&buck2_reg>;
>> };
>> @@ -319,6 +325,12 @@
>> status = "okay";
>> };
>>
>> +&rtc {
>> + clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>;
>> + clock-names = "rtc", "rtc_src";
>> + status = "okay";
>> +};
>
> Same comment as for previous patch - just squash it. Splitting brings no
> benefits and makes it more difficult to see bigger picture.
Okay. I'll merge it with 5/10 patch.
Best Regards,
Chanwoo Choi
On 2016년 03월 14일 15:57, Chanwoo Choi wrote:
> Hi Krzysztof,
>
> On 2016년 03월 14일 15:42, Krzysztof Kozlowski wrote:
>> On 14.03.2016 11:04, Chanwoo Choi wrote:
>>> This patch adds the support for Device Tree source for Samsung ARTIK5 module[1]
>>> based on Exynos3250 SoC. The ARTIK5 module includes the follwoing devices:
>>> - Application Processor (Samsung Exynos3250)
>>> - WiFi/BT Combo chip (Broadcom4354)
>>> - PMIC (Samsung S2MPS14)
>>> - eMMC (4GB)
>>> - DRAM LPDDR3 (512MB)
>>> - Connectors pin (60 Pins x 3 set)
>>>
>>> Also, this patch adds the ARTIK5 development board[2] dts file which includes
>>> the ARTIK5 module[1] and have the devices such as sound codec, sd card port,
>>> ethernet port, uart port and so on.
>>>
>>> [1] https://www.artik.io/hardware/artik-5
>>> [2] http://www.digikey.com/product-search/en?FV=ffecca14
>>>
>>> Signed-off-by: Chanwoo Choi <[email protected]>
>>> Signed-off-by: Andi Shyti <[email protected]>
>>> ---
>>> arch/arm/boot/dts/Makefile | 1 +
>>> arch/arm/boot/dts/exynos3250-artik5-devel.dts | 26 +++
>>> arch/arm/boot/dts/exynos3250-artik5.dtsi | 282 ++++++++++++++++++++++++++
>>
>> Plus changes in
>> Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt.
OK.
Also, I'll change the board name from 'artik5-devel' to 'artik5-eval'.
[snip]
Best Regards,
Chanwoo Choi
On 2016년 03월 14일 15:57, Krzysztof Kozlowski wrote:
> On 14.03.2016 11:04, Chanwoo Choi wrote:
>> From: Jaehoon Chung <[email protected]>
>>
>> This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos3250
>> SoC. MSHC is an interface between the system and the eMMC device.
>>
>> Signed-off-by: Jaehoon Chung <[email protected]>
>> Signed-off-by: Andi Shyti <[email protected]>
>> Signed-off-by: Chanwoo Choi <[email protected]>
>> ---
>> arch/arm/boot/dts/exynos3250-artik5.dtsi | 19 +++++++++++++++++++
>> 1 file changed, 19 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> index 97d0087efb9f..75b291c10cdc 100644
>> --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> @@ -277,6 +277,25 @@
>> };
>> };
>>
>> +&mshc_0 {
>> + num-slots = <1>;
>> + broken-cd;
>> + non-removable;
>
> Broken or non-removable, not both.
I'll remove the 'broken-cd' property.
>
>> + cap-mmc-highspeed;
>> + desc-num = <4>;
>> + card-detect-delay = <200>;
>> + vmmc-supply = <&ldo11_reg>;
>
> Isn't this vqmmc-supply?
I'll fix it as following by using ldo12_reg:
vmmc-supply = <&ldo12_reg>;
>
> BTW, both MMC0 regulators (ldo11, ldo12) are marked as always-on. Why
> they cannot be controlled by XMMC0CDN (just like on Rinato)?
I'll fix it like rinato board to handle the ldo11/ldo12 as following:
gpk0-2 is XMMC0CDN pin.
ldo11_reg: LDO11 {
- /* VDD_MMC */
+ /* VDD74 ~ VDD75 */
regulator-name = "VLDO11_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-always-on;
+ samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
};
ldo12_reg: LDO12 {
@@ -177,7 +178,7 @@
regulator-name = "VLDO12_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
- regulator-always-on;
+ samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>;
};
>
> What is the benefit of making this patch separate from "Add
> exynos3250-artik5 dtsi file for ARTIK5 module"? Does the board boot
> properly without this patch?
OK. I'll merge it with 5/10 patch.
Best Regards,
Chanwoo Choi
[snip]
On 2016년 03월 14일 15:22, Krzysztof Kozlowski wrote:
> On 14.03.2016 11:04, Chanwoo Choi wrote:
>> This patch adds the MSHC2 (Mobile Storage Host Controller) Device Tree node for
>> Exynos3250 SoC.
>>
>> Cc: Kukjin Kim <[email protected]>
>> Cc: Krzysztof Kozlowski <[email protected]>
>> Signed-off-by: Chanwoo Choi <[email protected]>
>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>> ---
>> arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 35 +++++++++++++++++++++++++++++++
>> arch/arm/boot/dts/exynos3250.dtsi | 13 ++++++++++++
>> 2 files changed, 48 insertions(+)
>
>
> After looking at your other patch ("ARM: dts: Add initial pin
> configuration for exynos3250-rinato") I have doubts. The Monk will be
> affected.
You're right. On monk board, this line may be not stable.
>
> Here you are configuring all the gpk2 GPIOS for EMMC2 mode. Then on
> Rinato you are setting it back to default non-used state. However the
> Monk board will remain with this new configuration... so you would have
> to add initial-state also for Monk.
OK. I'll do it.
>
> But how about doing opposite? Configure here the pins to unused state
> and enable them only for Artik board?
>
> What do you think?
I think that gpk2-[0~6] pins are fixed for MMC2 device.
So, it is good to add the pin setting for gpk2-[0~6] to exynos3250-pinctrl.dtsi.
If mmc2 device is not used like rinato and monk board,
we should add the initial setting as NC (not connected) pin state
as other patch (ARM: dts: Add initial pin configuration for exynos3250-rinato).
Best Regards,
Chanwoo Choi
On 14.03.2016 11:04, Chanwoo Choi wrote:
> From: Jaehoon Chung <[email protected]>
>
> This patch adds MSHC (Mobile Storage Host Controller) dt node for
> Exynos3250 SoC. MSHC is an interface between the system and the SD card
>
> Signed-off-by: Jaehoon Chung <[email protected]>
> Signed-off-by: Chanwoo Choi <[email protected]>
> ---
> arch/arm/boot/dts/exynos3250-artik5-devel.dts | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos3250-artik5-devel.dts b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
> index d17c28969118..a371baf8536d 100644
> --- a/arch/arm/boot/dts/exynos3250-artik5-devel.dts
> +++ b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
> @@ -21,6 +21,22 @@
> "samsung,exynos3250", "samsung,exynos3";
> };
>
> +&mshc_2 {
> + num-slots = <1>;
> + cap-sd-highspeed;
> + disable-wp;
> + card-detect-delay = <200>;
> + clock-frequency = <100000000>;
> + clock-freq-min-max = <400000 100000000>;
> + samsung,dw-mshc-ciu-div = <1>;
> + samsung,dw-mshc-sdr-timing = <0 1>;
> + samsung,dw-mshc-ddr-timing = <1 2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
> + bus-width = <4>;
> + status = "okay";
vqmmc-supply = ldo3?
Best regards,
Krzysztof
> +};
> +
> &serial_2 {
> status = "okay";
> };
>
On 14.03.2016 11:04, Chanwoo Choi wrote:
> This patch adds PPMU (Platform Performance Monitoring Unit) Device Tree node
> for Exynos3250 based ARTIK5 module. The PPMU node is used to get the
> utilization of DMC0/DMC1/LEFTBUS/RIGHTBUS Block.
>
> Signed-off-by: Chanwoo Choi <[email protected]>
> ---
> arch/arm/boot/dts/exynos3250-artik5.dtsi | 36 ++++++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
What is the status with your devfreq patches? Instead of this one, there
should be just:
#include "exynos4412-ppmu-common.dtsi"
(squashed into patch 5/10).
Best regards,
Krzysztof
> diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
> index 673883fda480..995356708b7d 100644
> --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
> +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
> @@ -321,6 +321,42 @@
> status = "okay";
> };
>
> +&ppmu_dmc0 {
> + status = "okay";
> + events {
> + ppmu_dmc0_3: ppmu-event3-dmc0 {
> + event-name = "ppmu-event3-dmc0";
> + };
> + };
> +};
> +
> +&ppmu_dmc1 {
> + status = "okay";
> + events {
> + ppmu_dmc1_3: ppmu-event3-dmc1 {
> + event-name = "ppmu-event3-dmc1";
> + };
> + };
> +};
> +
> +&ppmu_leftbus {
> + status = "okay";
> + events {
> + ppmu_leftbus_3: ppmu-event3-leftbus {
> + event-name = "ppmu-event3-leftbus";
> + };
> + };
> +};
> +
> +&ppmu_rightbus {
> + status = "okay";
> + events {
> + ppmu_rightbus_3: ppmu-event3-rightbus {
> + event-name = "ppmu-event3-rightbus";
> + };
> + };
> +};
> +
> &tmu {
> status = "okay";
> };
>
On 2016년 03월 14일 17:34, Krzysztof Kozlowski wrote:
> On 14.03.2016 11:04, Chanwoo Choi wrote:
>> This patch adds PPMU (Platform Performance Monitoring Unit) Device Tree node
>> for Exynos3250 based ARTIK5 module. The PPMU node is used to get the
>> utilization of DMC0/DMC1/LEFTBUS/RIGHTBUS Block.
>>
>> Signed-off-by: Chanwoo Choi <[email protected]>
>> ---
>> arch/arm/boot/dts/exynos3250-artik5.dtsi | 36 ++++++++++++++++++++++++++++++++
>> 1 file changed, 36 insertions(+)
>
> What is the status with your devfreq patches? Instead of this one, there
> should be just:
> #include "exynos4412-ppmu-common.dtsi"
> (squashed into patch 5/10).
I'm not working the devfreq patches(exynos-bus). Sorry for delay.
I'll again implement them by using DEVFREQ_NOTIFIER style according to (Myungjoo Ham's comment)
I drop the this patch on v2 patchset. After implementing the exynos-bus driver,
I'll send it.
Best Regards,
Chanwoo Choi
>
> Best regards,
> Krzysztof
>
>> diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> index 673883fda480..995356708b7d 100644
>> --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
>> @@ -321,6 +321,42 @@
>> status = "okay";
>> };
>>
>> +&ppmu_dmc0 {
>> + status = "okay";
>> + events {
>> + ppmu_dmc0_3: ppmu-event3-dmc0 {
>> + event-name = "ppmu-event3-dmc0";
>> + };
>> + };
>> +};
>> +
>> +&ppmu_dmc1 {
>> + status = "okay";
>> + events {
>> + ppmu_dmc1_3: ppmu-event3-dmc1 {
>> + event-name = "ppmu-event3-dmc1";
>> + };
>> + };
>> +};
>> +
>> +&ppmu_leftbus {
>> + status = "okay";
>> + events {
>> + ppmu_leftbus_3: ppmu-event3-leftbus {
>> + event-name = "ppmu-event3-leftbus";
>> + };
>> + };
>> +};
>> +
>> +&ppmu_rightbus {
>> + status = "okay";
>> + events {
>> + ppmu_rightbus_3: ppmu-event3-rightbus {
>> + event-name = "ppmu-event3-rightbus";
>> + };
>> + };
>> +};
>> +
>> &tmu {
>> status = "okay";
>> };
>>
>
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>
>
On 2016년 03월 14일 17:31, Krzysztof Kozlowski wrote:
> On 14.03.2016 11:04, Chanwoo Choi wrote:
>> From: Jaehoon Chung <[email protected]>
>>
>> This patch adds MSHC (Mobile Storage Host Controller) dt node for
>> Exynos3250 SoC. MSHC is an interface between the system and the SD card
>>
>> Signed-off-by: Jaehoon Chung <[email protected]>
>> Signed-off-by: Chanwoo Choi <[email protected]>
>> ---
>> arch/arm/boot/dts/exynos3250-artik5-devel.dts | 16 ++++++++++++++++
>> 1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos3250-artik5-devel.dts b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>> index d17c28969118..a371baf8536d 100644
>> --- a/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>> +++ b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>> @@ -21,6 +21,22 @@
>> "samsung,exynos3250", "samsung,exynos3";
>> };
>>
>> +&mshc_2 {
>> + num-slots = <1>;
>> + cap-sd-highspeed;
>> + disable-wp;
>> + card-detect-delay = <200>;
>> + clock-frequency = <100000000>;
>> + clock-freq-min-max = <400000 100000000>;
>> + samsung,dw-mshc-ciu-div = <1>;
>> + samsung,dw-mshc-sdr-timing = <0 1>;
>> + samsung,dw-mshc-ddr-timing = <1 2>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
>> + bus-width = <4>;
>> + status = "okay";
>
> vqmmc-supply = ldo3?
ldo3 is always on state because ldo3 is used for various IP in exynos3250.
I think that we had better to remain always on state for ldo3.
Best Regards,
Chanwoo Choi
On 14.03.2016 17:48, Chanwoo Choi wrote:
> On 2016년 03월 14일 17:31, Krzysztof Kozlowski wrote:
>> On 14.03.2016 11:04, Chanwoo Choi wrote:
>>> From: Jaehoon Chung <[email protected]>
>>>
>>> This patch adds MSHC (Mobile Storage Host Controller) dt node for
>>> Exynos3250 SoC. MSHC is an interface between the system and the SD card
>>>
>>> Signed-off-by: Jaehoon Chung <[email protected]>
>>> Signed-off-by: Chanwoo Choi <[email protected]>
>>> ---
>>> arch/arm/boot/dts/exynos3250-artik5-devel.dts | 16 ++++++++++++++++
>>> 1 file changed, 16 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/exynos3250-artik5-devel.dts b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>> index d17c28969118..a371baf8536d 100644
>>> --- a/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>> +++ b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>> @@ -21,6 +21,22 @@
>>> "samsung,exynos3250", "samsung,exynos3";
>>> };
>>>
>>> +&mshc_2 {
>>> + num-slots = <1>;
>>> + cap-sd-highspeed;
>>> + disable-wp;
>>> + card-detect-delay = <200>;
>>> + clock-frequency = <100000000>;
>>> + clock-freq-min-max = <400000 100000000>;
>>> + samsung,dw-mshc-ciu-div = <1>;
>>> + samsung,dw-mshc-sdr-timing = <0 1>;
>>> + samsung,dw-mshc-ddr-timing = <1 2>;
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
>>> + bus-width = <4>;
>>> + status = "okay";
>>
>> vqmmc-supply = ldo3?
>
> ldo3 is always on state because ldo3 is used for various IP in exynos3250.
> I think that we had better to remain always on state for ldo3.
Yes, I wasn't thinking about toggling ldo3 but about taking the
regulator here to model the dependencies between components.
Best regards,
Krzysztof
On 14.03.2016 17:28, Chanwoo Choi wrote:
> On 2016년 03월 14일 15:22, Krzysztof Kozlowski wrote:
>> On 14.03.2016 11:04, Chanwoo Choi wrote:
>>> This patch adds the MSHC2 (Mobile Storage Host Controller) Device Tree node for
>>> Exynos3250 SoC.
>>>
>>> Cc: Kukjin Kim <[email protected]>
>>> Cc: Krzysztof Kozlowski <[email protected]>
>>> Signed-off-by: Chanwoo Choi <[email protected]>
>>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>>> ---
>>> arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 35 +++++++++++++++++++++++++++++++
>>> arch/arm/boot/dts/exynos3250.dtsi | 13 ++++++++++++
>>> 2 files changed, 48 insertions(+)
>>
>>
>> After looking at your other patch ("ARM: dts: Add initial pin
>> configuration for exynos3250-rinato") I have doubts. The Monk will be
>> affected.
>
> You're right. On monk board, this line may be not stable.
>
>>
>> Here you are configuring all the gpk2 GPIOS for EMMC2 mode. Then on
>> Rinato you are setting it back to default non-used state. However the
>> Monk board will remain with this new configuration... so you would have
>> to add initial-state also for Monk.
>
> OK. I'll do it.
>
>>
>> But how about doing opposite? Configure here the pins to unused state
>> and enable them only for Artik board?
>>
>> What do you think?
>
> I think that gpk2-[0~6] pins are fixed for MMC2 device.
> So, it is good to add the pin setting for gpk2-[0~6] to exynos3250-pinctrl.dtsi.
>
> If mmc2 device is not used like rinato and monk board,
> we should add the initial setting as NC (not connected) pin state
> as other patch (ARM: dts: Add initial pin configuration for exynos3250-rinato).
Okay, fine to me.
BR,
Krzysztof
On 14.03.2016 17:15, Chanwoo Choi wrote:
> On 2016년 03월 14일 15:57, Krzysztof Kozlowski wrote:
>> On 14.03.2016 11:04, Chanwoo Choi wrote:
>>> From: Jaehoon Chung <[email protected]>
>>>
>>> This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos3250
>>> SoC. MSHC is an interface between the system and the eMMC device.
>>>
>>> Signed-off-by: Jaehoon Chung <[email protected]>
>>> Signed-off-by: Andi Shyti <[email protected]>
>>> Signed-off-by: Chanwoo Choi <[email protected]>
>>> ---
>>> arch/arm/boot/dts/exynos3250-artik5.dtsi | 19 +++++++++++++++++++
>>> 1 file changed, 19 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi
>>> index 97d0087efb9f..75b291c10cdc 100644
>>> --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi
>>> +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi
>>> @@ -277,6 +277,25 @@
>>> };
>>> };
>>>
>>> +&mshc_0 {
>>> + num-slots = <1>;
>>> + broken-cd;
>>> + non-removable;
>>
>> Broken or non-removable, not both.
>
> I'll remove the 'broken-cd' property.
>
>>
>>> + cap-mmc-highspeed;
>>> + desc-num = <4>;
>>> + card-detect-delay = <200>;
>>> + vmmc-supply = <&ldo11_reg>;
>>
>> Isn't this vqmmc-supply?
>
> I'll fix it as following by using ldo12_reg:
> vmmc-supply = <&ldo12_reg>;
Sure, looks good.
>
>>
>> BTW, both MMC0 regulators (ldo11, ldo12) are marked as always-on. Why
>> they cannot be controlled by XMMC0CDN (just like on Rinato)?
>
> I'll fix it like rinato board to handle the ldo11/ldo12 as following:
> gpk0-2 is XMMC0CDN pin.
Great! Thanks,
Krzysztof
On 2016년 03월 14일 18:44, Krzysztof Kozlowski wrote:
> On 14.03.2016 17:48, Chanwoo Choi wrote:
>> On 2016년 03월 14일 17:31, Krzysztof Kozlowski wrote:
>>> On 14.03.2016 11:04, Chanwoo Choi wrote:
>>>> From: Jaehoon Chung <[email protected]>
>>>>
>>>> This patch adds MSHC (Mobile Storage Host Controller) dt node for
>>>> Exynos3250 SoC. MSHC is an interface between the system and the SD card
>>>>
>>>> Signed-off-by: Jaehoon Chung <[email protected]>
>>>> Signed-off-by: Chanwoo Choi <[email protected]>
>>>> ---
>>>> arch/arm/boot/dts/exynos3250-artik5-devel.dts | 16 ++++++++++++++++
>>>> 1 file changed, 16 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/exynos3250-artik5-devel.dts b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>> index d17c28969118..a371baf8536d 100644
>>>> --- a/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>> +++ b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>> @@ -21,6 +21,22 @@
>>>> "samsung,exynos3250", "samsung,exynos3";
>>>> };
>>>>
>>>> +&mshc_2 {
>>>> + num-slots = <1>;
>>>> + cap-sd-highspeed;
>>>> + disable-wp;
>>>> + card-detect-delay = <200>;
>>>> + clock-frequency = <100000000>;
>>>> + clock-freq-min-max = <400000 100000000>;
>>>> + samsung,dw-mshc-ciu-div = <1>;
>>>> + samsung,dw-mshc-sdr-timing = <0 1>;
>>>> + samsung,dw-mshc-ddr-timing = <1 2>;
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
>>>> + bus-width = <4>;
>>>> + status = "okay";
>>>
>>> vqmmc-supply = ldo3?
>>
>> ldo3 is always on state because ldo3 is used for various IP in exynos3250.
>> I think that we had better to remain always on state for ldo3.
>
> Yes, I wasn't thinking about toggling ldo3 but about taking the
> regulator here to model the dependencies between components.
Okay. I'll add it as following:
vmmc-supply = <&ldo18_reg>;
vqmmc-supply = <&ldo3>;
Best Regards,
Chanwoo Choi
On 14.03.2016 19:22, Chanwoo Choi wrote:
> On 2016년 03월 14일 18:44, Krzysztof Kozlowski wrote:
>> On 14.03.2016 17:48, Chanwoo Choi wrote:
>>> On 2016년 03월 14일 17:31, Krzysztof Kozlowski wrote:
>>>> On 14.03.2016 11:04, Chanwoo Choi wrote:
>>>>> From: Jaehoon Chung <[email protected]>
>>>>>
>>>>> This patch adds MSHC (Mobile Storage Host Controller) dt node for
>>>>> Exynos3250 SoC. MSHC is an interface between the system and the SD card
>>>>>
>>>>> Signed-off-by: Jaehoon Chung <[email protected]>
>>>>> Signed-off-by: Chanwoo Choi <[email protected]>
>>>>> ---
>>>>> arch/arm/boot/dts/exynos3250-artik5-devel.dts | 16 ++++++++++++++++
>>>>> 1 file changed, 16 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/exynos3250-artik5-devel.dts b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>>> index d17c28969118..a371baf8536d 100644
>>>>> --- a/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>>> +++ b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>>> @@ -21,6 +21,22 @@
>>>>> "samsung,exynos3250", "samsung,exynos3";
>>>>> };
>>>>>
>>>>> +&mshc_2 {
>>>>> + num-slots = <1>;
>>>>> + cap-sd-highspeed;
>>>>> + disable-wp;
>>>>> + card-detect-delay = <200>;
>>>>> + clock-frequency = <100000000>;
>>>>> + clock-freq-min-max = <400000 100000000>;
>>>>> + samsung,dw-mshc-ciu-div = <1>;
>>>>> + samsung,dw-mshc-sdr-timing = <0 1>;
>>>>> + samsung,dw-mshc-ddr-timing = <1 2>;
>>>>> + pinctrl-names = "default";
>>>>> + pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
>>>>> + bus-width = <4>;
>>>>> + status = "okay";
>>>>
>>>> vqmmc-supply = ldo3?
>>>
>>> ldo3 is always on state because ldo3 is used for various IP in exynos3250.
>>> I think that we had better to remain always on state for ldo3.
>>
>> Yes, I wasn't thinking about toggling ldo3 but about taking the
>> regulator here to model the dependencies between components.
>
> Okay. I'll add it as following:
>
> vmmc-supply = <&ldo18_reg>;
> vqmmc-supply = <&ldo3>;
ldo18 is not used by mshc2. At least my schematics show that LDO3 goes
to DVDD_MMC2 (on different board revision that would be ldo18 instead of
ldo3, but not both).
The card itself is powered by VDDFLASH_28/MAIN_BAT.
BR,
Krzysztof
On 03/15/2016 09:25 AM, Krzysztof Kozlowski wrote:
> On 14.03.2016 19:22, Chanwoo Choi wrote:
>> On 2016년 03월 14일 18:44, Krzysztof Kozlowski wrote:
>>> On 14.03.2016 17:48, Chanwoo Choi wrote:
>>>> On 2016년 03월 14일 17:31, Krzysztof Kozlowski wrote:
>>>>> On 14.03.2016 11:04, Chanwoo Choi wrote:
>>>>>> From: Jaehoon Chung <[email protected]>
>>>>>>
>>>>>> This patch adds MSHC (Mobile Storage Host Controller) dt node for
>>>>>> Exynos3250 SoC. MSHC is an interface between the system and the SD card
>>>>>>
>>>>>> Signed-off-by: Jaehoon Chung <[email protected]>
>>>>>> Signed-off-by: Chanwoo Choi <[email protected]>
>>>>>> ---
>>>>>> arch/arm/boot/dts/exynos3250-artik5-devel.dts | 16 ++++++++++++++++
>>>>>> 1 file changed, 16 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/exynos3250-artik5-devel.dts b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>>>> index d17c28969118..a371baf8536d 100644
>>>>>> --- a/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>>>> +++ b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>>>> @@ -21,6 +21,22 @@
>>>>>> "samsung,exynos3250", "samsung,exynos3";
>>>>>> };
>>>>>>
>>>>>> +&mshc_2 {
>>>>>> + num-slots = <1>;
>>>>>> + cap-sd-highspeed;
>>>>>> + disable-wp;
>>>>>> + card-detect-delay = <200>;
>>>>>> + clock-frequency = <100000000>;
>>>>>> + clock-freq-min-max = <400000 100000000>;
>>>>>> + samsung,dw-mshc-ciu-div = <1>;
>>>>>> + samsung,dw-mshc-sdr-timing = <0 1>;
>>>>>> + samsung,dw-mshc-ddr-timing = <1 2>;
>>>>>> + pinctrl-names = "default";
>>>>>> + pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
>>>>>> + bus-width = <4>;
>>>>>> + status = "okay";
>>>>>
>>>>> vqmmc-supply = ldo3?
>>>>
>>>> ldo3 is always on state because ldo3 is used for various IP in exynos3250.
>>>> I think that we had better to remain always on state for ldo3.
>>>
>>> Yes, I wasn't thinking about toggling ldo3 but about taking the
>>> regulator here to model the dependencies between components.
>>
>> Okay. I'll add it as following:
>>
>> vmmc-supply = <&ldo18_reg>;
>> vqmmc-supply = <&ldo3>;
>
> ldo18 is not used by mshc2. At least my schematics show that LDO3 goes
> to DVDD_MMC2 (on different board revision that would be ldo18 instead of
> ldo3, but not both).
It's confusing..but it seems that Krzysztof's opinion is right.
Best Regards,
Jaehoon Chung
>
> The card itself is powered by VDDFLASH_28/MAIN_BAT.
>
> BR,
> Krzysztof
>
>
On 2016년 03월 15일 09:56, Jaehoon Chung wrote:
> On 03/15/2016 09:25 AM, Krzysztof Kozlowski wrote:
>> On 14.03.2016 19:22, Chanwoo Choi wrote:
>>> On 2016년 03월 14일 18:44, Krzysztof Kozlowski wrote:
>>>> On 14.03.2016 17:48, Chanwoo Choi wrote:
>>>>> On 2016년 03월 14일 17:31, Krzysztof Kozlowski wrote:
>>>>>> On 14.03.2016 11:04, Chanwoo Choi wrote:
>>>>>>> From: Jaehoon Chung <[email protected]>
>>>>>>>
>>>>>>> This patch adds MSHC (Mobile Storage Host Controller) dt node for
>>>>>>> Exynos3250 SoC. MSHC is an interface between the system and the SD card
>>>>>>>
>>>>>>> Signed-off-by: Jaehoon Chung <[email protected]>
>>>>>>> Signed-off-by: Chanwoo Choi <[email protected]>
>>>>>>> ---
>>>>>>> arch/arm/boot/dts/exynos3250-artik5-devel.dts | 16 ++++++++++++++++
>>>>>>> 1 file changed, 16 insertions(+)
>>>>>>>
>>>>>>> diff --git a/arch/arm/boot/dts/exynos3250-artik5-devel.dts b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>>>>> index d17c28969118..a371baf8536d 100644
>>>>>>> --- a/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>>>>> +++ b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>>>>> @@ -21,6 +21,22 @@
>>>>>>> "samsung,exynos3250", "samsung,exynos3";
>>>>>>> };
>>>>>>>
>>>>>>> +&mshc_2 {
>>>>>>> + num-slots = <1>;
>>>>>>> + cap-sd-highspeed;
>>>>>>> + disable-wp;
>>>>>>> + card-detect-delay = <200>;
>>>>>>> + clock-frequency = <100000000>;
>>>>>>> + clock-freq-min-max = <400000 100000000>;
>>>>>>> + samsung,dw-mshc-ciu-div = <1>;
>>>>>>> + samsung,dw-mshc-sdr-timing = <0 1>;
>>>>>>> + samsung,dw-mshc-ddr-timing = <1 2>;
>>>>>>> + pinctrl-names = "default";
>>>>>>> + pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
>>>>>>> + bus-width = <4>;
>>>>>>> + status = "okay";
>>>>>>
>>>>>> vqmmc-supply = ldo3?
>>>>>
>>>>> ldo3 is always on state because ldo3 is used for various IP in exynos3250.
>>>>> I think that we had better to remain always on state for ldo3.
>>>>
>>>> Yes, I wasn't thinking about toggling ldo3 but about taking the
>>>> regulator here to model the dependencies between components.
>>>
>>> Okay. I'll add it as following:
>>>
>>> vmmc-supply = <&ldo18_reg>;
>>> vqmmc-supply = <&ldo3>;
>>
>> ldo18 is not used by mshc2. At least my schematics show that LDO3 goes
>> to DVDD_MMC2 (on different board revision that would be ldo18 instead of
>> ldo3, but not both).
ARTIK5 schema document VLDO18 and VLDO3 are connected to DVDD_MMC2_AP.
But, I'm not sure what is meaning. So, I'll drop the 'vmmc-supply'
>
> It's confusing..but it seems that Krzysztof's opinion is right.
>
> Best Regards,
> Jaehoon Chung
>
>>
>> The card itself is powered by VDDFLASH_28/MAIN_BAT.
You're right.
OK, I'll modify it with only vqmmc-supply = <&ldo3>;
Best Regards,
Chanwoo Choi
On 2016년 03월 15일 10:45, Chanwoo Choi wrote:
> On 2016년 03월 15일 09:56, Jaehoon Chung wrote:
>> On 03/15/2016 09:25 AM, Krzysztof Kozlowski wrote:
>>> On 14.03.2016 19:22, Chanwoo Choi wrote:
>>>> On 2016년 03월 14일 18:44, Krzysztof Kozlowski wrote:
>>>>> On 14.03.2016 17:48, Chanwoo Choi wrote:
>>>>>> On 2016년 03월 14일 17:31, Krzysztof Kozlowski wrote:
>>>>>>> On 14.03.2016 11:04, Chanwoo Choi wrote:
>>>>>>>> From: Jaehoon Chung <[email protected]>
>>>>>>>>
>>>>>>>> This patch adds MSHC (Mobile Storage Host Controller) dt node for
>>>>>>>> Exynos3250 SoC. MSHC is an interface between the system and the SD card
>>>>>>>>
>>>>>>>> Signed-off-by: Jaehoon Chung <[email protected]>
>>>>>>>> Signed-off-by: Chanwoo Choi <[email protected]>
>>>>>>>> ---
>>>>>>>> arch/arm/boot/dts/exynos3250-artik5-devel.dts | 16 ++++++++++++++++
>>>>>>>> 1 file changed, 16 insertions(+)
>>>>>>>>
>>>>>>>> diff --git a/arch/arm/boot/dts/exynos3250-artik5-devel.dts b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>>>>>> index d17c28969118..a371baf8536d 100644
>>>>>>>> --- a/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>>>>>> +++ b/arch/arm/boot/dts/exynos3250-artik5-devel.dts
>>>>>>>> @@ -21,6 +21,22 @@
>>>>>>>> "samsung,exynos3250", "samsung,exynos3";
>>>>>>>> };
>>>>>>>>
>>>>>>>> +&mshc_2 {
>>>>>>>> + num-slots = <1>;
>>>>>>>> + cap-sd-highspeed;
>>>>>>>> + disable-wp;
>>>>>>>> + card-detect-delay = <200>;
>>>>>>>> + clock-frequency = <100000000>;
>>>>>>>> + clock-freq-min-max = <400000 100000000>;
>>>>>>>> + samsung,dw-mshc-ciu-div = <1>;
>>>>>>>> + samsung,dw-mshc-sdr-timing = <0 1>;
>>>>>>>> + samsung,dw-mshc-ddr-timing = <1 2>;
>>>>>>>> + pinctrl-names = "default";
>>>>>>>> + pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
>>>>>>>> + bus-width = <4>;
>>>>>>>> + status = "okay";
>>>>>>>
>>>>>>> vqmmc-supply = ldo3?
>>>>>>
>>>>>> ldo3 is always on state because ldo3 is used for various IP in exynos3250.
>>>>>> I think that we had better to remain always on state for ldo3.
>>>>>
>>>>> Yes, I wasn't thinking about toggling ldo3 but about taking the
>>>>> regulator here to model the dependencies between components.
>>>>
>>>> Okay. I'll add it as following:
>>>>
>>>> vmmc-supply = <&ldo18_reg>;
>>>> vqmmc-supply = <&ldo3>;
>>>
>>> ldo18 is not used by mshc2. At least my schematics show that LDO3 goes
>>> to DVDD_MMC2 (on different board revision that would be ldo18 instead of
>>> ldo3, but not both).
>
> ARTIK5 schema document VLDO18 and VLDO3 are connected to DVDD_MMC2_AP.
> But, I'm not sure what is meaning. So, I'll drop the 'vmmc-supply'
VLDO18 is not connected to DVDD_MMC2_AP. It is NC state.
Sorry for confusion.
Best Regards,
Chanwoo Choi
[snip]