The TCUs (Translation Control Units) and TBUs (Translation Buffer
Units) are key components of the ARM MMU-500. Multiple TBUs are
connected to a single TCU over an interconnect. Each TBU contains
a TLB that caches page tables. The MMU-500 implements a TBU for each
connected master, and the TBU is designed, so that it is local to the
master.
The Qualcomm sdm845 platform has an implementation of the ARM SMMU-500,
that consists of a single TCU and multiple TBUs. Support for the TCU
is already present and this patchset is adds support for TBUs that
allow us to use some of the debug features to include more info when
a context fault occurs.
Each TBU requires some resources like power-domains, interconnects and
clocks to be described in DT. These resources will be being controlled
by the TBU driver when they in use.
Georgi Djakov (6):
dt-bindings: iommu: Add Translation Buffer Unit bindings
iommu/arm-smmu-qcom: Add support for TBUs
iommu/arm-smmu-qcom: Add Qualcomm TBU driver
iommu/arm-smmu: Allow using a threaded handler for context interrupts
iommu/arm-smmu-qcom: Use a custom context fault handler for sdm845
arm64: dts: qcom: sdm845: Add DT nodes for the TBUs
.../devicetree/bindings/iommu/arm,smmu.yaml | 13 +
.../bindings/iommu/qcom,qsmmuv500-tbu.yaml | 67 +++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 85 +++
drivers/iommu/Kconfig | 8 +
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 544 ++++++++++++++++++
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 4 +-
drivers/iommu/arm/arm-smmu/arm-smmu.c | 12 +-
drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +
8 files changed, 733 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
Add the device-tree nodes for the TBUs (translation buffer units) that
are present on the sdm845 platforms. The TBUs can be used debug the
kernel and provide additional information when a context faults occur.
Describe the all registers, clocks, interconnects and power-domain
resources that are needed for each of the TBUs.
Signed-off-by: Georgi Djakov <[email protected]>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 85 ++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 055ca80c0075..984770be5e08 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -5030,6 +5031,7 @@ pil-reloc@94c {
apps_smmu: iommu@15000000 {
compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x80000>;
+ ranges;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
@@ -5097,6 +5099,89 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ anoc_1_tbu: tbu@150c5000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150c5000 0x0 0x1000>;
+ reg-names = "base";
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC>;
+ qcom,stream-id-range = <0x0 0x400>;
+ };
+
+ anoc_2_tbu: tbu@150c9000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150c9000 0x0 0x1000>;
+ reg-names = "base";
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC>;
+ qcom,stream-id-range = <0x400 0x400>;
+ };
+
+ mnoc_hf_0_tbu: tbu@150cd000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150cd000 0x0 0x1000>;
+ reg-names = "base";
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>;
+ qcom,stream-id-range = <0x800 0x400>;
+ };
+
+ mnoc_hf_1_tbu: tbu@150d1000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150d1000 0x0 0x1000>;
+ reg-names = "base";
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>;
+ qcom,stream-id-range = <0xc00 0x400>;
+ };
+
+ mnoc_sf_0_tbu: tbu@150d5000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150d5000 0x0 0x1000>;
+ reg-names = "base";
+ interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY
+ &mmss_noc SLAVE_MNOC_SF_MEM_NOC QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC>;
+ qcom,stream-id-range = <0x1000 0x400>;
+ };
+
+ compute_dsp_tbu: tbu@150d9000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150d9000 0x0 0x1000>;
+ reg-names = "base";
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ qcom,stream-id-range = <0x1400 0x400>;
+ };
+
+ adsp_tbu: tbu@150dd000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150dd000 0x0 0x1000>;
+ reg-names = "base";
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC>;
+ qcom,stream-id-range = <0x1800 0x400>;
+ };
+
+ anoc_1_pcie_tbu: tbu@150e1000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x150e1000 0x0 0x1000>;
+ reg-names = "base";
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>;
+ qcom,stream-id-range = <0x1c00 0x400>;
+ };
};
lpasscc: clock-controller@17014000 {
The "apps_smmu" on the Qualcomm sdm845 platform is an implementation
of the ARM SMMU-500, that consists of a single TCU (Translation Control
Unit) and multiple TBUs (Translation Buffer Units). The TCU is already
being described in the ARM SMMU DT schema. Add also bindings for the
TBUs so that we can describe their properties.
In this DT schema, the TBUs are modelled as a child devices of the TCU
and each of them is described with it's own resources such as clocks,
power domains, interconnects etc.
Signed-off-by: Georgi Djakov <[email protected]>
---
.../devicetree/bindings/iommu/arm,smmu.yaml | 13 ++++
.../bindings/iommu/qcom,qsmmuv500-tbu.yaml | 67 +++++++++++++++++++
2 files changed, 80 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index cf29ab10501c..afc323b4bbc5 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -230,6 +230,19 @@ properties:
enabled for any given device.
$ref: /schemas/types.yaml#/definitions/phandle
+ '#address-cells':
+ const: 2
+
+ '#size-cells':
+ const: 2
+
+ ranges: true
+
+patternProperties:
+ "^tbu@[0-9a-f]+$":
+ $ref: qcom,qsmmuv500-tbu.yaml
+ description: The SMMU may include Translation Buffer Units (TBU) as subnodes
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
new file mode 100644
index 000000000000..4baba7397e90
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu/qcom,qsmmuv500-tbu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm TBU (Translation Buffer Unit)
+
+maintainers:
+ - Georgi Djakov <[email protected]>
+
+description:
+ TBU nodes represent Translation Buffer Units in an ARM SMMU. Each TBU node
+ should be a child node of the SMMU in the device tree.
+
+properties:
+ compatible:
+ enum:
+ - qcom,qsmmuv500-tbu
+
+ reg:
+ items:
+ - description: Address and size of the TBU's register space.
+
+ reg-names:
+ items:
+ - const: base
+
+ clocks:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ qcom,stream-id-range:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: Stream ID range (address and size) that is assigned by the TBU
+
+required:
+ - compatible
+ - reg
+ - interconnects
+ - qcom,stream-id-range
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/interconnect/qcom,sdm845.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+
+ tbu@150e1000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x150e1000 0x1000>;
+ reg-names = "base";
+ clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>;
+ interconnects = <&system_noc MASTER_GNOC_SNOC 0 &config_noc SLAVE_IMEM_CFG 0>;
+ qcom,stream-id-range = <0x1c00 0x400>;
+ };
+
+...
On 10/19/23 04:19, Georgi Djakov wrote:
> The "apps_smmu" on the Qualcomm sdm845 platform is an implementation
> of the ARM SMMU-500, that consists of a single TCU (Translation Control
> Unit) and multiple TBUs (Translation Buffer Units). The TCU is already
> being described in the ARM SMMU DT schema. Add also bindings for the
> TBUs so that we can describe their properties.
>
> In this DT schema, the TBUs are modelled as a child devices of the TCU
> and each of them is described with it's own resources such as clocks,
> power domains, interconnects etc.
>
> Signed-off-by: Georgi Djakov <[email protected]>
> ---
> .../devicetree/bindings/iommu/arm,smmu.yaml | 13 ++++
> .../bindings/iommu/qcom,qsmmuv500-tbu.yaml | 67 +++++++++++++++++++
> 2 files changed, 80 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index cf29ab10501c..afc323b4bbc5 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -230,6 +230,19 @@ properties:
> enabled for any given device.
> $ref: /schemas/types.yaml#/definitions/phandle
>
> + '#address-cells':
> + const: 2
> +
> + '#size-cells':
> + const: 2
> +
> + ranges: true
> +
> +patternProperties:
> + "^tbu@[0-9a-f]+$":
> + $ref: qcom,qsmmuv500-tbu.yaml
> + description: The SMMU may include Translation Buffer Units (TBU) as subnodes
> +
> required:
> - compatible
> - reg
> diff --git a/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
> new file mode 100644
> index 000000000000..4baba7397e90
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iommu/qcom,qsmmuv500-tbu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm TBU (Translation Buffer Unit)
> +
> +maintainers:
> + - Georgi Djakov <[email protected]>
> +
> +description:
> + TBU nodes represent Translation Buffer Units in an ARM SMMU. Each TBU node
> + should be a child node of the SMMU in the device tree.
description: refers to the hardware, so it should say what this IP
is, what it does and things like that
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,qsmmuv500-tbu
Should we expect this list to grow?
> +
> + reg:
> + items:
> + - description: Address and size of the TBU's register space.
> +
> + reg-names:
> + items:
> + - const: base
> +
> + clocks:
> + maxItems: 1
> +
> + interconnects:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + qcom,stream-id-range:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: Stream ID range (address and size) that is assigned by the TBU
I believe you need to size-limit this.
If it's only supposed to be a single tuple, perhaps it could be said
explicitly.
> +
> +required:
> + - compatible
> + - reg
> + - interconnects
> + - qcom,stream-id-range
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> + #include <dt-bindings/interconnect/qcom,sdm845.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> +
2 newlines seems excessive
> + tbu@150e1000 {
> + compatible = "qcom,qsmmuv500-tbu";
> + reg = <0x150e1000 0x1000>;
> + reg-names = "base";
> + clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
> + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>;
> + interconnects = <&system_noc MASTER_GNOC_SNOC 0 &config_noc SLAVE_IMEM_CFG 0>;
> + qcom,stream-id-range = <0x1c00 0x400>;
> + };
I think it would be beneficial if this tbu was a child of some smmu node
like it's intended to be.
Konrad
On Wed, Oct 18, 2023 at 07:19:18PM -0700, Georgi Djakov wrote:
> The "apps_smmu" on the Qualcomm sdm845 platform is an implementation
> of the ARM SMMU-500, that consists of a single TCU (Translation Control
> Unit) and multiple TBUs (Translation Buffer Units). The TCU is already
> being described in the ARM SMMU DT schema. Add also bindings for the
> TBUs so that we can describe their properties.
Arm SMMU-500 is an implementation, too. Is QCom's a modified
implementation or you are just the first to want to control TBU
resources?
You need to split this into what could be any SMMU-500 implementation
and what is truly QCom specific (i.e. modified). Unlike some licensed IP
that's a free-for-all on DT resources, Arm IP has public specs so we
don't have to guess.
> In this DT schema, the TBUs are modelled as a child devices of the TCU
> and each of them is described with it's own resources such as clocks,
> power domains, interconnects etc.
>
> Signed-off-by: Georgi Djakov <[email protected]>
> ---
> .../devicetree/bindings/iommu/arm,smmu.yaml | 13 ++++
> .../bindings/iommu/qcom,qsmmuv500-tbu.yaml | 67 +++++++++++++++++++
> 2 files changed, 80 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index cf29ab10501c..afc323b4bbc5 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -230,6 +230,19 @@ properties:
> enabled for any given device.
> $ref: /schemas/types.yaml#/definitions/phandle
>
> + '#address-cells':
> + const: 2
> +
> + '#size-cells':
> + const: 2
> +
> + ranges: true
> +
> +patternProperties:
> + "^tbu@[0-9a-f]+$":
> + $ref: qcom,qsmmuv500-tbu.yaml
Generic SMMU binding includes something QCom specific. That's not right.
> + description: The SMMU may include Translation Buffer Units (TBU) as subnodes
> +
> required:
> - compatible
> - reg
> diff --git a/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
> new file mode 100644
> index 000000000000..4baba7397e90
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iommu/qcom,qsmmuv500-tbu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm TBU (Translation Buffer Unit)
> +
> +maintainers:
> + - Georgi Djakov <[email protected]>
> +
> +description:
> + TBU nodes represent Translation Buffer Units in an ARM SMMU. Each TBU node
> + should be a child node of the SMMU in the device tree.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,qsmmuv500-tbu
> +
> + reg:
> + items:
> + - description: Address and size of the TBU's register space.
> +
> + reg-names:
> + items:
> + - const: base
> +
> + clocks:
> + maxItems: 1
> +
> + interconnects:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + qcom,stream-id-range:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: Stream ID range (address and size) that is assigned by the TBU
> +
> +required:
> + - compatible
> + - reg
> + - interconnects
> + - qcom,stream-id-range
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> + #include <dt-bindings/interconnect/qcom,sdm845.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> +
> + tbu@150e1000 {
> + compatible = "qcom,qsmmuv500-tbu";
> + reg = <0x150e1000 0x1000>;
> + reg-names = "base";
> + clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
> + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>;
> + interconnects = <&system_noc MASTER_GNOC_SNOC 0 &config_noc SLAVE_IMEM_CFG 0>;
> + qcom,stream-id-range = <0x1c00 0x400>;
> + };
> +
> +...
On 2023-10-24 19:42, Rob Herring wrote:
> On Wed, Oct 18, 2023 at 07:19:18PM -0700, Georgi Djakov wrote:
>> The "apps_smmu" on the Qualcomm sdm845 platform is an implementation
>> of the ARM SMMU-500, that consists of a single TCU (Translation Control
>> Unit) and multiple TBUs (Translation Buffer Units). The TCU is already
>> being described in the ARM SMMU DT schema. Add also bindings for the
>> TBUs so that we can describe their properties.
>
> Arm SMMU-500 is an implementation, too. Is QCom's a modified
> implementation or you are just the first to want to control TBU
> resources?
It's very very modified. The stock MMU-500 has very few
microarchitectural registers[1], they all live within the regular SMMU
address space, are all Secure-only by default, and don't do anything
like the shenanigans here.
That said, looking at patch #3, I don't really understand why we need
any of this stuff upstream... AFAICS it's doing an insane amount of work
to use complicated imp-def debug functionality to duplicate things that
the main driver can already do far more efficiently. Sure, in general it
seems like it could potentially be useful stuff for bringing up and
debugging a new driver, but the Linux SMMUv2 driver is mature and
frankly already closer to being obsolete than to being new...
[ digression since I can't be bothered to split this discussion by
replying separately to patch #3: ]
I mean, just looking at qsmmuv500_iova_to_phys(), you do realise that
that's going to be called potentially multiple times by iommu-dma for
*every* dma_sync and dma_unmap call and really wants to be fast, right?
This brings to mind all the work I did a couple of years back[2] because
strict TLB invalidation on unmap was considered too slow for certain
devices on QCom platforms by ChromeOS, yet what this achieves looks like
it could easily be up to an order of magnitude slower again :(
> You need to split this into what could be any SMMU-500 implementation
> and what is truly QCom specific (i.e. modified). Unlike some licensed IP
> that's a free-for-all on DT resources, Arm IP has public specs so we
> don't have to guess.
>
>> In this DT schema, the TBUs are modelled as a child devices of the TCU
>> and each of them is described with it's own resources such as clocks,
>> power domains, interconnects etc.
>>
>> Signed-off-by: Georgi Djakov <[email protected]>
>> ---
>> .../devicetree/bindings/iommu/arm,smmu.yaml | 13 ++++
>> .../bindings/iommu/qcom,qsmmuv500-tbu.yaml | 67 +++++++++++++++++++
>> 2 files changed, 80 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> index cf29ab10501c..afc323b4bbc5 100644
>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> @@ -230,6 +230,19 @@ properties:
>> enabled for any given device.
>> $ref: /schemas/types.yaml#/definitions/phandle
>>
>> + '#address-cells':
>> + const: 2
>> +
>> + '#size-cells':
>> + const: 2
>> +
>> + ranges: true
>> +
>> +patternProperties:
>> + "^tbu@[0-9a-f]+$":
>> + $ref: qcom,qsmmuv500-tbu.yaml
>
> Generic SMMU binding includes something QCom specific. That's not right.
>
>
>> + description: The SMMU may include Translation Buffer Units (TBU) as subnodes
>> +
>> required:
>> - compatible
>> - reg
>> diff --git a/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
>> new file mode 100644
>> index 000000000000..4baba7397e90
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
>> @@ -0,0 +1,67 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/iommu/qcom,qsmmuv500-tbu.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm TBU (Translation Buffer Unit)
>> +
>> +maintainers:
>> + - Georgi Djakov <[email protected]>
>> +
>> +description:
>> + TBU nodes represent Translation Buffer Units in an ARM SMMU. Each TBU node
>> + should be a child node of the SMMU in the device tree.
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - qcom,qsmmuv500-tbu
>> +
>> + reg:
>> + items:
>> + - description: Address and size of the TBU's register space.
>> +
>> + reg-names:
>> + items:
>> + - const: base
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + interconnects:
>> + maxItems: 1
What does this interconnect represent? MMU-500 TBUs don't access memory
themselves[3], they only have an internal AXI Stream interface to the
TCU to request translations.
Thanks,
Robin.
[1]
https://developer.arm.com/documentation/ddi0517/f/programmers-model/memory-model
[2]
https://lore.kernel.org/all/d652966348c78457c38bf18daf369272a4ebc2c9.1628682049.git.robin.murphy@arm.com/
[3] Yeah yeah, other than the special case of TBU0 issuing pagetable
walks on behalf of the TCU when it's not configured with its own
dedicated PTW interface, I know :P
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + qcom,stream-id-range:
>> + $ref: /schemas/types.yaml#/definitions/uint32-array
>> + description: Stream ID range (address and size) that is assigned by the TBU
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - interconnects
>> + - qcom,stream-id-range
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
>> + #include <dt-bindings/interconnect/qcom,sdm845.h>
>> + #include <dt-bindings/power/qcom-rpmpd.h>
>> +
>> +
>> + tbu@150e1000 {
>> + compatible = "qcom,qsmmuv500-tbu";
>> + reg = <0x150e1000 0x1000>;
>> + reg-names = "base";
>> + clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
>> + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>;
>> + interconnects = <&system_noc MASTER_GNOC_SNOC 0 &config_noc SLAVE_IMEM_CFG 0>;
>> + qcom,stream-id-range = <0x1c00 0x400>;
>> + };
>> +
>> +...
Hi Robin,
Thanks for taking a look at this!
On 10/25/2023 1:26 AM, Robin Murphy wrote:
> On 2023-10-24 19:42, Rob Herring wrote:
>> On Wed, Oct 18, 2023 at 07:19:18PM -0700, Georgi Djakov wrote:
>>> The "apps_smmu" on the Qualcomm sdm845 platform is an implementation
>>> of the ARM SMMU-500, that consists of a single TCU (Translation Control
>>> Unit) and multiple TBUs (Translation Buffer Units). The TCU is already
>>> being described in the ARM SMMU DT schema. Add also bindings for the
>>> TBUs so that we can describe their properties.
>>
>> Arm SMMU-500 is an implementation, too. Is QCom's a modified
>> implementation or you are just the first to want to control TBU
>> resources?
>
> It's very very modified. The stock MMU-500 has very few microarchitectural registers[1], they all live within the regular SMMU address space, are all Secure-only by default, and don't do anything like the shenanigans here.
>
> That said, looking at patch #3, I don't really understand why we need any of this stuff upstream... AFAICS it's doing an insane amount of work to use complicated imp-def debug functionality to duplicate things that the main driver can already do far more efficiently. Sure, in general it seems like it could potentially be useful stuff for bringing up and debugging a new driver, but the Linux SMMUv2 driver is mature and frankly already closer to being obsolete than to being new...
Yes, the arm-smmu driver already does similar stuff with the ATS feature, but this unfortunately isn't available in Qualcomm's implementation. Instead of that, there is this eCATS thing for debugging various issues including hardware issues. It supports many features, but here we use it just for hardware page table walks. And in the majority of cases it's expected that the software and hardware page table walks give the same result, but if there is a difference, it's sign of a problem. For example, it helped in the past to trace some power management issues of the SMMU. This of course is a debug feature and can enabled when needed.
> [ digression since I can't be bothered to split this discussion by replying separately to patch #3: ]
>
> I mean, just looking at qsmmuv500_iova_to_phys(), you do realise that that's going to be called potentially multiple times by iommu-dma for *every* dma_sync and dma_unmap call and really wants to be fast, right? This brings to mind all the work I did a couple of years back[2] because strict TLB invalidation on unmap was considered too slow for certain devices on QCom platforms by ChromeOS, yet what this achieves looks like it could easily be up to an order of magnitude slower again :(
No, this is not going to be called for every dma_sync and dma_unmap. In patch 5 we register a custom context_fault handler that uses this code to get information from the TBUs. So all of this is executed only when a context fault occurs. Does this sound acceptable?
[..]>>> +description:
>>> + TBU nodes represent Translation Buffer Units in an ARM SMMU. Each TBU node
>>> + should be a child node of the SMMU in the device tree.
>>> +
>>> +properties:
>>> + compatible:
>>> + enum:
>>> + - qcom,qsmmuv500-tbu
>>> +
>>> + reg:
>>> + items:
>>> + - description: Address and size of the TBU's register space.
>>> +
>>> + reg-names:
>>> + items:
>>> + - const: base
>>> +
>>> + clocks:
>>> + maxItems: 1
>>> +
>>> + interconnects:
>>> + maxItems: 1
>
> What does this interconnect represent? MMU-500 TBUs don't access memory themselves[3], they only have an internal AXI Stream interface to the TCU to request translations.
It's to enable access from the CPU to the register space of the TBUs.
Thanks,
Georgi