2016-04-21 15:07:52

by Lee Jones

[permalink] [raw]
Subject: [[PATCH v2] 1/8] ARM: dts: STi: STiH407: Provide generic (safe) DVFS configuration

You'll notice that the voltage cell is populated with 0's. Voltage
information is very platform specific, even depends on 'cut' and
'substrate' versions. Thus it is left blank for a generic (safe)
implementation. If other nodes/properties are provided by the
bootloader, the ST CPUFreq driver will over-ride these generic
values.

Signed-off-by: Lee Jones <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
---
arch/arm/boot/dts/stih407-family.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 81f8121..9fa1e58 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -22,15 +22,29 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+
/* u-boot puts hpen in SBC dmem at 0xa4 offset */
cpu-release-addr = <0x94100A4>;
+
+ /* kHz uV */
+ operating-points = <1500000 0
+ 1200000 0
+ 800000 0
+ 500000 0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+
/* u-boot puts hpen in SBC dmem at 0xa4 offset */
cpu-release-addr = <0x94100A4>;
+
+ /* kHz uV */
+ operating-points = <1500000 0
+ 1200000 0
+ 800000 0
+ 500000 0>;
};
};

--
2.8.0


2016-04-21 15:07:55

by Lee Jones

[permalink] [raw]
Subject: [[PATCH v2] 3/8] ARM: dts: STi: STiH407: Link CPU with its voltage supply

Used for Voltage Scaling using CPUFreq.

Signed-off-by: Lee Jones <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
---
arch/arm/boot/dts/stih407-family.dtsi | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index af9233b..d0e639cd 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -35,6 +35,7 @@
clocks = <&clk_m_a9>;
clock-names = "cpu";
clock-latency = <100000>;
+ cpu0-supply = <&pwm_regulator>;
};
cpu@1 {
device_type = "cpu";
--
2.8.0

2016-04-21 15:07:59

by Lee Jones

[permalink] [raw]
Subject: [[PATCH v2] 6/8] ARM: dts: STiH407: Add nodes for RemoteProc

Signed-off-by: Ludovic Barre <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
---
arch/arm/boot/dts/stih407-family.dtsi | 40 +++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 680b7c1..7cd358b 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -747,5 +747,45 @@
mbox-name = "st231_audio_video";
status = "okay";
};
+
+ st231_gp0: remote-processor@40000000 {
+ compatible = "st,st231-rproc";
+ reg = <0x40000000 0x01000000>;
+ resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
+ reset-names = "sw_reset";
+ clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
+ clock-frequency = <600000000>;
+ st,syscfg = <&syscfg_core 0x22c>;
+ };
+
+ st231_gp1: remote-processor@41000000 {
+ compatible = "st,st231-rproc";
+ reg = <0x41000000 0x01000000>;
+ resets = <&softreset STIH407_ST231_GP1_SOFTRESET>;
+ reset-names = "sw_reset";
+ clocks = <&clk_s_c0_flexgen CLK_ST231_GP_1>;
+ clock-frequency = <600000000>;
+ st,syscfg = <&syscfg_core 0x220>;
+ };
+
+ st231_audio: remote-processor@42000000 {
+ compatible = "st,st231-rproc";
+ reg = <0x42000000 0x01000000>;
+ resets = <&softreset STIH407_ST231_AUD_SOFTRESET>;
+ reset-names = "sw_reset";
+ clocks = <&clk_s_c0_flexgen CLK_ST231_AUD_0>;
+ clock-frequency = <600000000>;
+ st,syscfg = <&syscfg_core 0x228>;
+ };
+
+ st231_dmu: remote-processor@43000000 {
+ compatible = "st,st231-rproc";
+ reg = <0x43000000 0x01000000>;
+ resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
+ reset-names = "sw_reset";
+ clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
+ clock-frequency = <600000000>;
+ st,syscfg = <&syscfg_core 0x224>;
+ };
};
};
--
2.8.0

2016-04-21 15:07:57

by Lee Jones

[permalink] [raw]
Subject: [[PATCH v2] 7/8] ARM: dts: STiH407: Move over to using the 'reserved-memory' API for obtaining DMA memory

Doing so saves quite a bit of code in the driver.

For more information on the 'reserved-memory' bindings see:

Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt

Suggested-by: Suman Anna <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
---
arch/arm/boot/dts/stih407-family.dtsi | 47 +++++++++++++++++++++++++++++------
1 file changed, 39 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 7cd358b..33de7361 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -15,6 +15,36 @@
#address-cells = <1>;
#size-cells = <1>;

+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gp0_reserved: rproc@40000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x40000000 0x01000000>;
+ no-map;
+ };
+
+ gp1_reserved: rproc@41000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x41000000 0x01000000>;
+ no-map;
+ };
+
+ audio_reserved: rproc@42000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x42000000 0x01000000>;
+ no-map;
+ };
+
+ dmu_reserved: rproc@43000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x43000000 0x01000000>;
+ no-map;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -748,9 +778,9 @@
status = "okay";
};

- st231_gp0: remote-processor@40000000 {
+ st231_gp0: remote-processor {
compatible = "st,st231-rproc";
- reg = <0x40000000 0x01000000>;
+ memory-region = <&gp0_reserved>;
resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
reset-names = "sw_reset";
clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
@@ -758,9 +788,10 @@
st,syscfg = <&syscfg_core 0x22c>;
};

- st231_gp1: remote-processor@41000000 {
+
+ st231_gp1: remote-processor {
compatible = "st,st231-rproc";
- reg = <0x41000000 0x01000000>;
+ memory-region = <&gp1_reserved>;
resets = <&softreset STIH407_ST231_GP1_SOFTRESET>;
reset-names = "sw_reset";
clocks = <&clk_s_c0_flexgen CLK_ST231_GP_1>;
@@ -768,9 +799,9 @@
st,syscfg = <&syscfg_core 0x220>;
};

- st231_audio: remote-processor@42000000 {
+ st231_audio: remote-processor {
compatible = "st,st231-rproc";
- reg = <0x42000000 0x01000000>;
+ memory-region = <&audio_reserved>;
resets = <&softreset STIH407_ST231_AUD_SOFTRESET>;
reset-names = "sw_reset";
clocks = <&clk_s_c0_flexgen CLK_ST231_AUD_0>;
@@ -778,9 +809,9 @@
st,syscfg = <&syscfg_core 0x228>;
};

- st231_dmu: remote-processor@43000000 {
+ st231_dmu: remote-processor {
compatible = "st,st231-rproc";
- reg = <0x43000000 0x01000000>;
+ memory-region = <&dmu_reserved>;
resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
reset-names = "sw_reset";
clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
--
2.8.0

2016-04-21 15:08:45

by Lee Jones

[permalink] [raw]
Subject: [[PATCH v2] 5/8] ARM: dts: STi: stih407-family: Add nodes for Mailbox

This patch supplies the Mailbox Controller nodes. In order to
request channels, these nodes will be referenced by Mailbox
Client nodes.

Signed-off-by: Lee Jones <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
---
arch/arm/boot/dts/stih407-family.dtsi | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index eb2601f..680b7c1 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -714,5 +714,38 @@
clocks = <&clk_sysin>;
status = "okay";
};
+
+ mailbox0: mailbox@8f00000 {
+ compatible = "st,stih407-mailbox";
+ reg = <0x8f00000 0x1000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>;
+ #mbox-cells = <2>;
+ mbox-name = "a9";
+ status = "okay";
+ };
+
+ mailbox1: mailbox@8f01000 {
+ compatible = "st,stih407-mailbox";
+ reg = <0x8f01000 0x1000>;
+ #mbox-cells = <2>;
+ mbox-name = "st231_gp_1";
+ status = "okay";
+ };
+
+ mailbox2: mailbox@8f02000 {
+ compatible = "st,stih407-mailbox";
+ reg = <0x8f02000 0x1000>;
+ #mbox-cells = <2>;
+ mbox-name = "st231_gp_0";
+ status = "okay";
+ };
+
+ mailbox3: mailbox@8f03000 {
+ compatible = "st,stih407-mailbox";
+ reg = <0x8f03000 0x1000>;
+ #mbox-cells = <2>;
+ mbox-name = "st231_audio_video";
+ status = "okay";
+ };
};
};
--
2.8.0

2016-04-21 15:08:42

by Lee Jones

[permalink] [raw]
Subject: [[PATCH v2] 8/8] ARM: dts: STi: STih407: Switch LPC mode from RTC to Clocksource

This aligns with the internal configuration.

Signed-off-by: Lee Jones <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
---
arch/arm/boot/dts/stih407-family.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 33de7361..ad8ba10 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -584,7 +584,7 @@
reg = <0x8788000 0x1000>;
interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
- st,lpc-mode = <ST_LPC_MODE_RTC>;
+ st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
};

sata0: sata@9b20000 {
--
2.8.0

2016-04-21 15:09:23

by Lee Jones

[permalink] [raw]
Subject: [[PATCH v2] 4/8] ARM: dts: STi: STiH407: Provide CPU with a means to look-up Major number

This is used for CPU Frequency Scaling.

Signed-off-by: Lee Jones <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
---
arch/arm/boot/dts/stih407-family.dtsi | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index d0e639cd..eb2601f 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -36,6 +36,7 @@
clock-names = "cpu";
clock-latency = <100000>;
cpu0-supply = <&pwm_regulator>;
+ st,syscfg = <&syscfg_core 0x8e0>;
};
cpu@1 {
device_type = "cpu";
--
2.8.0

2016-04-21 15:09:52

by Lee Jones

[permalink] [raw]
Subject: [[PATCH v2] 2/8] ARM: dts: STi: STiH407: Provide CPU with clocking information

Signed-off-by: Lee Jones <[email protected]>
Signed-off-by: Maxime Coquelin <[email protected]>
---
arch/arm/boot/dts/stih407-family.dtsi | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 9fa1e58..af9233b 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -31,6 +31,10 @@
1200000 0
800000 0
500000 0>;
+
+ clocks = <&clk_m_a9>;
+ clock-names = "cpu";
+ clock-latency = <100000>;
};
cpu@1 {
device_type = "cpu";
--
2.8.0

2016-04-26 14:10:28

by Maxime Coquelin

[permalink] [raw]
Subject: Re: [[PATCH v2] 1/8] ARM: dts: STi: STiH407: Provide generic (safe) DVFS configuration

Hi Lee,

Series is applied, thanks for having done the changes.

Note that I had to rework all the commit titles, because of the
double brackets ("[[PATCH v2] 1/8]").
Something wrong with your script?

Thanks,
Maxime

On 04/21/2016 05:07 PM, Lee Jones wrote:
> You'll notice that the voltage cell is populated with 0's. Voltage
> information is very platform specific, even depends on 'cut' and
> 'substrate' versions. Thus it is left blank for a generic (safe)
> implementation. If other nodes/properties are provided by the
> bootloader, the ST CPUFreq driver will over-ride these generic
> values.
>
> Signed-off-by: Lee Jones <[email protected]>
> Signed-off-by: Maxime Coquelin <[email protected]>
> ---
> arch/arm/boot/dts/stih407-family.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
> index 81f8121..9fa1e58 100644
> --- a/arch/arm/boot/dts/stih407-family.dtsi
> +++ b/arch/arm/boot/dts/stih407-family.dtsi
> @@ -22,15 +22,29 @@
> device_type = "cpu";
> compatible = "arm,cortex-a9";
> reg = <0>;
> +
> /* u-boot puts hpen in SBC dmem at 0xa4 offset */
> cpu-release-addr = <0x94100A4>;
> +
> + /* kHz uV */
> + operating-points = <1500000 0
> + 1200000 0
> + 800000 0
> + 500000 0>;
> };
> cpu@1 {
> device_type = "cpu";
> compatible = "arm,cortex-a9";
> reg = <1>;
> +
> /* u-boot puts hpen in SBC dmem at 0xa4 offset */
> cpu-release-addr = <0x94100A4>;
> +
> + /* kHz uV */
> + operating-points = <1500000 0
> + 1200000 0
> + 800000 0
> + 500000 0>;
> };
> };
>

2016-04-26 17:35:59

by Lee Jones

[permalink] [raw]
Subject: Re: [[PATCH v2] 1/8] ARM: dts: STi: STiH407: Provide generic (safe) DVFS configuration

On Tue, 26 Apr 2016, Maxime Coquelin wrote:

> Hi Lee,
>
> Series is applied, thanks for having done the changes.
>
> Note that I had to rework all the commit titles, because of the double
> brackets ("[[PATCH v2] 1/8]").
> Something wrong with your script?

Apologies. Nothing wrong with the script, this was a manual error
that I didn't catch until after they'd been sent. Problem was

`git format-patch $sha..HEAD --subject-prefix="[PATCH v2]"`

... I should have omitted the '[]'s, since gfp does this for you.

> On 04/21/2016 05:07 PM, Lee Jones wrote:
> >You'll notice that the voltage cell is populated with 0's. Voltage
> >information is very platform specific, even depends on 'cut' and
> >'substrate' versions. Thus it is left blank for a generic (safe)
> >implementation. If other nodes/properties are provided by the
> >bootloader, the ST CPUFreq driver will over-ride these generic
> >values.
> >
> >Signed-off-by: Lee Jones <[email protected]>
> >Signed-off-by: Maxime Coquelin <[email protected]>
> >---
> > arch/arm/boot/dts/stih407-family.dtsi | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> >diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
> >index 81f8121..9fa1e58 100644
> >--- a/arch/arm/boot/dts/stih407-family.dtsi
> >+++ b/arch/arm/boot/dts/stih407-family.dtsi
> >@@ -22,15 +22,29 @@
> > device_type = "cpu";
> > compatible = "arm,cortex-a9";
> > reg = <0>;
> >+
> > /* u-boot puts hpen in SBC dmem at 0xa4 offset */
> > cpu-release-addr = <0x94100A4>;
> >+
> >+ /* kHz uV */
> >+ operating-points = <1500000 0
> >+ 1200000 0
> >+ 800000 0
> >+ 500000 0>;
> > };
> > cpu@1 {
> > device_type = "cpu";
> > compatible = "arm,cortex-a9";
> > reg = <1>;
> >+
> > /* u-boot puts hpen in SBC dmem at 0xa4 offset */
> > cpu-release-addr = <0x94100A4>;
> >+
> >+ /* kHz uV */
> >+ operating-points = <1500000 0
> >+ 1200000 0
> >+ 800000 0
> >+ 500000 0>;
> > };
> > };
>

--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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