Currently, the designware schema is defined on a text file:
designware-pcie.txt
It contains two separate schemas on it:
- snps,dw-pcie
This one uses the pci-bus.yaml schema;
- snps,dw-pcie-ep
This one uses the pci-ep.yaml schema.
As the:
AllOf:
- $ref: <foo>
for the endpoint part is different than the PCI one, place
it on a separate yaml file.
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
---
.../bindings/pci/snps,dw-pcie-ep.yaml | 90 +++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 91 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
new file mode 100644
index 000000000000..43baf29f8dd6
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare PCIe endpoint interface
+
+maintainers:
+ - Jingoo Han <[email protected]>
+ - Gustavo Pimentel <[email protected]>
+
+description: |
+ Synopsys DesignWare PCIe host controller endpoint
+
+allOf:
+ - $ref: /schemas/pci/pci-ep.yaml#
+
+properties:
+ compatible:
+ anyOf:
+ - {}
+ - const: snps,dw-pcie-ep
+
+ reg:
+ description: |
+ It should contain Data Bus Interface (dbi) and config registers for all
+ versions.
+ For designware core version >= 4.80, it may contain ATU address space.
+ minItems: 2
+ maxItems: 4
+
+ reg-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ enum: [dbi, dbi2, config, atu, addr_space, link]
+
+ reset-gpio:
+ description: GPIO pin number of PERST# signal
+ maxItems: 1
+ deprecated: true
+
+ reset-gpios:
+ description: GPIO controlled connection to PERST# signal
+ maxItems: 1
+
+ snps,enable-cdm-check:
+ type: boolean
+ description: |
+ This is a boolean property and if present enables
+ automatic checking of CDM (Configuration Dependent Module) registers
+ for data corruption. CDM registers include standard PCIe configuration
+ space registers, Port Logic registers, DMA and iATU (internal Address
+ Translation Unit) registers.
+
+ num-ib-windows:
+ description: number of inbound address translation windows
+ maxItems: 1
+ deprecated: true
+
+ num-ob-windows:
+ description: number of outbound address translation windows
+ maxItems: 1
+ deprecated: true
+
+ max-functions:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: maximum number of functions that can be configured
+
+required:
+ - reg
+ - reg-names
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pcie-ep@dfd00000 {
+ compatible = "snps,dw-pcie-ep";
+ reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
+ <0xdfc01000 0x0001000>, /* IP registers 2 */
+ <0xd0000000 0x2000000>; /* Configuration space */
+ reg-names = "dbi", "dbi2", "addr_space";
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index f0115c590731..f0cf510c26fd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14284,6 +14284,7 @@ L: [email protected]
S: Maintained
F: Documentation/devicetree/bindings/pci/designware-pcie.txt
F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+F: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
F: drivers/pci/controller/dwc/*designware*
PCI DRIVER FOR TI DRA7XX/J721E
--
2.31.1