Hi All,
This series adds support for a new next generation 64-bit TI DSP based on
the TMS320C71x CorePac processor subsystem called the C71x. The support is
enabled through couple of enhancements to the remoteproc core (primarily to
support a 64-bit trace resource entry), and does depend on the K3 DSP
remoteproc driver posted earlier today [1].
The loading support leveraged the 64-bit ELF loader support code added by
Clement and already staged on the rproc-next branch. I am posting this
series separate from the C66x series because of the new 64-bit resource
type enhancement needs (patches 2 and 3). I have leveraged the existing
resource types as is by introducing a new version element, and am open to
ideas if it is desired to just define it as a separate resource type.
The C71x DSP boots using firmware segments loaded into the DDR with a 2 MB
aligned address requirement on the boot vectors. There is no support for
internal memory loading, and all internal memories shall be used as fast
RAMs/scatchpads by the firmware executing on the DSPs. IPC is through the
virtio-rpmsg transport. There is no support for Error Recovery, Power
Management or loading into on-chip SRAMs at present.
Following is the patch summary:
- Patch 1 updates the K3 DSP bindings for C71x cores
- Patch 2 introduces a concept of version element into existing resource types
- Patch 3 adds support for a new 64-bit trace resource entry
- Patch 4 enhances the K3 DSP remoteproc driver for C71x
regards
Suman
[1] https://patchwork.kernel.org/cover/11458573/
Suman Anna (4):
dt-bindings: remoteproc: k3-dsp: Update bindings for C71x DSPs
remoteproc: introduce version element into resource type field
remoteproc: add support for a new 64-bit trace version
remoteproc/k3-dsp: Add support for C71x DSPs
.../bindings/remoteproc/ti,k3-dsp-rproc.yaml | 78 ++++++++++++++++---
drivers/remoteproc/remoteproc_core.c | 65 +++++++++++-----
drivers/remoteproc/remoteproc_debugfs.c | 50 ++++++++----
drivers/remoteproc/ti_k3_dsp_remoteproc.c | 17 ++++
include/linux/remoteproc.h | 34 +++++++-
5 files changed, 203 insertions(+), 41 deletions(-)
--
2.23.0
Some Texas Instruments K3 family of SoCs have one of more newer
generation TMS320C71x CorePac processor subsystem in addition to
the existing TMS320C66x CorePac processor subsystems. Update the
device tree bindings document for the C71x DSP devices.
The example is also updated to show the single C71 DSP present
on J721E SoCs.
Signed-off-by: Suman Anna <[email protected]>
---
.../bindings/remoteproc/ti,k3-dsp-rproc.yaml | 78 ++++++++++++++++---
1 file changed, 69 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml
index 416e3abe7937..6b1536509c39 100644
--- a/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml
@@ -27,9 +27,12 @@ description: |
properties:
compatible:
- const: ti,j721e-c66-dsp
+ enum:
+ - ti,j721e-c66-dsp
+ - ti,j721e-c71-dsp
description:
Use "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs
+ Use "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs
reg:
description: |
@@ -37,18 +40,11 @@ properties:
Each entry should have the memory region's start address
and the size of the region, the representation matching
the parent node's '#address-cells' and '#size-cells' values.
- minItems: 3
- maxItems: 3
reg-names:
description: |
Should contain strings with the names of the specific internal
internal memory regions, and should be defined in this order
- maxItems: 3
- items:
- - const: l2sram
- - const: l1pram
- - const: l1dram
ti,sci:
$ref: /schemas/types.yaml#/definitions/phandle
@@ -117,6 +113,41 @@ properties:
should be defined as per the generic bindings in,
Documentation/devicetree/bindings/sram/sram.yaml
+if:
+ properties:
+ compatible:
+ enum:
+ - ti,j721e-c66-dsp
+then:
+ properties:
+ reg:
+ minItems: 3
+ maxItems: 3
+ reg-names:
+ minItems: 3
+ maxItems: 3
+ items:
+ - const: l2sram
+ - const: l1pram
+ - const: l1dram
+else:
+ if:
+ properties:
+ compatible:
+ enum:
+ - ti,j721e-c71-dsp
+ then:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 2
+ reg-names:
+ minItems: 2
+ maxItems: 2
+ items:
+ - const: l2sram
+ - const: l1dram
+
required:
- compatible
- reg
@@ -152,13 +183,26 @@ examples:
reg = <0x00 0xa6100000 0x00 0xf00000>;
no-map;
};
+
+ c71_0_dma_memory_region: c71-dma-memory@a8000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8000000 0x00 0x100000>;
+ no-map;
+ };
+
+ c71_0_memory_region: c71-memory@a8100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa8100000 0x00 0xf00000>;
+ no-map;
+ };
};
cbass_main: interconnect@100000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
- ranges = <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
+ ranges = <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */
+ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
<0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */
/* J721E C66_0 DSP node */
@@ -177,4 +221,20 @@ examples:
<&c66_0_memory_region>;
mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
};
+
+ /* J721E C71_0 DSP node */
+ c71_0: dsp@64800000 {
+ compatible = "ti,j721e-c71-dsp";
+ reg = <0x00 0x64800000 0x00 0x00080000>,
+ <0x00 0x64e00000 0x00 0x0000c000>;
+ reg-names = "l2sram", "l1dram";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <15>;
+ ti,sci-proc-ids = <0x30 0xFF>;
+ resets = <&k3_reset 15 1>;
+ firmware-name = "j7-c71_0-fw";
+ memory-region = <&c71_0_dma_memory_region>,
+ <&c71_0_memory_region>;
+ mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
+ };
};
--
2.23.0
The Texas Instrument's K3 J721E SoCs have a newer next-generation
C71x DSP Subsystem in the MAIN voltage domain in addition to the
previous generation C66x DSP subsystems. The C71x DSP subsystem is
based on the TMS320C71x DSP CorePac module. The C71x CPU is a true
64-bit machine including 64-bit memory addressing and single-cycle
64-bit base arithmetic operations and supports vector signal processing
providing a significant lift in DSP processing power over C66x DSPs.
J721E SoCs use a C711 (a one-core 512-bit vector width CPU core) DSP
that is cache coherent with the A72 Arm cores.
Each subsystem has one or more Fixed/Floating-Point DSP CPUs, with 32 KB
of L1P Cache, 48 KB of L1D SRAM that can be configured and partitioned as
either RAM and/or Cache, and 512 KB of L2 SRAM configurable as either RAM
and/or Cache. The CorePac also includes a Matrix Multiplication Accelerator
(MMA), a Stream Engine (SE) and a C71x Memory Management Unit (CMMU), an
Interrupt Controller (INTC) and a Powerdown Management Unit (PMU) modules.
Update the existing K3 DSP remoteproc driver to add support for this C71x
DSP subsystem. The firmware loading support is provided by using the newly
added 64-bit ELF loader support, and is limited to images using only
external DDR memory at the moment. The L1D and L2 SRAMs are used as scratch
memory when using as RAMs, and cannot be used for loadable segments. The
CMMU is also not supported to begin with, and the driver is designed to
treat the MMU as if it is in bypass mode.
Signed-off-by: Suman Anna <[email protected]>
---
drivers/remoteproc/ti_k3_dsp_remoteproc.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/remoteproc/ti_k3_dsp_remoteproc.c b/drivers/remoteproc/ti_k3_dsp_remoteproc.c
index 7b712ef74611..48d26f7d5f48 100644
--- a/drivers/remoteproc/ti_k3_dsp_remoteproc.c
+++ b/drivers/remoteproc/ti_k3_dsp_remoteproc.c
@@ -649,6 +649,9 @@ static int k3_dsp_rproc_probe(struct platform_device *pdev)
rproc->has_iommu = false;
rproc->recovery_disabled = true;
+ /* C71x is a 64-bit processor, so plug in generic .sanity_check ops */
+ rproc->ops->sanity_check = rproc_elf_sanity_check;
+
kproc = rproc->priv;
kproc->rproc = rproc;
kproc->dev = dev;
@@ -789,6 +792,12 @@ static const struct k3_dsp_mem_data c66_mems[] = {
{ .name = "l1dram", .dev_addr = 0xf00000 },
};
+/* C71x cores only have a L1P Cache, there are no L1P SRAMs */
+static const struct k3_dsp_mem_data c71_mems[] = {
+ { .name = "l2sram", .dev_addr = 0x800000 },
+ { .name = "l1dram", .dev_addr = 0xe00000 },
+};
+
static const struct k3_dsp_dev_data c66_data = {
.mems = c66_mems,
.num_mems = ARRAY_SIZE(c66_mems),
@@ -796,8 +805,16 @@ static const struct k3_dsp_dev_data c66_data = {
.uses_lreset = true,
};
+static const struct k3_dsp_dev_data c71_data = {
+ .mems = c71_mems,
+ .num_mems = ARRAY_SIZE(c71_mems),
+ .boot_align_addr = SZ_2M,
+ .uses_lreset = false,
+};
+
static const struct of_device_id k3_dsp_of_match[] = {
{ .compatible = "ti,j721e-c66-dsp", .data = &c66_data, },
+ { .compatible = "ti,j721e-c71-dsp", .data = &c71_data, },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, k3_dsp_of_match);
--
2.23.0
On Wed, 25 Mar 2020 15:46:58 -0500, Suman Anna wrote:
> Some Texas Instruments K3 family of SoCs have one of more newer
> generation TMS320C71x CorePac processor subsystem in addition to
> the existing TMS320C66x CorePac processor subsystems. Update the
> device tree bindings document for the C71x DSP devices.
>
> The example is also updated to show the single C71 DSP present
> on J721E SoCs.
>
> Signed-off-by: Suman Anna <[email protected]>
> ---
> .../bindings/remoteproc/ti,k3-dsp-rproc.yaml | 78 ++++++++++++++++---
> 1 file changed, 69 insertions(+), 9 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On 3/25/20 3:47 PM, Suman Anna wrote:
> The Texas Instrument's K3 J721E SoCs have a newer next-generation
> C71x DSP Subsystem in the MAIN voltage domain in addition to the
> previous generation C66x DSP subsystems. The C71x DSP subsystem is
> based on the TMS320C71x DSP CorePac module. The C71x CPU is a true
> 64-bit machine including 64-bit memory addressing and single-cycle
> 64-bit base arithmetic operations and supports vector signal processing
> providing a significant lift in DSP processing power over C66x DSPs.
> J721E SoCs use a C711 (a one-core 512-bit vector width CPU core) DSP
> that is cache coherent with the A72 Arm cores.
>
> Each subsystem has one or more Fixed/Floating-Point DSP CPUs, with 32 KB
> of L1P Cache, 48 KB of L1D SRAM that can be configured and partitioned as
> either RAM and/or Cache, and 512 KB of L2 SRAM configurable as either RAM
> and/or Cache. The CorePac also includes a Matrix Multiplication Accelerator
> (MMA), a Stream Engine (SE) and a C71x Memory Management Unit (CMMU), an
> Interrupt Controller (INTC) and a Powerdown Management Unit (PMU) modules.
>
> Update the existing K3 DSP remoteproc driver to add support for this C71x
> DSP subsystem. The firmware loading support is provided by using the newly
> added 64-bit ELF loader support, and is limited to images using only
> external DDR memory at the moment. The L1D and L2 SRAMs are used as scratch
> memory when using as RAMs, and cannot be used for loadable segments. The
> CMMU is also not supported to begin with, and the driver is designed to
> treat the MMU as if it is in bypass mode.
>
> Signed-off-by: Suman Anna <[email protected]>
> ---
> drivers/remoteproc/ti_k3_dsp_remoteproc.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/remoteproc/ti_k3_dsp_remoteproc.c b/drivers/remoteproc/ti_k3_dsp_remoteproc.c
> index 7b712ef74611..48d26f7d5f48 100644
> --- a/drivers/remoteproc/ti_k3_dsp_remoteproc.c
> +++ b/drivers/remoteproc/ti_k3_dsp_remoteproc.c
> @@ -649,6 +649,9 @@ static int k3_dsp_rproc_probe(struct platform_device *pdev)
>
> rproc->has_iommu = false;
> rproc->recovery_disabled = true;
> + /* C71x is a 64-bit processor, so plug in generic .sanity_check ops */
> + rproc->ops->sanity_check = rproc_elf_sanity_check;
> +
Will drop this on the next version, this is no longer needed after
commit e29ff72b7794 ("remoteproc: remove rproc_elf32_sanity_check")
currently on rproc-next.
regards
Suman
> kproc = rproc->priv;
> kproc->rproc = rproc;
> kproc->dev = dev;
> @@ -789,6 +792,12 @@ static const struct k3_dsp_mem_data c66_mems[] = {
> { .name = "l1dram", .dev_addr = 0xf00000 },
> };
>
> +/* C71x cores only have a L1P Cache, there are no L1P SRAMs */
> +static const struct k3_dsp_mem_data c71_mems[] = {
> + { .name = "l2sram", .dev_addr = 0x800000 },
> + { .name = "l1dram", .dev_addr = 0xe00000 },
> +};
> +
> static const struct k3_dsp_dev_data c66_data = {
> .mems = c66_mems,
> .num_mems = ARRAY_SIZE(c66_mems),
> @@ -796,8 +805,16 @@ static const struct k3_dsp_dev_data c66_data = {
> .uses_lreset = true,
> };
>
> +static const struct k3_dsp_dev_data c71_data = {
> + .mems = c71_mems,
> + .num_mems = ARRAY_SIZE(c71_mems),
> + .boot_align_addr = SZ_2M,
> + .uses_lreset = false,
> +};
> +
> static const struct of_device_id k3_dsp_of_match[] = {
> { .compatible = "ti,j721e-c66-dsp", .data = &c66_data, },
> + { .compatible = "ti,j721e-c71-dsp", .data = &c71_data, },
> { /* sentinel */ },
> };
> MODULE_DEVICE_TABLE(of, k3_dsp_of_match);
>
On 3/25/20 3:46 PM, Suman Anna wrote:
> Hi All,
>
> This series adds support for a new next generation 64-bit TI DSP based on
> the TMS320C71x CorePac processor subsystem called the C71x. The support is
> enabled through couple of enhancements to the remoteproc core (primarily to
> support a 64-bit trace resource entry), and does depend on the K3 DSP
> remoteproc driver posted earlier today [1].
>
> The loading support leveraged the 64-bit ELF loader support code added by
> Clement and already staged on the rproc-next branch. I am posting this
> series separate from the C66x series because of the new 64-bit resource
> type enhancement needs (patches 2 and 3). I have leveraged the existing
> resource types as is by introducing a new version element, and am open to
> ideas if it is desired to just define it as a separate resource type.
>
> The C71x DSP boots using firmware segments loaded into the DDR with a 2 MB
> aligned address requirement on the boot vectors. There is no support for
> internal memory loading, and all internal memories shall be used as fast
> RAMs/scatchpads by the firmware executing on the DSPs. IPC is through the
> virtio-rpmsg transport. There is no support for Error Recovery, Power
> Management or loading into on-chip SRAMs at present.
>
> Following is the patch summary:
> - Patch 1 updates the K3 DSP bindings for C71x cores
> - Patch 2 introduces a concept of version element into existing resource types
> - Patch 3 adds support for a new 64-bit trace resource entry
> - Patch 4 enhances the K3 DSP remoteproc driver for C71x
I have separated out the C71 platform driver pieces (patches 1 & 4) and
posted a v2 for those.
Appreciate any feedback on the core patches (patches 2 & 3) that add the
minimal 64-bit trace support, as this also sets the direction for
resource extensions. I can post the next version for those based on
feedback.
regards
Suman
>
> regards
> Suman
>
> [1] https://patchwork.kernel.org/cover/11458573/
>
> Suman Anna (4):
> dt-bindings: remoteproc: k3-dsp: Update bindings for C71x DSPs
> remoteproc: introduce version element into resource type field
> remoteproc: add support for a new 64-bit trace version
> remoteproc/k3-dsp: Add support for C71x DSPs
>
> .../bindings/remoteproc/ti,k3-dsp-rproc.yaml | 78 ++++++++++++++++---
> drivers/remoteproc/remoteproc_core.c | 65 +++++++++++-----
> drivers/remoteproc/remoteproc_debugfs.c | 50 ++++++++----
> drivers/remoteproc/ti_k3_dsp_remoteproc.c | 17 ++++
> include/linux/remoteproc.h | 34 +++++++-
> 5 files changed, 203 insertions(+), 41 deletions(-)
>