This patchset adds USB support for Vybrid VF610 SoC. It extends the
clock framework to support the USB PHY cocks, extends the device
tree files and adds support for the non-core registers in the
usbmisc_imx driver.
This patchset needs the eSDHC length fix available in Shawn's
for-next branch.
The whole patchset proved to be working on a Colibri VF61. The
first USB controller runs in peripheral mode. I could successfully
use RNDIS, however with some stability issues: Suddenly the other
side was not reachable anymore and the interface needed to brought
down and back up again. I'm still investigating this.
The second USB controller, running in USB host mode, showed no
issues so far.
Stefan Agner (6):
ARM: dts: vf610: add USB PHY and controller
ARM: imx: clk-vf610: add USBPHY clocks
ARM: dts: vf610: Add usbmisc for non-core registers
chipidea: usbmisc_imx: Add USB support for VF610 SoCs
usb: phy: mxs: Add VF610 USB PHY support
ARM: dts: vf610-colibri: add USB support
arch/arm/boot/dts/vf610-colibri.dts | 10 +++++
arch/arm/boot/dts/vf610.dtsi | 55 ++++++++++++++++++++++--
arch/arm/mach-imx/clk-vf610.c | 12 +++++-
drivers/usb/chipidea/usbmisc_imx.c | 76 +++++++++++++++++++++++----------
drivers/usb/phy/phy-mxs-usb.c | 5 +++
include/dt-bindings/clock/vf610-clock.h | 5 ++-
6 files changed, 135 insertions(+), 28 deletions(-)
--
2.0.1
Add device tree node for usbmisc which controls the non-core USB
registers. This is required to use the property to disable the over-
current detection.
Signed-off-by: Stefan Agner <[email protected]>
---
arch/arm/boot/dts/vf610.dtsi | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index f6c3f02..b20ce4f 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -334,11 +334,19 @@
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBC0>;
fsl,usbphy = <&usbphy0>;
+ fsl,usbmisc = <&usbmisc 0>;
dr_mode = "peripheral";
status = "disabled";
};
-
+ usbmisc: usb@40034800 {
+ #index-cells = <1>;
+ compatible = "fsl,vf610-usbmisc";
+ reg = <0x40034800 0x200>,
+ <0x400b4800 0x200>;
+ clocks = <&clks VF610_CLK_USBC0>,
+ <&clks VF610_CLK_USBC1>;
+ };
};
aips1: aips-bus@40080000 {
@@ -407,6 +415,7 @@
interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks VF610_CLK_USBC1>;
fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 1>;
dr_mode = "host";
status = "disabled";
};
--
2.0.1
This adds USB PHY and USB controller nodes. Vybrid SoCs have two
independent USB cores which each supports DR (dual role). However,
real OTG is not supported since the OTG ID pin is not available.
The PHYs are located within the anadig register range, hence we need
to change the length of the anadig registers.
Signed-off-by: Stefan Agner <[email protected]>
---
arch/arm/boot/dts/vf610.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++---
1 file changed, 43 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 6a6190c..f6c3f02 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -25,6 +25,8 @@
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
+ usbphy0 = &usbphy0;
+ usbphy1 = &usbphy1;
};
cpus {
@@ -285,9 +287,25 @@
gpio-ranges = <&iomuxc 0 128 7>;
};
- anatop@40050000 {
- compatible = "fsl,vf610-anatop";
- reg = <0x40050000 0x1000>;
+ anatop: anatop@40050000 {
+ compatible = "fsl,vf610-anatop", "syscon";
+ reg = <0x40050000 0x400>;
+ };
+
+ usbphy0: usbphy@40050800 {
+ compatible = "fsl,vf610-usbphy", "fsl,imx23-usbphy";
+ reg = <0x40050800 0x400>;
+ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks VF610_CLK_USBPHY0>;
+ fsl,anatop = <&anatop>;
+ };
+
+ usbphy1: usbphy@40050c00 {
+ compatible = "fsl,vf610-usbphy", "fsl,imx23-usbphy";
+ reg = <0x40050c00 0x400>;
+ interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks VF610_CLK_USBPHY1>;
+ fsl,anatop = <&anatop>;
};
i2c0: i2c@40066000 {
@@ -309,6 +327,18 @@
reg = <0x4006b000 0x1000>;
#clock-cells = <1>;
};
+
+ usbdev0: usb@40034000 {
+ compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ reg = <0x40034000 0x800>;
+ interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks VF610_CLK_USBC0>;
+ fsl,usbphy = <&usbphy0>;
+ dr_mode = "peripheral";
+ status = "disabled";
+ };
+
+
};
aips1: aips-bus@40080000 {
@@ -371,6 +401,16 @@
status = "disabled";
};
+ usbh1: usb@400b4000 {
+ compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ reg = <0x400b4000 0x800>;
+ interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks VF610_CLK_USBC1>;
+ fsl,usbphy = <&usbphy1>;
+ dr_mode = "host";
+ status = "disabled";
+ };
+
ftm: ftm@400b8000 {
compatible = "fsl,ftm-timer";
reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
--
2.0.1
This adds support for the USB PHY in Vybrid VF610. We assume that
the disconnection without VBUS is also needed for Vybrid. For all
other flags, the presumption of innocence applies.
Signed-off-by: Stefan Agner <[email protected]>
---
drivers/usb/phy/phy-mxs-usb.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c
index c42bdf0..207946b 100644
--- a/drivers/usb/phy/phy-mxs-usb.c
+++ b/drivers/usb/phy/phy-mxs-usb.c
@@ -125,10 +125,15 @@ static const struct mxs_phy_data imx6sl_phy_data = {
MXS_PHY_NEED_IP_FIX,
};
+static const struct mxs_phy_data vf610_phy_data = {
+ .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
+};
+
static const struct of_device_id mxs_phy_dt_ids[] = {
{ .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
{ .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
{ .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
+ { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
--
2.0.1
Add USB support for Colibri VF61 modules. Due to lack of pinmux
options, the USB hosts over-current protection signal of the Colibri
standard could not be connected to the PHY's over-current protection,
hence we need to disable it.
Signed-off-by: Stefan Agner <[email protected]>
---
arch/arm/boot/dts/vf610-colibri.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/vf610-colibri.dts b/arch/arm/boot/dts/vf610-colibri.dts
index aecc7db..f2a950d 100644
--- a/arch/arm/boot/dts/vf610-colibri.dts
+++ b/arch/arm/boot/dts/vf610-colibri.dts
@@ -69,6 +69,16 @@
status = "okay";
};
+&usbdev0 {
+ disable-over-current;
+ status = "okay";
+};
+
+&usbh1 {
+ disable-over-current;
+ status = "okay";
+};
+
&iomuxc {
vf610-colibri {
pinctrl_esdhc1: esdhc1grp {
--
2.0.1
This commit adds PLL7 which is required for USBPHY1. It also adds
the USB PHY and USB Controller clocks and the gates to enable them.
Signed-off-by: Stefan Agner <[email protected]>
---
All the main PLLs are currently turned on by boot ROM or boot loader, within
the kernel we only set the fixed factor. Altough, the function imx_clk_pllv3
would provide enabling and rate calculation support.
Because PLL7 is _not_ enabled at boot up, we need enable support. With this,
we make use of the imx_clk_pllv3 function the first time in clk-vf610. In
order to be aligned, would it make sense to use the function for all the
main PLLs? I think support for all types of PLL available in Vybrid is
already there, altough this need to be verified first.
arch/arm/mach-imx/clk-vf610.c | 12 ++++++++++--
include/dt-bindings/clock/vf610-clock.h | 5 ++++-
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index 22dc3ee..159c5c4 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -58,6 +58,8 @@
#define PFD_PLL1_BASE (anatop_base + 0x2b0)
#define PFD_PLL2_BASE (anatop_base + 0x100)
#define PFD_PLL3_BASE (anatop_base + 0xf0)
+#define PLL3_CTRL (anatop_base + 0x10)
+#define PLL7_CTRL (anatop_base + 0x20)
static void __iomem *anatop_base;
static void __iomem *ccm_base;
@@ -148,6 +150,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
/* pll6: default 960Mhz */
clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
+ /* pll7: USB1 PLL at 480MHz */
+ clk[VF610_CLK_PLL7_MAIN] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_main", "fast_clk_sel", PLL7_CTRL, 0x2);
+
clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
@@ -160,8 +165,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
- clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4));
- clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4));
+ clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_main", PLL3_CTRL, 6);
+ clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_main", PLL7_CTRL, 6);
+
+ clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4));
+ clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4));
clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4);
clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index a916029..6593757 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -164,6 +164,9 @@
#define VF610_CLK_DMAMUX1 151
#define VF610_CLK_DMAMUX2 152
#define VF610_CLK_DMAMUX3 153
-#define VF610_CLK_END 154
+#define VF610_CLK_PLL7_MAIN 154
+#define VF610_CLK_USBPHY0 155
+#define VF610_CLK_USBPHY1 156
+#define VF610_CLK_END 157
#endif /* __DT_BINDINGS_CLOCK_VF610_H */
--
2.0.1
This adds Vybrid VF610 SoC support. The IP is very similar to i.MX6,
however the non-core registers are spread in two different register
areas. Hence we support multiple registers which are addressed by
the index of usbmisc.
Signed-off-by: Stefan Agner <[email protected]>
---
I tried first to create two usbmisc nodes and hoped it would instanciate
the driver twice, however, the driver currently only supports one instance.
In an short attempt to add support for that, I realized that since the
data structure holding the information for each instance is within the
driver ci_hdrc_imx. For Vybrid two instances would make much more sense,
however, a i.MX6Q shares all the non-core registers in one register area,
hence only one driver can map this area. I ended up with this multiple
registers solution, altough for the Vybrid multiple instances would
probably make more sense. Any thoughts on this?
drivers/usb/chipidea/usbmisc_imx.c | 76 +++++++++++++++++++++++++++-----------
1 file changed, 54 insertions(+), 22 deletions(-)
diff --git a/drivers/usb/chipidea/usbmisc_imx.c b/drivers/usb/chipidea/usbmisc_imx.c
index 85293b8..61c2350 100644
--- a/drivers/usb/chipidea/usbmisc_imx.c
+++ b/drivers/usb/chipidea/usbmisc_imx.c
@@ -57,6 +57,10 @@
#define MX6_BM_OVER_CUR_DIS BIT(7)
+#define VF610_OVER_CUR_DIS BIT(7)
+
+#define MAX_BASE_ADDR 2
+
struct usbmisc_ops {
/* It's called once when probe a usb device */
int (*init)(struct imx_usbmisc_data *data);
@@ -65,7 +69,7 @@ struct usbmisc_ops {
};
struct imx_usbmisc {
- void __iomem *base;
+ void __iomem *base[MAX_BASE_ADDR];
spinlock_t lock;
struct clk *clk;
const struct usbmisc_ops *ops;
@@ -84,20 +88,20 @@ static int usbmisc_imx25_init(struct imx_usbmisc_data *data)
spin_lock_irqsave(&usbmisc->lock, flags);
switch (data->index) {
case 0:
- val = readl(usbmisc->base);
+ val = readl(usbmisc->base[0]);
val &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PP_BIT);
val |= (MX25_EHCI_INTERFACE_DIFF_UNI & MX25_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
val |= (MX25_OTG_PM_BIT | MX25_OTG_OCPOL_BIT);
- writel(val, usbmisc->base);
+ writel(val, usbmisc->base[0]);
break;
case 1:
- val = readl(usbmisc->base);
+ val = readl(usbmisc->base[0]);
val &= ~(MX25_H1_SIC_MASK | MX25_H1_PP_BIT | MX25_H1_IPPUE_UP_BIT);
val |= (MX25_EHCI_INTERFACE_SINGLE_UNI & MX25_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
val |= (MX25_H1_PM_BIT | MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT);
- writel(val, usbmisc->base);
+ writel(val, usbmisc->base[0]);
break;
}
@@ -115,7 +119,7 @@ static int usbmisc_imx25_post(struct imx_usbmisc_data *data)
if (data->index > 2)
return -EINVAL;
- reg = usbmisc->base + MX25_USB_PHY_CTRL_OFFSET;
+ reg = usbmisc->base[0] + MX25_USB_PHY_CTRL_OFFSET;
if (data->evdo) {
spin_lock_irqsave(&usbmisc->lock, flags);
@@ -149,10 +153,10 @@ static int usbmisc_imx27_init(struct imx_usbmisc_data *data)
spin_lock_irqsave(&usbmisc->lock, flags);
if (data->disable_oc)
- val = readl(usbmisc->base) | val;
+ val = readl(usbmisc->base[0]) | val;
else
- val = readl(usbmisc->base) & ~val;
- writel(val, usbmisc->base);
+ val = readl(usbmisc->base[0]) & ~val;
+ writel(val, usbmisc->base[0]);
spin_unlock_irqrestore(&usbmisc->lock, flags);
return 0;
@@ -168,29 +172,29 @@ static int usbmisc_imx53_init(struct imx_usbmisc_data *data)
return -EINVAL;
/* Select a 24 MHz reference clock for the PHY */
- reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET;
+ reg = usbmisc->base[0] + MX53_USB_OTG_PHY_CTRL_1_OFFSET;
val = readl(reg);
val &= ~MX53_USB_PHYCTRL1_PLLDIV_MASK;
val |= MX53_USB_PLL_DIV_24_MHZ;
- writel(val, usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET);
+ writel(val, usbmisc->base[0] + MX53_USB_OTG_PHY_CTRL_1_OFFSET);
if (data->disable_oc) {
spin_lock_irqsave(&usbmisc->lock, flags);
switch (data->index) {
case 0:
- reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_0_OFFSET;
+ reg = usbmisc->base[0] + MX53_USB_OTG_PHY_CTRL_0_OFFSET;
val = readl(reg) | MX53_BM_OVER_CUR_DIS_OTG;
break;
case 1:
- reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_0_OFFSET;
+ reg = usbmisc->base[0] + MX53_USB_OTG_PHY_CTRL_0_OFFSET;
val = readl(reg) | MX53_BM_OVER_CUR_DIS_H1;
break;
case 2:
- reg = usbmisc->base + MX53_USB_UH2_CTRL_OFFSET;
+ reg = usbmisc->base[0] + MX53_USB_UH2_CTRL_OFFSET;
val = readl(reg) | MX53_BM_OVER_CUR_DIS_UHx;
break;
case 3:
- reg = usbmisc->base + MX53_USB_UH3_CTRL_OFFSET;
+ reg = usbmisc->base[0] + MX53_USB_UH3_CTRL_OFFSET;
val = readl(reg) | MX53_BM_OVER_CUR_DIS_UHx;
break;
}
@@ -212,15 +216,31 @@ static int usbmisc_imx6q_init(struct imx_usbmisc_data *data)
if (data->disable_oc) {
spin_lock_irqsave(&usbmisc->lock, flags);
- reg = readl(usbmisc->base + data->index * 4);
+ reg = readl(usbmisc->base[0] + data->index * 4);
writel(reg | MX6_BM_OVER_CUR_DIS,
- usbmisc->base + data->index * 4);
+ usbmisc->base[0] + data->index * 4);
spin_unlock_irqrestore(&usbmisc->lock, flags);
}
return 0;
}
+static int usbmisc_vf610_init(struct imx_usbmisc_data *data)
+{
+ u32 reg;
+
+ if (data->index >= 2)
+ return -EINVAL;
+
+ if (data->disable_oc) {
+ reg = readl(usbmisc->base[data->index]);
+ writel(reg | VF610_OVER_CUR_DIS,
+ usbmisc->base[data->index]);
+ }
+
+ return 0;
+}
+
static const struct usbmisc_ops imx25_usbmisc_ops = {
.init = usbmisc_imx25_init,
.post = usbmisc_imx25_post,
@@ -238,6 +258,10 @@ static const struct usbmisc_ops imx6q_usbmisc_ops = {
.init = usbmisc_imx6q_init,
};
+static const struct usbmisc_ops vf610_usbmisc_ops = {
+ .init = usbmisc_vf610_init,
+};
+
int imx_usbmisc_init(struct imx_usbmisc_data *data)
{
if (!usbmisc)
@@ -283,6 +307,10 @@ static const struct of_device_id usbmisc_imx_dt_ids[] = {
.compatible = "fsl,imx6q-usbmisc",
.data = &imx6q_usbmisc_ops,
},
+ {
+ .compatible = "fsl,vf610-usbmisc",
+ .data = &vf610_usbmisc_ops,
+ },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, usbmisc_imx_dt_ids);
@@ -291,7 +319,7 @@ static int usbmisc_imx_probe(struct platform_device *pdev)
{
struct resource *res;
struct imx_usbmisc *data;
- int ret;
+ int ret, i;
struct of_device_id *tmp_dev;
if (usbmisc)
@@ -303,10 +331,14 @@ static int usbmisc_imx_probe(struct platform_device *pdev)
spin_lock_init(&data->lock);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- data->base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(data->base))
- return PTR_ERR(data->base);
+ for (i = 0; i < MAX_BASE_ADDR; i++) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+ data->base[i] = devm_ioremap_resource(&pdev->dev, res);
+
+ /* First base address is mandatory */
+ if (IS_ERR(data->base) && !i)
+ return PTR_ERR(data->base);
+ }
data->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(data->clk)) {
--
2.0.1
On Fri, Jul 18, 2014 at 07:01:36PM +0200, Stefan Agner wrote:
> This patchset adds USB support for Vybrid VF610 SoC. It extends the
> clock framework to support the USB PHY cocks, extends the device
> tree files and adds support for the non-core registers in the
> usbmisc_imx driver.
>
> This patchset needs the eSDHC length fix available in Shawn's
> for-next branch.
>
Why it is related to USB patchset?
> The whole patchset proved to be working on a Colibri VF61. The
> first USB controller runs in peripheral mode. I could successfully
> use RNDIS, however with some stability issues: Suddenly the other
> side was not reachable anymore and the interface needed to brought
> down and back up again. I'm still investigating this.
Do you use ubuntu as host distribution? I find ubuntu will lost the
first connection for usb-ethernet-gadget(usb0) as network interface,
but once you re-config usb0 again (ifconfig usb0 ip up), it should work
and will not lose connection any more.
>
> The second USB controller, running in USB host mode, showed no
> issues so far.
>
> Stefan Agner (6):
> ARM: dts: vf610: add USB PHY and controller
> ARM: imx: clk-vf610: add USBPHY clocks
> ARM: dts: vf610: Add usbmisc for non-core registers
> chipidea: usbmisc_imx: Add USB support for VF610 SoCs
> usb: phy: mxs: Add VF610 USB PHY support
> ARM: dts: vf610-colibri: add USB support
>
> arch/arm/boot/dts/vf610-colibri.dts | 10 +++++
> arch/arm/boot/dts/vf610.dtsi | 55 ++++++++++++++++++++++--
> arch/arm/mach-imx/clk-vf610.c | 12 +++++-
> drivers/usb/chipidea/usbmisc_imx.c | 76 +++++++++++++++++++++++----------
> drivers/usb/phy/phy-mxs-usb.c | 5 +++
> include/dt-bindings/clock/vf610-clock.h | 5 ++-
> 6 files changed, 135 insertions(+), 28 deletions(-)
>
> --
> 2.0.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to [email protected]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Best Regards,
Peter Chen
On Fri, Jul 18, 2014 at 07:01:41PM +0200, Stefan Agner wrote:
> This adds support for the USB PHY in Vybrid VF610. We assume that
> the disconnection without VBUS is also needed for Vybrid. For all
> other flags, the presumption of innocence applies.
>
> Signed-off-by: Stefan Agner <[email protected]>
> ---
> drivers/usb/phy/phy-mxs-usb.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c
> index c42bdf0..207946b 100644
> --- a/drivers/usb/phy/phy-mxs-usb.c
> +++ b/drivers/usb/phy/phy-mxs-usb.c
> @@ -125,10 +125,15 @@ static const struct mxs_phy_data imx6sl_phy_data = {
> MXS_PHY_NEED_IP_FIX,
> };
>
> +static const struct mxs_phy_data vf610_phy_data = {
> + .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
> +};
> +
> static const struct of_device_id mxs_phy_dt_ids[] = {
> { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
> { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
> { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
> + { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
> --
> 2.0.1
>
Acked-by: Peter Chen <[email protected]>
--
Best Regards,
Peter Chen
On Fri, Jul 18, 2014 at 07:01:40PM +0200, Stefan Agner wrote:
> This adds Vybrid VF610 SoC support. The IP is very similar to i.MX6,
> however the non-core registers are spread in two different register
> areas. Hence we support multiple registers which are addressed by
> the index of usbmisc.
>
> Signed-off-by: Stefan Agner <[email protected]>
> ---
> I tried first to create two usbmisc nodes and hoped it would instanciate
> the driver twice, however, the driver currently only supports one instance.
> In an short attempt to add support for that, I realized that since the
> data structure holding the information for each instance is within the
> driver ci_hdrc_imx. For Vybrid two instances would make much more sense,
> however, a i.MX6Q shares all the non-core registers in one register area,
> hence only one driver can map this area. I ended up with this multiple
> registers solution, altough for the Vybrid multiple instances would
> probably make more sense. Any thoughts on this?
>
I prefer rename current usbmisc_imx as usbmisc_mix_v1 and create the
new usbmisc_imx_v2 for multiple instances case.
Peter
> drivers/usb/chipidea/usbmisc_imx.c | 76 +++++++++++++++++++++++++++-----------
> 1 file changed, 54 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/usb/chipidea/usbmisc_imx.c b/drivers/usb/chipidea/usbmisc_imx.c
> index 85293b8..61c2350 100644
> --- a/drivers/usb/chipidea/usbmisc_imx.c
> +++ b/drivers/usb/chipidea/usbmisc_imx.c
> @@ -57,6 +57,10 @@
>
> #define MX6_BM_OVER_CUR_DIS BIT(7)
>
> +#define VF610_OVER_CUR_DIS BIT(7)
> +
> +#define MAX_BASE_ADDR 2
> +
> struct usbmisc_ops {
> /* It's called once when probe a usb device */
> int (*init)(struct imx_usbmisc_data *data);
> @@ -65,7 +69,7 @@ struct usbmisc_ops {
> };
>
> struct imx_usbmisc {
> - void __iomem *base;
> + void __iomem *base[MAX_BASE_ADDR];
> spinlock_t lock;
> struct clk *clk;
> const struct usbmisc_ops *ops;
> @@ -84,20 +88,20 @@ static int usbmisc_imx25_init(struct imx_usbmisc_data *data)
> spin_lock_irqsave(&usbmisc->lock, flags);
> switch (data->index) {
> case 0:
> - val = readl(usbmisc->base);
> + val = readl(usbmisc->base[0]);
> val &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PP_BIT);
> val |= (MX25_EHCI_INTERFACE_DIFF_UNI & MX25_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
> val |= (MX25_OTG_PM_BIT | MX25_OTG_OCPOL_BIT);
> - writel(val, usbmisc->base);
> + writel(val, usbmisc->base[0]);
> break;
> case 1:
> - val = readl(usbmisc->base);
> + val = readl(usbmisc->base[0]);
> val &= ~(MX25_H1_SIC_MASK | MX25_H1_PP_BIT | MX25_H1_IPPUE_UP_BIT);
> val |= (MX25_EHCI_INTERFACE_SINGLE_UNI & MX25_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
> val |= (MX25_H1_PM_BIT | MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
> MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT);
>
> - writel(val, usbmisc->base);
> + writel(val, usbmisc->base[0]);
>
> break;
> }
> @@ -115,7 +119,7 @@ static int usbmisc_imx25_post(struct imx_usbmisc_data *data)
> if (data->index > 2)
> return -EINVAL;
>
> - reg = usbmisc->base + MX25_USB_PHY_CTRL_OFFSET;
> + reg = usbmisc->base[0] + MX25_USB_PHY_CTRL_OFFSET;
>
> if (data->evdo) {
> spin_lock_irqsave(&usbmisc->lock, flags);
> @@ -149,10 +153,10 @@ static int usbmisc_imx27_init(struct imx_usbmisc_data *data)
>
> spin_lock_irqsave(&usbmisc->lock, flags);
> if (data->disable_oc)
> - val = readl(usbmisc->base) | val;
> + val = readl(usbmisc->base[0]) | val;
> else
> - val = readl(usbmisc->base) & ~val;
> - writel(val, usbmisc->base);
> + val = readl(usbmisc->base[0]) & ~val;
> + writel(val, usbmisc->base[0]);
> spin_unlock_irqrestore(&usbmisc->lock, flags);
>
> return 0;
> @@ -168,29 +172,29 @@ static int usbmisc_imx53_init(struct imx_usbmisc_data *data)
> return -EINVAL;
>
> /* Select a 24 MHz reference clock for the PHY */
> - reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET;
> + reg = usbmisc->base[0] + MX53_USB_OTG_PHY_CTRL_1_OFFSET;
> val = readl(reg);
> val &= ~MX53_USB_PHYCTRL1_PLLDIV_MASK;
> val |= MX53_USB_PLL_DIV_24_MHZ;
> - writel(val, usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET);
> + writel(val, usbmisc->base[0] + MX53_USB_OTG_PHY_CTRL_1_OFFSET);
>
> if (data->disable_oc) {
> spin_lock_irqsave(&usbmisc->lock, flags);
> switch (data->index) {
> case 0:
> - reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_0_OFFSET;
> + reg = usbmisc->base[0] + MX53_USB_OTG_PHY_CTRL_0_OFFSET;
> val = readl(reg) | MX53_BM_OVER_CUR_DIS_OTG;
> break;
> case 1:
> - reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_0_OFFSET;
> + reg = usbmisc->base[0] + MX53_USB_OTG_PHY_CTRL_0_OFFSET;
> val = readl(reg) | MX53_BM_OVER_CUR_DIS_H1;
> break;
> case 2:
> - reg = usbmisc->base + MX53_USB_UH2_CTRL_OFFSET;
> + reg = usbmisc->base[0] + MX53_USB_UH2_CTRL_OFFSET;
> val = readl(reg) | MX53_BM_OVER_CUR_DIS_UHx;
> break;
> case 3:
> - reg = usbmisc->base + MX53_USB_UH3_CTRL_OFFSET;
> + reg = usbmisc->base[0] + MX53_USB_UH3_CTRL_OFFSET;
> val = readl(reg) | MX53_BM_OVER_CUR_DIS_UHx;
> break;
> }
> @@ -212,15 +216,31 @@ static int usbmisc_imx6q_init(struct imx_usbmisc_data *data)
>
> if (data->disable_oc) {
> spin_lock_irqsave(&usbmisc->lock, flags);
> - reg = readl(usbmisc->base + data->index * 4);
> + reg = readl(usbmisc->base[0] + data->index * 4);
> writel(reg | MX6_BM_OVER_CUR_DIS,
> - usbmisc->base + data->index * 4);
> + usbmisc->base[0] + data->index * 4);
> spin_unlock_irqrestore(&usbmisc->lock, flags);
> }
>
> return 0;
> }
>
> +static int usbmisc_vf610_init(struct imx_usbmisc_data *data)
> +{
> + u32 reg;
> +
> + if (data->index >= 2)
> + return -EINVAL;
> +
> + if (data->disable_oc) {
> + reg = readl(usbmisc->base[data->index]);
> + writel(reg | VF610_OVER_CUR_DIS,
> + usbmisc->base[data->index]);
> + }
> +
> + return 0;
> +}
> +
> static const struct usbmisc_ops imx25_usbmisc_ops = {
> .init = usbmisc_imx25_init,
> .post = usbmisc_imx25_post,
> @@ -238,6 +258,10 @@ static const struct usbmisc_ops imx6q_usbmisc_ops = {
> .init = usbmisc_imx6q_init,
> };
>
> +static const struct usbmisc_ops vf610_usbmisc_ops = {
> + .init = usbmisc_vf610_init,
> +};
> +
> int imx_usbmisc_init(struct imx_usbmisc_data *data)
> {
> if (!usbmisc)
> @@ -283,6 +307,10 @@ static const struct of_device_id usbmisc_imx_dt_ids[] = {
> .compatible = "fsl,imx6q-usbmisc",
> .data = &imx6q_usbmisc_ops,
> },
> + {
> + .compatible = "fsl,vf610-usbmisc",
> + .data = &vf610_usbmisc_ops,
> + },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, usbmisc_imx_dt_ids);
> @@ -291,7 +319,7 @@ static int usbmisc_imx_probe(struct platform_device *pdev)
> {
> struct resource *res;
> struct imx_usbmisc *data;
> - int ret;
> + int ret, i;
> struct of_device_id *tmp_dev;
>
> if (usbmisc)
> @@ -303,10 +331,14 @@ static int usbmisc_imx_probe(struct platform_device *pdev)
>
> spin_lock_init(&data->lock);
>
> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - data->base = devm_ioremap_resource(&pdev->dev, res);
> - if (IS_ERR(data->base))
> - return PTR_ERR(data->base);
> + for (i = 0; i < MAX_BASE_ADDR; i++) {
> + res = platform_get_resource(pdev, IORESOURCE_MEM, i);
> + data->base[i] = devm_ioremap_resource(&pdev->dev, res);
> +
> + /* First base address is mandatory */
> + if (IS_ERR(data->base) && !i)
> + return PTR_ERR(data->base);
> + }
>
> data->clk = devm_clk_get(&pdev->dev, NULL);
> if (IS_ERR(data->clk)) {
> --
> 2.0.1
>
--
Best Regards,
Peter Chen
On Fri, Jul 18, 2014 at 07:01:41PM +0200, Stefan Agner wrote:
> This adds support for the USB PHY in Vybrid VF610. We assume that
> the disconnection without VBUS is also needed for Vybrid. For all
> other flags, the presumption of innocence applies.
>
> Signed-off-by: Stefan Agner <[email protected]>
> ---
> drivers/usb/phy/phy-mxs-usb.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c
> index c42bdf0..207946b 100644
> --- a/drivers/usb/phy/phy-mxs-usb.c
> +++ b/drivers/usb/phy/phy-mxs-usb.c
> @@ -125,10 +125,15 @@ static const struct mxs_phy_data imx6sl_phy_data = {
> MXS_PHY_NEED_IP_FIX,
> };
>
> +static const struct mxs_phy_data vf610_phy_data = {
> + .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
> +};
> +
> static const struct of_device_id mxs_phy_dt_ids[] = {
> { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
> { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
> { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
> + { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, },
This new compatible string should be documented in
Documentation/devicetree/bindings/usb/mxs-phy.txt.
Shawn
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
> --
> 2.0.1
>
On Fri, Jul 18, 2014 at 07:01:37PM +0200, Stefan Agner wrote:
> This adds USB PHY and USB controller nodes. Vybrid SoCs have two
> independent USB cores which each supports DR (dual role). However,
> real OTG is not supported since the OTG ID pin is not available.
>
> The PHYs are located within the anadig register range, hence we need
> to change the length of the anadig registers.
>
> Signed-off-by: Stefan Agner <[email protected]>
> ---
> arch/arm/boot/dts/vf610.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 43 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
> index 6a6190c..f6c3f02 100644
> --- a/arch/arm/boot/dts/vf610.dtsi
> +++ b/arch/arm/boot/dts/vf610.dtsi
> @@ -25,6 +25,8 @@
> gpio2 = &gpio3;
> gpio3 = &gpio4;
> gpio4 = &gpio5;
> + usbphy0 = &usbphy0;
> + usbphy1 = &usbphy1;
> };
>
> cpus {
> @@ -285,9 +287,25 @@
> gpio-ranges = <&iomuxc 0 128 7>;
> };
>
> - anatop@40050000 {
> - compatible = "fsl,vf610-anatop";
> - reg = <0x40050000 0x1000>;
> + anatop: anatop@40050000 {
> + compatible = "fsl,vf610-anatop", "syscon";
> + reg = <0x40050000 0x400>;
> + };
> +
> + usbphy0: usbphy@40050800 {
> + compatible = "fsl,vf610-usbphy", "fsl,imx23-usbphy";
Since phy driver will match "fsl,vf610-usbphy" anyway, we do not need
"fsl,imx23-usbphy" here.
> + reg = <0x40050800 0x400>;
> + interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks VF610_CLK_USBPHY0>;
> + fsl,anatop = <&anatop>;
> + };
> +
> + usbphy1: usbphy@40050c00 {
> + compatible = "fsl,vf610-usbphy", "fsl,imx23-usbphy";
> + reg = <0x40050c00 0x400>;
> + interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks VF610_CLK_USBPHY1>;
> + fsl,anatop = <&anatop>;
> };
>
> i2c0: i2c@40066000 {
> @@ -309,6 +327,18 @@
> reg = <0x4006b000 0x1000>;
> #clock-cells = <1>;
> };
> +
> + usbdev0: usb@40034000 {
> + compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
It doesn't really make any sense to have "fsl,imx6q-usb" here. The
following one should be less confusing.
compatible = "fsl,vf610-usb", "fsl,imx27-usb";
Shawn
> + reg = <0x40034000 0x800>;
> + interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks VF610_CLK_USBC0>;
> + fsl,usbphy = <&usbphy0>;
> + dr_mode = "peripheral";
> + status = "disabled";
> + };
> +
> +
> };
>
> aips1: aips-bus@40080000 {
> @@ -371,6 +401,16 @@
> status = "disabled";
> };
>
> + usbh1: usb@400b4000 {
> + compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
> + reg = <0x400b4000 0x800>;
> + interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks VF610_CLK_USBC1>;
> + fsl,usbphy = <&usbphy1>;
> + dr_mode = "host";
> + status = "disabled";
> + };
> +
> ftm: ftm@400b8000 {
> compatible = "fsl,ftm-timer";
> reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
> --
> 2.0.1
>
On Fri, Jul 18, 2014 at 07:01:38PM +0200, Stefan Agner wrote:
> This commit adds PLL7 which is required for USBPHY1. It also adds
> the USB PHY and USB Controller clocks and the gates to enable them.
>
> Signed-off-by: Stefan Agner <[email protected]>
Jingchang,
Does the patch look good to you?
Shawn
> ---
> All the main PLLs are currently turned on by boot ROM or boot loader, within
> the kernel we only set the fixed factor. Altough, the function imx_clk_pllv3
> would provide enabling and rate calculation support.
> Because PLL7 is _not_ enabled at boot up, we need enable support. With this,
> we make use of the imx_clk_pllv3 function the first time in clk-vf610. In
> order to be aligned, would it make sense to use the function for all the
> main PLLs? I think support for all types of PLL available in Vybrid is
> already there, altough this need to be verified first.
>
> arch/arm/mach-imx/clk-vf610.c | 12 ++++++++++--
> include/dt-bindings/clock/vf610-clock.h | 5 ++++-
> 2 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
> index 22dc3ee..159c5c4 100644
> --- a/arch/arm/mach-imx/clk-vf610.c
> +++ b/arch/arm/mach-imx/clk-vf610.c
> @@ -58,6 +58,8 @@
> #define PFD_PLL1_BASE (anatop_base + 0x2b0)
> #define PFD_PLL2_BASE (anatop_base + 0x100)
> #define PFD_PLL3_BASE (anatop_base + 0xf0)
> +#define PLL3_CTRL (anatop_base + 0x10)
> +#define PLL7_CTRL (anatop_base + 0x20)
>
> static void __iomem *anatop_base;
> static void __iomem *ccm_base;
> @@ -148,6 +150,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
> clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
> /* pll6: default 960Mhz */
> clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
> + /* pll7: USB1 PLL at 480MHz */
> + clk[VF610_CLK_PLL7_MAIN] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_main", "fast_clk_sel", PLL7_CTRL, 0x2);
> +
> clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
> clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
> clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
> @@ -160,8 +165,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
> clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
> clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
>
> - clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4));
> - clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4));
> + clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_main", PLL3_CTRL, 6);
> + clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_main", PLL7_CTRL, 6);
> +
> + clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4));
> + clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4));
>
> clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4);
> clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);
> diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
> index a916029..6593757 100644
> --- a/include/dt-bindings/clock/vf610-clock.h
> +++ b/include/dt-bindings/clock/vf610-clock.h
> @@ -164,6 +164,9 @@
> #define VF610_CLK_DMAMUX1 151
> #define VF610_CLK_DMAMUX2 152
> #define VF610_CLK_DMAMUX3 153
> -#define VF610_CLK_END 154
> +#define VF610_CLK_PLL7_MAIN 154
> +#define VF610_CLK_USBPHY0 155
> +#define VF610_CLK_USBPHY1 156
> +#define VF610_CLK_END 157
>
> #endif /* __DT_BINDINGS_CLOCK_VF610_H */
> --
> 2.0.1
>
On Fri, Jul 18, 2014 at 07:01:40PM +0200, Stefan Agner wrote:
> @@ -283,6 +307,10 @@ static const struct of_device_id usbmisc_imx_dt_ids[] = {
> .compatible = "fsl,imx6q-usbmisc",
> .data = &imx6q_usbmisc_ops,
> },
> + {
> + .compatible = "fsl,vf610-usbmisc",
Update Documentation/devicetree/bindings/usb/usbmisc-imx.txt please.
Shawn
> + .data = &vf610_usbmisc_ops,
> + },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, usbmisc_imx_dt_ids);
>-----Original Message-----
>From: Shawn Guo [mailto:[email protected]]
>Sent: Tuesday, July 22, 2014 10:32 AM
>To: Stefan Agner; Lu Jingchang-B35083
>Cc: Chen Peter-B29397; [email protected]; linux-arm-
>[email protected]; [email protected]; linux-
>[email protected]
>Subject: Re: [PATCH 2/6] ARM: imx: clk-vf610: add USBPHY clocks
>
>On Fri, Jul 18, 2014 at 07:01:38PM +0200, Stefan Agner wrote:
>> This commit adds PLL7 which is required for USBPHY1. It also adds the
>> USB PHY and USB Controller clocks and the gates to enable them.
>>
>> Signed-off-by: Stefan Agner <[email protected]>
>
>Jingchang,
>
>Does the patch look good to you?
>
>Shawn
>
For the clk creation, I think it is ok if the functionality has been tested, thanks!
Acked-by: Jingchang Lu <[email protected]>
????{.n?+???????+%?????ݶ??w??{.n?+????{??G?????{ay? ʇڙ?,j??f???h?????????z_??(?階?ݢj"???m??????G????????????&???~???iO???z??v?^?m???? ????????I?
Am 2014-07-22 04:22, schrieb Shawn Guo:
> On Fri, Jul 18, 2014 at 07:01:37PM +0200, Stefan Agner wrote:
>> This adds USB PHY and USB controller nodes. Vybrid SoCs have two
>> independent USB cores which each supports DR (dual role). However,
>> real OTG is not supported since the OTG ID pin is not available.
>>
>> The PHYs are located within the anadig register range, hence we need
>> to change the length of the anadig registers.
>>
>> Signed-off-by: Stefan Agner <[email protected]>
>> ---
>> arch/arm/boot/dts/vf610.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++---
>> 1 file changed, 43 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
>> index 6a6190c..f6c3f02 100644
>> --- a/arch/arm/boot/dts/vf610.dtsi
>> +++ b/arch/arm/boot/dts/vf610.dtsi
>> @@ -25,6 +25,8 @@
>> gpio2 = &gpio3;
>> gpio3 = &gpio4;
>> gpio4 = &gpio5;
>> + usbphy0 = &usbphy0;
>> + usbphy1 = &usbphy1;
>> };
>>
>> cpus {
>> @@ -285,9 +287,25 @@
>> gpio-ranges = <&iomuxc 0 128 7>;
>> };
>>
>> - anatop@40050000 {
>> - compatible = "fsl,vf610-anatop";
>> - reg = <0x40050000 0x1000>;
>> + anatop: anatop@40050000 {
>> + compatible = "fsl,vf610-anatop", "syscon";
>> + reg = <0x40050000 0x400>;
>> + };
>> +
>> + usbphy0: usbphy@40050800 {
>> + compatible = "fsl,vf610-usbphy", "fsl,imx23-usbphy";
>
> Since phy driver will match "fsl,vf610-usbphy" anyway, we do not need
> "fsl,imx23-usbphy" here.
<snip>
>> @@ -309,6 +327,18 @@
>> reg = <0x4006b000 0x1000>;
>> #clock-cells = <1>;
>> };
>> +
>> + usbdev0: usb@40034000 {
>> + compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
>
> It doesn't really make any sense to have "fsl,imx6q-usb" here. The
> following one should be less confusing.
>
> compatible = "fsl,vf610-usb", "fsl,imx27-usb";
I don't quite understand the rule here, when do we drop compatible you
suggest in fsl,imx23-usbphy and when do we keep the "fallback" as we do
for the USB controller?
Documentation/devicetree/bindings/usb/mxs-phy.txt says:
> "fsl,imx23-usbphy" is still a fallback for other strings
And Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt says:
> - compatible: Should be "fsl,imx27-usb"
--
Stefan
On Tue, Jul 22, 2014 at 11:57:31AM +0200, Stefan Agner wrote:
> Am 2014-07-22 04:22, schrieb Shawn Guo:
> > On Fri, Jul 18, 2014 at 07:01:37PM +0200, Stefan Agner wrote:
> >> This adds USB PHY and USB controller nodes. Vybrid SoCs have two
> >> independent USB cores which each supports DR (dual role). However,
> >> real OTG is not supported since the OTG ID pin is not available.
> >>
> >> The PHYs are located within the anadig register range, hence we need
> >> to change the length of the anadig registers.
> >>
> >> Signed-off-by: Stefan Agner <[email protected]>
> >> ---
> >> arch/arm/boot/dts/vf610.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++---
> >> 1 file changed, 43 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
> >> index 6a6190c..f6c3f02 100644
> >> --- a/arch/arm/boot/dts/vf610.dtsi
> >> +++ b/arch/arm/boot/dts/vf610.dtsi
> >> @@ -25,6 +25,8 @@
> >> gpio2 = &gpio3;
> >> gpio3 = &gpio4;
> >> gpio4 = &gpio5;
> >> + usbphy0 = &usbphy0;
> >> + usbphy1 = &usbphy1;
> >> };
> >>
> >> cpus {
> >> @@ -285,9 +287,25 @@
> >> gpio-ranges = <&iomuxc 0 128 7>;
> >> };
> >>
> >> - anatop@40050000 {
> >> - compatible = "fsl,vf610-anatop";
> >> - reg = <0x40050000 0x1000>;
> >> + anatop: anatop@40050000 {
> >> + compatible = "fsl,vf610-anatop", "syscon";
> >> + reg = <0x40050000 0x400>;
> >> + };
> >> +
> >> + usbphy0: usbphy@40050800 {
> >> + compatible = "fsl,vf610-usbphy", "fsl,imx23-usbphy";
> >
> > Since phy driver will match "fsl,vf610-usbphy" anyway, we do not need
> > "fsl,imx23-usbphy" here.
>
> <snip>
>
> >> @@ -309,6 +327,18 @@
> >> reg = <0x4006b000 0x1000>;
> >> #clock-cells = <1>;
> >> };
> >> +
> >> + usbdev0: usb@40034000 {
> >> + compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
> >
> > It doesn't really make any sense to have "fsl,imx6q-usb" here. The
> > following one should be less confusing.
> >
> > compatible = "fsl,vf610-usb", "fsl,imx27-usb";
>
>
> I don't quite understand the rule here, when do we drop compatible you
> suggest in fsl,imx23-usbphy and when do we keep the "fallback" as we do
> for the USB controller?
>
> Documentation/devicetree/bindings/usb/mxs-phy.txt says:
> > "fsl,imx23-usbphy" is still a fallback for other strings
As "fsl,vf610-usbphy" should be added into mxs-phy.txt as a new
compatible string, "fsl,imx23-usbphy" will not be the "fallback" of it,
so there is no point to have "fsl,imx23-usbphy" for vf610 usbphy.
>
> And Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt says:
> > - compatible: Should be "fsl,imx27-usb"
The "fsl,imx27-usb" is the only compatible string defined by the
binding, and vf610 usb will also match it, so we need to have it in the
vf610 usb compatible string. "fsl,vf610-usb" is put there only for
saving DTB update in case someday vf610 usb needs a new programming
model and the binding needs to be extended to have "fsl,vf610-usb" as
a new compatible.
Shawn
Am 2014-07-22 02:13, schrieb Peter Chen:
> On Fri, Jul 18, 2014 at 07:01:36PM +0200, Stefan Agner wrote:
>> This patchset adds USB support for Vybrid VF610 SoC. It extends the
>> clock framework to support the USB PHY cocks, extends the device
>> tree files and adds support for the non-core registers in the
>> usbmisc_imx driver.
>>
>> This patchset needs the eSDHC length fix available in Shawn's
>> for-next branch.
>>
>
> Why it is related to USB patchset?
>
The eSDHC registers are just in front of the USB registers. Due to the
wrong length, the two register areas overlapped, hence the second driver
(and I think it was USB which was loaded second) could not probe
successfully.
>> The whole patchset proved to be working on a Colibri VF61. The
>> first USB controller runs in peripheral mode. I could successfully
>> use RNDIS, however with some stability issues: Suddenly the other
>> side was not reachable anymore and the interface needed to brought
>> down and back up again. I'm still investigating this.
>
> Do you use ubuntu as host distribution? I find ubuntu will lost the
> first connection for usb-ethernet-gadget(usb0) as network interface,
> but once you re-config usb0 again (ifconfig usb0 ip up), it should work
> and will not lose connection any more.
>
I use a Angstrom build, an OpenEmbedded distribution. I restarted the
link using ip link set dev usb0 up/down, this brought the link back in a
pingable state, however even afterwards after some seconds of iperf, the
link hanged again...
--
Stefan