Add following peripherals :
- AO Clock + Reset Controller
- Pinctrl
- UARTs
- SAR-ADC
- USB
- Mali GPU
USB depends on the PCIE clock and missing Reset bindings.
SARADC bindings is merged.
USB bindings has been reviewed, but not merged yet.
Mali GPU bindings are still in review.
Changes since v1 :
- dropped already applied "Add AO Secure node"
- dropped meson-g12a-u200.dts uart_AO change
- fixed includes overall to fix build for each patches
- removed disabled status in dwc2 node
- removed uart_ao_a_c pinctrl
- fixed uart pinctrl node name
Jerome Brunet (3):
arm64: dts: meson: g12a: add pinctrl support controllers
arm64: dts: meson: g12a: add uart_ao_a pinctrl
arm64: dts: meson: g12a: add reset controller
Neil Armstrong (5):
arm64: dts: meson: g12a: Add AO Clock + Reset Controller support
arm64: dts: meson: g12a: Add UART A, B & C nodes and pins
arm64: dts: meson: g12a: Add SAR ADC node
arm64: dts: meson: g12a: Add G12A USB nodes
arm64: dts: meson: g12a: Add mali-g31 gpu node
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 274 ++++++++++++++++++++
1 file changed, 274 insertions(+)
--
2.20.1
Add nodes and properties for the AO Clocks and Resets.
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 31ddf9444b3e..5c0983edf837 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/g12a-clkc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -122,6 +123,23 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
+ rti: sys-ctrl@0 {
+ compatible = "amlogic,meson-gx-ao-sysctrl",
+ "simple-mfd", "syscon";
+ reg = <0x0 0x0 0x0 0x100>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
+
+ clkc_AO: clock-controller {
+ compatible = "amlogic,meson-g12a-aoclkc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&xtal>, <&clkc CLKID_CLK81>;
+ clock-names = "xtal", "mpeg-clk";
+ };
+ };
+
sec_AO: ao-secure@140 {
compatible = "amlogic,meson-gx-ao-secure", "syscon";
reg = <0x0 0x140 0x0 0x140>;
--
2.20.1
This patch adds the ARM Mali G31 GPU node.
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 +++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index ce681aef8d5b..05f0f06f89a5 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -421,6 +421,33 @@
snps,quirk-frame-length-adjustment;
};
};
+
+ mali: gpu@ffe40000 {
+ compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
+ reg = <0x0 0xffe40000 0x0 0x40000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpu", "mmu", "job";
+ clocks = <&clkc CLKID_MALI>;
+ resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; /* Glitch free mux */
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
+ <0>, /* Do Nothing */
+ <&clkc CLKID_MALI_0>;
+ assigned-clock-rates = <0>, /* Do Nothing */
+ <800000000>,
+ <0>; /* Do Nothing */
+ };
};
timer {
--
2.20.1
From: Jerome Brunet <[email protected]>
Add the always on UART pinctrl setting to the g12a soc DT.
Signed-off-by: Jerome Brunet <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index e050737a1b3e..7023c1c0f23c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -179,6 +179,24 @@
#gpio-cells = <2>;
gpio-ranges = <&ao_pinctrl 0 0 15>;
};
+
+ uart_ao_a_pins: uart-a-ao {
+ mux {
+ groups = "uart_ao_a_tx",
+ "uart_ao_a_rx";
+ function = "uart_ao_a";
+ bias-disable;
+ };
+ };
+
+ uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
+ mux {
+ groups = "uart_ao_a_cts",
+ "uart_ao_a_rts";
+ function = "uart_ao_a";
+ bias-disable;
+ };
+ };
};
};
--
2.20.1
From: Jerome Brunet <[email protected]>
Add the reset controller device of g12a SoC family
Signed-off-by: Jerome Brunet <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 7023c1c0f23c..cefd6e27c7a7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -247,6 +247,13 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
+ reset: reset-controller@1004 {
+ compatible = "amlogic,meson-g12a-reset",
+ "amlogic,meson-axg-reset";
+ reg = <0x0 0x1004 0x0 0x9c>;
+ #reset-cells = <1>;
+ };
+
clk_msr: clock-measure@18000 {
compatible = "amlogic,meson-g12a-clk-measure";
reg = <0x0 0x18000 0x0 0x10>;
--
2.20.1
From: Jerome Brunet <[email protected]>
Add the peripheral and always-on pinctrl controllers to the g12a soc.
Signed-off-by: Jerome Brunet <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 42 +++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 5c0983edf837..e050737a1b3e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -92,6 +92,29 @@
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
+
+ periphs_pinctrl: pinctrl@40 {
+ compatible = "amlogic,meson-g12a-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank@40 {
+ reg = <0x0 0x40 0x0 0x4c>,
+ <0x0 0xe8 0x0 0x18>,
+ <0x0 0x120 0x0 0x18>,
+ <0x0 0x2c0 0x0 0x40>,
+ <0x0 0x340 0x0 0x1c>;
+ reg-names = "gpio",
+ "pull",
+ "pull-enable",
+ "mux",
+ "ds";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&periphs_pinctrl 0 0 86>;
+ };
+ };
};
hiu: bus@3c000 {
@@ -138,6 +161,25 @@
clocks = <&xtal>, <&clkc CLKID_CLK81>;
clock-names = "xtal", "mpeg-clk";
};
+
+ ao_pinctrl: pinctrl@14 {
+ compatible = "amlogic,meson-g12a-aobus-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio_ao: bank@14 {
+ reg = <0x0 0x14 0x0 0x8>,
+ <0x0 0x1c 0x0 0x8>,
+ <0x0 0x24 0x0 0x14>;
+ reg-names = "mux",
+ "ds",
+ "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&ao_pinctrl 0 0 15>;
+ };
+ };
};
sec_AO: ao-secure@140 {
--
2.20.1
This patch adds the nodes for the USB Complex found in the Amlogic
G12A SoC.
It includes the :
- 2 USB2 PHYs
- 1 USB3 + PCIE Combo PHY
- the USB Glue with it's DWC2 and DWC3 sub-nodes
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 75 +++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index a99c13ee724a..ce681aef8d5b 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -3,11 +3,13 @@
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
*/
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/g12a-clkc.h>
#include <dt-bindings/clock/g12a-aoclkc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
/ {
compatible = "amlogic,g12a";
@@ -163,6 +165,26 @@
};
};
+ usb2_phy0: phy@36000 {
+ compatible = "amlogic,g12a-usb2-phy";
+ reg = <0x0 0x36000 0x0 0x2000>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ resets = <&reset RESET_USB_PHY20>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
+
+ usb2_phy1: phy@3a000 {
+ compatible = "amlogic,g12a-usb2-phy";
+ reg = <0x0 0x3a000 0x0 0x2000>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ resets = <&reset RESET_USB_PHY21>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
+
hiu: bus@3c000 {
compatible = "simple-bus";
reg = <0x0 0x3c000 0x0 0x1400>;
@@ -183,6 +205,18 @@
};
};
};
+
+ usb3_pcie_phy: phy@46000 {
+ compatible = "amlogic,g12a-usb3-pcie-phy";
+ reg = <0x0 0x46000 0x0 0x2000>;
+ clocks = <&clkc CLKID_PCIE_PLL>;
+ clock-names = "ref_clk";
+ resets = <&reset RESET_PCIE_PHY>;
+ reset-names = "phy";
+ assigned-clocks = <&clkc CLKID_PCIE_PLL>;
+ assigned-clock-rates = <100000000>;
+ #phy-cells = <1>;
+ };
};
aobus: bus@ff800000 {
@@ -346,6 +380,47 @@
status = "disabled";
};
};
+
+ usb: usb@ffe09000 {
+ status = "disabled";
+ compatible = "amlogic,meson-g12a-usb-ctrl";
+ reg = <0x0 0xffe09000 0x0 0xa0>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&clkc CLKID_USB>;
+ resets = <&reset RESET_USB>;
+
+ dr_mode = "otg";
+
+ phys = <&usb2_phy0>, <&usb2_phy1>,
+ <&usb3_pcie_phy PHY_TYPE_USB3>;
+ phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
+
+ dwc2: usb@ff400000 {
+ compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
+ reg = <0x0 0xff400000 0x0 0x40000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+ clock-names = "ddr";
+ phys = <&usb2_phy1>;
+ dr_mode = "peripheral";
+ g-rx-fifo-size = <192>;
+ g-np-tx-fifo-size = <128>;
+ g-tx-fifo-size = <128 128 16 16 16>;
+ };
+
+ dwc3: usb@ff500000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff500000 0x0 0x100000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,dis_u2_susphy_quirk;
+ snps,quirk-frame-length-adjustment;
+ };
+ };
};
timer {
--
2.20.1
This patch adds the 3 UART nodes in the EE power domain with the corresponding
pinctrl nodes.
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 72 +++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index cefd6e27c7a7..992751024366 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -114,6 +114,51 @@
#gpio-cells = <2>;
gpio-ranges = <&periphs_pinctrl 0 0 86>;
};
+
+ uart_a_pins: uart-a {
+ mux {
+ groups = "uart_a_tx",
+ "uart_a_rx";
+ function = "uart_a";
+ bias-disable;
+ };
+ };
+
+ uart_a_cts_rts_pins: uart-a-cts-rts {
+ mux {
+ groups = "uart_a_cts",
+ "uart_a_rts";
+ function = "uart_a";
+ bias-disable;
+ };
+ };
+
+ uart_b_pins: uart-b {
+ mux {
+ groups = "uart_b_tx",
+ "uart_b_rx";
+ function = "uart_b";
+ bias-disable;
+ };
+ };
+
+ uart_c_pins: uart-c {
+ mux {
+ groups = "uart_c_tx",
+ "uart_c_rx";
+ function = "uart_c";
+ bias-disable;
+ };
+ };
+
+ uart_c_cts_rts_pins: uart-c-cts-rts {
+ mux {
+ groups = "uart_c_cts",
+ "uart_c_rts";
+ function = "uart_c";
+ bias-disable;
+ };
+ };
};
};
@@ -258,6 +303,33 @@
compatible = "amlogic,meson-g12a-clk-measure";
reg = <0x0 0x18000 0x0 0x10>;
};
+
+ uart_C: serial@22000 {
+ compatible = "amlogic,meson-gx-uart";
+ reg = <0x0 0x22000 0x0 0x18>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
+
+ uart_B: serial@23000 {
+ compatible = "amlogic,meson-gx-uart";
+ reg = <0x0 0x23000 0x0 0x18>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
+
+ uart_A: serial@24000 {
+ compatible = "amlogic,meson-gx-uart";
+ reg = <0x0 0x24000 0x0 0x18>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ status = "disabled";
+ };
};
};
--
2.20.1
This patch adds the SAR ADC controller node.
Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 992751024366..a99c13ee724a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/g12a-clkc.h>
+#include <dt-bindings/clock/g12a-aoclkc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -270,6 +271,20 @@
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ saradc: adc@9000 {
+ compatible = "amlogic,meson-g12a-saradc",
+ "amlogic,meson-saradc";
+ reg = <0x0 0x9000 0x0 0x48>;
+ #io-channel-cells = <1>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>,
+ <&clkc_AO CLKID_AO_SAR_ADC>,
+ <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
+ <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
+ clock-names = "clkin", "core", "adc_clk", "adc_sel";
+ status = "disabled";
+ };
};
gic: interrupt-controller@ffc01000 {
--
2.20.1
On Mon, Mar 18, 2019 at 10:59 AM Neil Armstrong <[email protected]> wrote:
>
> From: Jerome Brunet <[email protected]>
>
> Add the always on UART pinctrl setting to the g12a soc DT.
>
> Signed-off-by: Jerome Brunet <[email protected]>
> Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
On Mon, Mar 18, 2019 at 11:00 AM Neil Armstrong <[email protected]> wrote:
>
> This patch adds the nodes for the USB Complex found in the Amlogic
> G12A SoC.
>
> It includes the :
> - 2 USB2 PHYs
> - 1 USB3 + PCIE Combo PHY
> - the USB Glue with it's DWC2 and DWC3 sub-nodes
>
> Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
Hi Neil,
On Mon, Mar 18, 2019 at 10:59 AM Neil Armstrong <[email protected]> wrote:
>
> Add nodes and properties for the AO Clocks and Resets.
>
> Signed-off-by: Neil Armstrong <[email protected]>
> Signed-off-by: Jerome Brunet <[email protected]>
> ---
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> index 31ddf9444b3e..5c0983edf837 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> @@ -4,6 +4,7 @@
> */
>
> #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/clock/g12a-clkc.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> @@ -122,6 +123,23 @@
> #size-cells = <2>;
> ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
>
> + rti: sys-ctrl@0 {
> + compatible = "amlogic,meson-gx-ao-sysctrl",
> + "simple-mfd", "syscon";
> + reg = <0x0 0x0 0x0 0x100>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
sorry for noticing this only very late: I missed the #address-cells,
#size-cells and ranges property in my last review
do you have any change queued which requires this?
my understanding is that the drivers for all RTI children should use
the register offsets relative to the RTI start address. In that case
the child nodes neither have a unit-address nor a reg property, making
the last three properties unnecessary.
Regards
Martin
On Mon, Mar 18, 2019 at 11:00 AM Neil Armstrong <[email protected]> wrote:
>
> This patch adds the 3 UART nodes in the EE power domain with the corresponding
> pinctrl nodes.
>
> Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
On 18/03/2019 21:02, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Mon, Mar 18, 2019 at 10:59 AM Neil Armstrong <[email protected]> wrote:
>>
>> Add nodes and properties for the AO Clocks and Resets.
>>
>> Signed-off-by: Neil Armstrong <[email protected]>
>> Signed-off-by: Jerome Brunet <[email protected]>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> index 31ddf9444b3e..5c0983edf837 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> @@ -4,6 +4,7 @@
>> */
>>
>> #include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/clock/g12a-clkc.h>
>> #include <dt-bindings/interrupt-controller/irq.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>
>> @@ -122,6 +123,23 @@
>> #size-cells = <2>;
>> ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
>>
>> + rti: sys-ctrl@0 {
>> + compatible = "amlogic,meson-gx-ao-sysctrl",
>> + "simple-mfd", "syscon";
>> + reg = <0x0 0x0 0x0 0x100>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
> sorry for noticing this only very late: I missed the #address-cells,
> #size-cells and ranges property in my last review
> do you have any change queued which requires this?
> my understanding is that the drivers for all RTI children should use
> the register offsets relative to the RTI start address. In that case
> the child nodes neither have a unit-address nor a reg property, making
> the last three properties unnecessary.
We need the address-cells/size-cells and `ranges;` to satisfy the need
for the gpio subnode of the pinctrl node.
For GX, we didn't add the pinctrl in the sysctrl_AO subnode, but we should
overwise we have overlapping.
Neil
>
>
> Regards
> Martin
>
Hi Neil,
On Tue, Mar 19, 2019 at 9:47 AM Neil Armstrong <[email protected]> wrote:
>
> On 18/03/2019 21:02, Martin Blumenstingl wrote:
> > Hi Neil,
> >
> > On Mon, Mar 18, 2019 at 10:59 AM Neil Armstrong <[email protected]> wrote:
> >>
> >> Add nodes and properties for the AO Clocks and Resets.
> >>
> >> Signed-off-by: Neil Armstrong <[email protected]>
> >> Signed-off-by: Jerome Brunet <[email protected]>
> >> ---
> >> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 18 ++++++++++++++++++
> >> 1 file changed, 18 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> >> index 31ddf9444b3e..5c0983edf837 100644
> >> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> >> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> >> @@ -4,6 +4,7 @@
> >> */
> >>
> >> #include <dt-bindings/gpio/gpio.h>
> >> +#include <dt-bindings/clock/g12a-clkc.h>
> >> #include <dt-bindings/interrupt-controller/irq.h>
> >> #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>
> >> @@ -122,6 +123,23 @@
> >> #size-cells = <2>;
> >> ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
> >>
> >> + rti: sys-ctrl@0 {
> >> + compatible = "amlogic,meson-gx-ao-sysctrl",
> >> + "simple-mfd", "syscon";
> >> + reg = <0x0 0x0 0x0 0x100>;
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> + ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
> > sorry for noticing this only very late: I missed the #address-cells,
> > #size-cells and ranges property in my last review
> > do you have any change queued which requires this?
> > my understanding is that the drivers for all RTI children should use
> > the register offsets relative to the RTI start address. In that case
> > the child nodes neither have a unit-address nor a reg property, making
> > the last three properties unnecessary.
>
> We need the address-cells/size-cells and `ranges;` to satisfy the need
> for the gpio subnode of the pinctrl node.
>
> For GX, we didn't add the pinctrl in the sysctrl_AO subnode, but we should
> overwise we have overlapping.
ah, I see - thank you for the explanation.
setting #address-cells and #size-cells will probably yield dtc
warnings for the children without unit-address / reg property.
also the pinctrl driver and the syscon driver would still ioremap
overlapping memory regions (syscon: the full 0x100 range, the pinctrl
driver various 4 and 8 byte registers) because both are ioremap'ing
their register space.
but indeed, the overlapping dt nodes are solved with this approach.
Rob acked a binding for the Lantiq XWAY SoC's with a simple-mfd /
syscon as parent and children with a reg property. The parent node
defines a reg and ranges property, but neither #size-cells nor
#address-cells. the binding is documented here: [0]
The requirements seem similar to our pinctrl needs. We could end up
with only a single syscon and no overlapping ioremap for the pinctrl
driver and we may not even have to change the binding.
with this mail I want to start a discussion about the bindings of the
AO pin controller (similar to how we re-considered the binding of the
AO clock controller in the past). at the same time I'm not saying that
we immediately have to change it.
Regards
Martin
[0] https://www.kernel.org/doc/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
Neil Armstrong <[email protected]> writes:
> Add following peripherals :
> - AO Clock + Reset Controller
> - Pinctrl
> - UARTs
> - SAR-ADC
> - USB
> - Mali GPU
>
> USB depends on the PCIE clock and missing Reset bindings.
I left this one out for now.
> SARADC bindings is merged.
And this one, as it depends on new clock IDs. I need a stable tag for
those.
> USB bindings has been reviewed, but not merged yet.
Also depends on a reset patch for the IDs used. This was just merged by
Phillip, but I need a stable tag before I can merg this.
> Mali GPU bindings are still in review.
I've left the Mali nodes out for now also.
IOW, I queued patches 1-5/8 (branch: v5.2/dt64), and will wait on the
others until their dependencies are cleared up and/or I have stable tags
to use.
In the future, please note all the out-of-tree dependencies for the
series.
Thanks,
Kevin
Le 23/03/2019 00:05, Kevin Hilman a ?crit :
> Neil Armstrong <[email protected]> writes:
>
>> Add following peripherals :
>> - AO Clock + Reset Controller
>> - Pinctrl
>> - UARTs
>> - SAR-ADC
>> - USB
>> - Mali GPU
>>
>> USB depends on the PCIE clock and missing Reset bindings.
>
> I left this one out for now.
>
>> SARADC bindings is merged.
>
> And this one, as it depends on new clock IDs. I need a stable tag for
> those.
>
>> USB bindings has been reviewed, but not merged yet.
>
> Also depends on a reset patch for the IDs used. This was just merged by
> Phillip, but I need a stable tag before I can merg this.
>
>> Mali GPU bindings are still in review.
>
> I've left the Mali nodes out for now also.
>
> IOW, I queued patches 1-5/8 (branch: v5.2/dt64), and will wait on the
> others until their dependencies are cleared up and/or I have stable tags
> to use.
Ok, Thanks
>
> In the future, please note all the out-of-tree dependencies for the
> series.
Sure, I'll add more dependencies details on the v3 cover letter.
Neil
>
> Thanks,
>
> Kevin
>