This patch series have some unrelated fixes related
to clocksource, dt-bindings and isa strings.
I combined them into series as most of them are
prerequisite for kvm patch series.
Changes from v1->v2:
1. Dropped the case-insensitive support patch and added a dt-bindings
update patch.
2. Added a export symbol patch.
Anup Patel (1):
RISC-V: Add riscv_isa reprensenting ISA features common across CPUs
Atish Patra (4):
RISC-V: Remove per cpu clocksource
RISC-V: Fix unsupported isa string info.
RISC-V: Export few kernel symbols
dt-bindings: Update the isa string description
.../devicetree/bindings/riscv/cpus.yaml | 6 ++-
arch/riscv/include/asm/hwcap.h | 25 ++++++++++
arch/riscv/kernel/cpu.c | 47 +++++++++++++++----
arch/riscv/kernel/cpufeature.c | 41 ++++++++++++++--
arch/riscv/kernel/smp.c | 2 +-
arch/riscv/kernel/time.c | 1 +
drivers/clocksource/timer-riscv.c | 6 +--
7 files changed, 109 insertions(+), 19 deletions(-)
--
2.21.0
Export few symbols used by kvm module. Without this, kvm can not
be compiled as a module.
Signed-off-by: Atish Patra <[email protected]>
---
arch/riscv/kernel/smp.c | 2 +-
arch/riscv/kernel/time.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 5a9834503a2f..402979f575de 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -193,4 +193,4 @@ void smp_send_reschedule(int cpu)
{
send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
}
-
+EXPORT_SYMBOL_GPL(smp_send_reschedule);
diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c
index 541a2b885814..9dd1f2e64db1 100644
--- a/arch/riscv/kernel/time.c
+++ b/arch/riscv/kernel/time.c
@@ -9,6 +9,7 @@
#include <asm/sbi.h>
unsigned long riscv_timebase;
+EXPORT_SYMBOL_GPL(riscv_timebase);
void __init time_init(void)
{
--
2.21.0
The yaml documentation description of isa strings section doesn't
specify anything about the case sensitiveness of the isa strings.
The RISC-V specification clearly specifies it to be case insensitive.
However, Linux kernel supports only lower case isa strings.
Update the yaml documentation accordingly to avoid any confusion.
Signed-off-by: Atish Patra <[email protected]>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c899111aa5e3..e22a2b7ebafa 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -46,10 +46,14 @@ properties:
- rv64imafdc
description:
Identifies the specific RISC-V instruction set architecture
- supported by the hart. These are documented in the RISC-V
+ supported by the hart. These are documented in the RISC-V
User-Level ISA document, available from
https://riscv.org/specifications/
+ Linux kernel only supports lower case isa strings. Thus,
+ isa strings must be specified in lower case in device tree
+ as well.
+
timebase-frequency:
type: integer
minimum: 1
--
2.21.0
Currently, kernel prints a info warning if any of the extensions
from "mafdcsu" is missing in device tree. This is not entirely
correct as Linux can boot with "f or d" extensions if kernel is
configured accordingly. Moreover, it will continue to print the
info string for future extensions such as hypervisor as well which
is misleading. /proc/cpuinfo also doesn't print any other extensions
except "mafdcsu".
Make sure that info log is only printed only if kernel is configured
to have any mandatory extensions but device tree doesn't describe it.
All the extensions present in device tree and follow the order
described in the RISC-V specification (except 'S') are printed via
/proc/cpuinfo always.
Signed-off-by: Atish Patra <[email protected]>
---
arch/riscv/kernel/cpu.c | 47 ++++++++++++++++++++++++++++++++---------
1 file changed, 37 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 7da3c6a93abd..9b1d4550fbe6 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -7,6 +7,7 @@
#include <linux/seq_file.h>
#include <linux/of.h>
#include <asm/smp.h>
+#include <asm/hwcap.h>
/*
* Returns the hart ID of the given device tree node, or -ENODEV if the node
@@ -46,11 +47,14 @@ int riscv_of_processor_hartid(struct device_node *node)
#ifdef CONFIG_PROC_FS
-static void print_isa(struct seq_file *f, const char *orig_isa)
+static void print_isa(struct seq_file *f, const char *orig_isa,
+ unsigned long cpuid)
{
- static const char *ext = "mafdcsu";
+ static const char *mandatory_ext = "mafdcsu";
const char *isa = orig_isa;
const char *e;
+ char unsupported_isa[26] = {0};
+ int index = 0;
/*
* Linux doesn't support rv32e or rv128i, and we only support booting
@@ -70,27 +74,50 @@ static void print_isa(struct seq_file *f, const char *orig_isa)
isa += 5;
/*
- * Check the rest of the ISA string for valid extensions, printing those
- * we find. RISC-V ISA strings define an order, so we only print the
+ * RISC-V ISA strings define an order, so we only print all the
* extension bits when they're in order. Hide the supervisor (S)
* extension from userspace as it's not accessible from there.
+ * Throw a warning only if any mandatory extensions are not available
+ * and kernel is configured to have that mandatory extensions.
*/
- for (e = ext; *e != '\0'; ++e) {
- if (isa[0] == e[0]) {
+ for (e = mandatory_ext; *e != '\0'; ++e) {
+ if (isa[0] != e[0]) {
+#if defined(CONFIG_ISA_RISCV_C)
+ if (isa[0] == 'c')
+ continue;
+#endif
+#if defined(CONFIG_FP)
+ if ((isa[0] == 'f') || (isa[0] == 'd'))
+ continue;
+#endif
+ unsupported_isa[index] = e[0];
+ index++;
+ }
+ /* Only write if part of isa string */
+ if (isa[0] != '\0') {
if (isa[0] != 's')
seq_write(f, isa, 1);
-
isa++;
}
}
+ if (isa[0] != '\0') {
+ /* Add remainging isa strings */
+ for (e = isa; *e != '\0'; ++e) {
+#if !defined(CONFIG_VIRTUALIZATION)
+ if (e[0] != 'h')
+#endif
+ seq_write(f, e, 1);
+ }
+ }
seq_puts(f, "\n");
/*
* If we were given an unsupported ISA in the device tree then print
* a bit of info describing what went wrong.
*/
- if (isa[0] != '\0')
- pr_info("unsupported ISA \"%s\" in device tree\n", orig_isa);
+ if (unsupported_isa[0])
+ pr_info("unsupported ISA extensions \"%s\" in device tree for cpu [%ld]\n",
+ unsupported_isa, cpuid);
}
static void print_mmu(struct seq_file *f, const char *mmu_type)
@@ -134,7 +161,7 @@ static int c_show(struct seq_file *m, void *v)
seq_printf(m, "processor\t: %lu\n", cpu_id);
seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
if (!of_property_read_string(node, "riscv,isa", &isa))
- print_isa(m, isa);
+ print_isa(m, isa, cpu_id);
if (!of_property_read_string(node, "mmu-type", &mmu))
print_mmu(m, mmu);
if (!of_property_read_string(node, "compatible", &compat)
--
2.21.0
From: Anup Patel <[email protected]>
This patch adds riscv_isa integer to represent ISA features common
across all CPUs. The riscv_isa is not same as elf_hwcap because
elf_hwcap will only have ISA features relevant for user-space apps
whereas riscv_isa will have ISA features relevant to both kernel
and user-space apps.
One of the use case is KVM hypervisor where riscv_isa will be used
to do following operations:
1. Check whether hypervisor extension is available
2. Find ISA features that need to be virtualized (e.g. floating
point support, vector extension, etc.)
Signed-off-by: Anup Patel <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
---
arch/riscv/include/asm/hwcap.h | 25 +++++++++++++++++++++
arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++---
2 files changed, 63 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 7ecb7c6a57b1..e069f60ad5d2 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -22,5 +22,30 @@ enum {
};
extern unsigned long elf_hwcap;
+
+#define RISCV_ISA_EXT_A (1UL << ('A' - 'A'))
+#define RISCV_ISA_EXT_a RISCV_ISA_EXT_A
+#define RISCV_ISA_EXT_C (1UL << ('C' - 'A'))
+#define RISCV_ISA_EXT_c RISCV_ISA_EXT_C
+#define RISCV_ISA_EXT_D (1UL << ('D' - 'A'))
+#define RISCV_ISA_EXT_d RISCV_ISA_EXT_D
+#define RISCV_ISA_EXT_F (1UL << ('F' - 'A'))
+#define RISCV_ISA_EXT_f RISCV_ISA_EXT_F
+#define RISCV_ISA_EXT_H (1UL << ('H' - 'A'))
+#define RISCV_ISA_EXT_h RISCV_ISA_EXT_H
+#define RISCV_ISA_EXT_I (1UL << ('I' - 'A'))
+#define RISCV_ISA_EXT_i RISCV_ISA_EXT_I
+#define RISCV_ISA_EXT_M (1UL << ('M' - 'A'))
+#define RISCV_ISA_EXT_m RISCV_ISA_EXT_M
+#define RISCV_ISA_EXT_S (1UL << ('S' - 'A'))
+#define RISCV_ISA_EXT_s RISCV_ISA_EXT_S
+#define RISCV_ISA_EXT_U (1UL << ('U' - 'A'))
+#define RISCV_ISA_EXT_u RISCV_ISA_EXT_U
+
+extern unsigned long riscv_isa;
+
+#define riscv_isa_extension_available(ext_char) \
+ (riscv_isa & RISCV_ISA_EXT_##ext_char)
+
#endif
#endif
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index b1ade9a49347..177529d48d87 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -12,6 +12,9 @@
#include <asm/smp.h>
unsigned long elf_hwcap __read_mostly;
+unsigned long riscv_isa __read_mostly;
+EXPORT_SYMBOL_GPL(riscv_isa);
+
#ifdef CONFIG_FPU
bool has_fpu __read_mostly;
#endif
@@ -20,7 +23,8 @@ void riscv_fill_hwcap(void)
{
struct device_node *node;
const char *isa;
- size_t i;
+ char print_str[BITS_PER_LONG+1];
+ size_t i, j, isa_len;
static unsigned long isa2hwcap[256] = {0};
isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I;
@@ -31,9 +35,11 @@ void riscv_fill_hwcap(void)
isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C;
elf_hwcap = 0;
+ riscv_isa = 0;
for_each_of_cpu_node(node) {
unsigned long this_hwcap = 0;
+ unsigned long this_isa = 0;
if (riscv_of_processor_hartid(node) < 0)
continue;
@@ -43,8 +49,22 @@ void riscv_fill_hwcap(void)
continue;
}
- for (i = 0; i < strlen(isa); ++i)
+ i = 0;
+ isa_len = strlen(isa);
+#if defined(CONFIG_32BIT)
+ if (strncasecmp(isa, "rv32", 4) != 0)
+ i += 4;
+#elif defined(CONFIG_64BIT)
+ if (strncasecmp(isa, "rv64", 4) != 0)
+ i += 4;
+#endif
+ for (; i < isa_len; ++i) {
this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
+ if ('a' <= isa[i] && isa[i] <= 'z')
+ this_isa |= (1UL << (isa[i] - 'a'));
+ if ('A' <= isa[i] && isa[i] <= 'Z')
+ this_isa |= (1UL << (isa[i] - 'A'));
+ }
/*
* All "okay" hart should have same isa. Set HWCAP based on
@@ -55,6 +75,11 @@ void riscv_fill_hwcap(void)
elf_hwcap &= this_hwcap;
else
elf_hwcap = this_hwcap;
+
+ if (riscv_isa)
+ riscv_isa &= this_isa;
+ else
+ riscv_isa = this_isa;
}
/* We don't support systems with F but without D, so mask those out
@@ -64,7 +89,17 @@ void riscv_fill_hwcap(void)
elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
}
- pr_info("elf_hwcap is 0x%lx\n", elf_hwcap);
+ memset(print_str, 0, sizeof(print_str));
+ for (i = 0, j = 0; i < BITS_PER_LONG; i++)
+ if (riscv_isa & (1UL << i))
+ print_str[j++] = (char)('A' + i);
+ pr_info("riscv: ISA extensions %s\n", print_str);
+
+ memset(print_str, 0, sizeof(print_str));
+ for (i = 0, j = 0; i < BITS_PER_LONG; i++)
+ if (elf_hwcap & (1UL << i))
+ print_str[j++] = (char)('A' + i);
+ pr_info("riscv: ELF capabilities %s\n", print_str);
#ifdef CONFIG_FPU
if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D))
--
2.21.0
On Tue, 30 Jul 2019, Atish Patra wrote:
> From: Anup Patel <[email protected]>
>
> This patch adds riscv_isa integer to represent ISA features common
> across all CPUs. The riscv_isa is not same as elf_hwcap because
> elf_hwcap will only have ISA features relevant for user-space apps
> whereas riscv_isa will have ISA features relevant to both kernel
> and user-space apps.
>
> One of the use case is KVM hypervisor where riscv_isa will be used
> to do following operations:
>
> 1. Check whether hypervisor extension is available
> 2. Find ISA features that need to be virtualized (e.g. floating
> point support, vector extension, etc.)
>
> Signed-off-by: Anup Patel <[email protected]>
> Signed-off-by: Atish Patra <[email protected]>
> ---
> arch/riscv/include/asm/hwcap.h | 25 +++++++++++++++++++++
> arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++---
> 2 files changed, 63 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 7ecb7c6a57b1..e069f60ad5d2 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -22,5 +22,30 @@ enum {
> };
>
> extern unsigned long elf_hwcap;
> +
> +#define RISCV_ISA_EXT_A (1UL << ('A' - 'A'))
Are these uppercase variants still needed if we define the ISA string to
be all lowercase, per our recent discussion?
> +#define RISCV_ISA_EXT_a RISCV_ISA_EXT_A
> +#define RISCV_ISA_EXT_C (1UL << ('C' - 'A'))
> +#define RISCV_ISA_EXT_c RISCV_ISA_EXT_C
> +#define RISCV_ISA_EXT_D (1UL << ('D' - 'A'))
> +#define RISCV_ISA_EXT_d RISCV_ISA_EXT_D
> +#define RISCV_ISA_EXT_F (1UL << ('F' - 'A'))
> +#define RISCV_ISA_EXT_f RISCV_ISA_EXT_F
> +#define RISCV_ISA_EXT_H (1UL << ('H' - 'A'))
> +#define RISCV_ISA_EXT_h RISCV_ISA_EXT_H
> +#define RISCV_ISA_EXT_I (1UL << ('I' - 'A'))
> +#define RISCV_ISA_EXT_i RISCV_ISA_EXT_I
> +#define RISCV_ISA_EXT_M (1UL << ('M' - 'A'))
> +#define RISCV_ISA_EXT_m RISCV_ISA_EXT_M
> +#define RISCV_ISA_EXT_S (1UL << ('S' - 'A'))
> +#define RISCV_ISA_EXT_s RISCV_ISA_EXT_S
> +#define RISCV_ISA_EXT_U (1UL << ('U' - 'A'))
> +#define RISCV_ISA_EXT_u RISCV_ISA_EXT_U
> +
> +extern unsigned long riscv_isa;
> +
> +#define riscv_isa_extension_available(ext_char) \
> + (riscv_isa & RISCV_ISA_EXT_##ext_char)
> +
> #endif
> #endif
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index b1ade9a49347..177529d48d87 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
[ ... ]
> @@ -43,8 +49,22 @@ void riscv_fill_hwcap(void)
> continue;
> }
>
> - for (i = 0; i < strlen(isa); ++i)
> + i = 0;
> + isa_len = strlen(isa);
> +#if defined(CONFIG_32BIT)
> + if (strncasecmp(isa, "rv32", 4) != 0)
strcmp()?
> + i += 4;
> +#elif defined(CONFIG_64BIT)
> + if (strncasecmp(isa, "rv64", 4) != 0)
And again here?
> + i += 4;
> +#endif
> + for (; i < isa_len; ++i) {
> this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
> + if ('a' <= isa[i] && isa[i] <= 'z')
> + this_isa |= (1UL << (isa[i] - 'a'));
> + if ('A' <= isa[i] && isa[i] <= 'Z')
> + this_isa |= (1UL << (isa[i] - 'A'));
Are these uppercase variants still needed?
- Paul
On Tue, 30 Jul 2019, Atish Patra wrote:
> The yaml documentation description of isa strings section doesn't
> specify anything about the case sensitiveness of the isa strings.
> The RISC-V specification clearly specifies it to be case insensitive.
> However, Linux kernel supports only lower case isa strings.
The DT binding documentation specifies an interface. As such the binding
isn't determined by any particular piece of software. So justifying the
binding update by referring to what the Linux kernel currently supports
isn't that relevant. If you still really believe that software should be
required to handle mixed-case DT ISA strings, the right answer would be to
change the software, as your original patches proposed. The way you've
written this patch description, it sounds like you still don't agree with
the conclusion that a strictly lowercase string is a good approach.
If I've misunderstood your intent here, and you do think that specifying
an all lowercase string is sufficient, then instead of the patch
description above, how about something like:
"Since the RISC-V specification states that ISA description strings are
case-insensitive, there's no functional difference between mixed-case,
upper-case, and lower-case ISA strings. Thus, to simplify parsing,
specify that the letters present of riscv,isa must be all lowercase."
That way it's clear that, per the RISC-V specification, there's no
functional difference associated with case.
However, if what you're saying is that you still don't like this outcome,
let me know and I'll write the patch myself. That way you don't have to
have your name associated with a change that you don't believe in.
> Update the yaml documentation accordingly to avoid any confusion.
>
> Signed-off-by: Atish Patra <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index c899111aa5e3..e22a2b7ebafa 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -46,10 +46,14 @@ properties:
> - rv64imafdc
> description:
> Identifies the specific RISC-V instruction set architecture
> - supported by the hart. These are documented in the RISC-V
> + supported by the hart. These are documented in the RISC-V
> User-Level ISA document, available from
> https://riscv.org/specifications/
>
> + Linux kernel only supports lower case isa strings. Thus,
In the past, the DT maintainers have pushed back against explicitly
mentioning the Linux kernel in binding documentation, since the DT
bindings define an interface that's independent of the underlying software
implementation. How about just stating something like "Letters in the
riscv,isa string must be all lowercase" ?
> + isa strings must be specified in lower case in device tree
> + as well.
> +
- Paul
On 7/30/19, 9:23 PM, "Paul Walmsley" <[email protected]> wrote:
On Tue, 30 Jul 2019, Atish Patra wrote:
> From: Anup Patel <[email protected]>
>
> This patch adds riscv_isa integer to represent ISA features common
> across all CPUs. The riscv_isa is not same as elf_hwcap because
> elf_hwcap will only have ISA features relevant for user-space apps
> whereas riscv_isa will have ISA features relevant to both kernel
> and user-space apps.
>
> One of the use case is KVM hypervisor where riscv_isa will be used
> to do following operations:
>
> 1. Check whether hypervisor extension is available
> 2. Find ISA features that need to be virtualized (e.g. floating
> point support, vector extension, etc.)
>
> Signed-off-by: Anup Patel <[email protected]>
> Signed-off-by: Atish Patra <[email protected]>
> ---
> arch/riscv/include/asm/hwcap.h | 25 +++++++++++++++++++++
> arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++---
> 2 files changed, 63 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 7ecb7c6a57b1..e069f60ad5d2 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -22,5 +22,30 @@ enum {
> };
>
> extern unsigned long elf_hwcap;
> +
> +#define RISCV_ISA_EXT_A (1UL << ('A' - 'A'))
Are these uppercase variants still needed if we define the ISA string to
be all lowercase, per our recent discussion?
Argh. Sorry. We have been carrying this patch so long that I completely forgot about the
case sensitive usage here.
> +#define RISCV_ISA_EXT_a RISCV_ISA_EXT_A
> +#define RISCV_ISA_EXT_C (1UL << ('C' - 'A'))
> +#define RISCV_ISA_EXT_c RISCV_ISA_EXT_C
> +#define RISCV_ISA_EXT_D (1UL << ('D' - 'A'))
> +#define RISCV_ISA_EXT_d RISCV_ISA_EXT_D
> +#define RISCV_ISA_EXT_F (1UL << ('F' - 'A'))
> +#define RISCV_ISA_EXT_f RISCV_ISA_EXT_F
> +#define RISCV_ISA_EXT_H (1UL << ('H' - 'A'))
> +#define RISCV_ISA_EXT_h RISCV_ISA_EXT_H
> +#define RISCV_ISA_EXT_I (1UL << ('I' - 'A'))
> +#define RISCV_ISA_EXT_i RISCV_ISA_EXT_I
> +#define RISCV_ISA_EXT_M (1UL << ('M' - 'A'))
> +#define RISCV_ISA_EXT_m RISCV_ISA_EXT_M
> +#define RISCV_ISA_EXT_S (1UL << ('S' - 'A'))
> +#define RISCV_ISA_EXT_s RISCV_ISA_EXT_S
> +#define RISCV_ISA_EXT_U (1UL << ('U' - 'A'))
> +#define RISCV_ISA_EXT_u RISCV_ISA_EXT_U
> +
> +extern unsigned long riscv_isa;
> +
> +#define riscv_isa_extension_available(ext_char) \
> + (riscv_isa & RISCV_ISA_EXT_##ext_char)
> +
> #endif
> #endif
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index b1ade9a49347..177529d48d87 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
[ ... ]
> @@ -43,8 +49,22 @@ void riscv_fill_hwcap(void)
> continue;
> }
>
> - for (i = 0; i < strlen(isa); ++i)
> + i = 0;
> + isa_len = strlen(isa);
> +#if defined(CONFIG_32BIT)
> + if (strncasecmp(isa, "rv32", 4) != 0)
strcmp()?
> + i += 4;
> +#elif defined(CONFIG_64BIT)
> + if (strncasecmp(isa, "rv64", 4) != 0)
And again here?
> + i += 4;
> +#endif
> + for (; i < isa_len; ++i) {
> this_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
> + if ('a' <= isa[i] && isa[i] <= 'z')
> + this_isa |= (1UL << (isa[i] - 'a'));
> + if ('A' <= isa[i] && isa[i] <= 'Z')
> + this_isa |= (1UL << (isa[i] - 'A'));
Are these uppercase variants still needed?
Nope. Same as above comment. Apologies for forgetting about these usages.
I will send a v3 removing them.
Regards,
Atish
- Paul
On 7/30/19, 9:52 PM, "Paul Walmsley" <[email protected]> wrote:
On Tue, 30 Jul 2019, Atish Patra wrote:
> The yaml documentation description of isa strings section doesn't
> specify anything about the case sensitiveness of the isa strings.
> The RISC-V specification clearly specifies it to be case insensitive.
> However, Linux kernel supports only lower case isa strings.
The DT binding documentation specifies an interface. As such the binding
isn't determined by any particular piece of software. So justifying the
binding update by referring to what the Linux kernel currently supports
isn't that relevant. If you still really believe that software should be
required to handle mixed-case DT ISA strings, the right answer would be to
change the software, as your original patches proposed. The way you've
written this patch description, it sounds like you still don't agree with
the conclusion that a strictly lowercase string is a good approach.
If I've misunderstood your intent here, and you do think that specifying
an all lowercase string is sufficient,
I think that specifying an all lowercase string is sufficient. I did not
realize that current commit text could mean something else (.
then instead of the patch
description above, how about something like:
"Since the RISC-V specification states that ISA description strings are
case-insensitive, there's no functional difference between mixed-case,
upper-case, and lower-case ISA strings. Thus, to simplify parsing,
specify that the letters present of riscv,isa must be all lowercase."
Sounds good to me. I will update the patch. Thanks for updated commit text.
That way it's clear that, per the RISC-V specification, there's no
functional difference associated with case.
However, if what you're saying is that you still don't like this outcome,
let me know and I'll write the patch myself. That way you don't have to
have your name associated with a change that you don't believe in.
> Update the yaml documentation accordingly to avoid any confusion.
>
> Signed-off-by: Atish Patra <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index c899111aa5e3..e22a2b7ebafa 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -46,10 +46,14 @@ properties:
> - rv64imafdc
> description:
> Identifies the specific RISC-V instruction set architecture
> - supported by the hart. These are documented in the RISC-V
> + supported by the hart. These are documented in the RISC-V
> User-Level ISA document, available from
> https://riscv.org/specifications/
>
> + Linux kernel only supports lower case isa strings. Thus,
In the past, the DT maintainers have pushed back against explicitly
mentioning the Linux kernel in binding documentation, since the DT
bindings define an interface that's independent of the underlying software
implementation. How about just stating something like "Letters in the
riscv,isa string must be all lowercase" ?
Sure.
Regards,
Atish
> + isa strings must be specified in lower case in device tree
> + as well.
> +
- Paul