On 16/02/2016 09:59, Anshuman Khandual wrote:
> This patch series adds twelve new ELF core note sections which can
> be used with existing ptrace request PTRACE_GETREGSET-SETREGSET for accessing
> various transactional memory and other miscellaneous debug register sets on
> powerpc platform.
Hi Michael,
This series is required to handle TM state in CRIU.
Is there a chance to get it upstream soon ?
Thanks,
Laurent.
>
> Test Result (All tests pass on both BE and LE)
> ----------------------------------------------
> ptrace-ebb PASS
> ptrace-gpr PASS
> ptrace-tm-gpr PASS
> ptrace-tm-spd-gpr PASS
> ptrace-tar PASS
> ptrace-tm-tar PASS
> ptrace-tm-spd-tar PASS
> ptrace-vsx PASS
> ptrace-tm-vsx PASS
> ptrace-tm-spd-vsx PASS
> ptrace-tm-spr PASS
>
> Previous versions:
> ==================
> RFC: https://lkml.org/lkml/2014/4/1/292
> V1: https://lkml.org/lkml/2014/4/2/43
> V2: https://lkml.org/lkml/2014/5/5/88
> V3: https://lkml.org/lkml/2014/5/23/486
> V4: https://lkml.org/lkml/2014/11/11/6
> V5: https://lkml.org/lkml/2014/11/25/134
> V6: https://lkml.org/lkml/2014/12/2/98
> V7: https://lkml.org/lkml/2015/1/14/19
> V8: https://lkml.org/lkml/2015/5/19/700
> V9: https://lkml.org/lkml/2015/10/8/522
>
> Changes in V10:
> ---------------
> - Rebased against the latest mainline
> - Fixed couple of build failures in the test cases related to aux vector
>
> Changes in V9:
> --------------
> - Fixed static build check failure after tm_orig_msr got dropped
> - Fixed asm volatile construct for used registers set
> - Fixed EBB, VSX, VMX tests for LE
> - Fixed TAR test which was failing because of system calls
> - Added checks for PPC_FEATURE2_HTM aux feature in the tests
> - Fixed copyright statements
>
> Changes in V8:
> --------------
> - Split the misc register set into individual ELF core notes
> - Implemented support for VSX register set (on and off TM)
> - Implemented support for EBB register set
> - Implemented review comments on previous versions
> - Some code re-arrangements, re-writes and documentation
> - Added comprehensive list of test cases into selftests
>
> Changes in V7:
> --------------
> - Fixed a config directive in the MISC code
> - Merged the two gitignore patches into a single one
>
> Changes in V6:
> --------------
> - Added two git ignore patches for powerpc selftests
> - Re-formatted all in-code function definitions in kernel-doc format
>
> Changes in V5:
> --------------
> - Changed flush_tmregs_to_thread, so not to take into account self tracing
> - Dropped the 3rd patch in the series which had merged two functions
> - Fixed one build problem for the misc debug register patch
> - Accommodated almost all the review comments from Suka on the 6th patch
> - Minor changes to the self test program
> - Changed commit messages for some of the patches
>
> Changes in V4:
> --------------
> - Added one test program into the powerpc selftest bucket in this regard
> - Split the 2nd patch in the previous series into four different patches
> - Accommodated most of the review comments on the previous patch series
> - Added a patch to merge functions __switch_to_tm and tm_reclaim_task
>
> Changes in V3:
> --------------
> - Added two new error paths in every TM related get/set functions when regset
> support is not present on the system (ENODEV) or when the process does not
> have any transaction active (ENODATA) in the context
> - Installed the active hooks for all the newly added regset core note types
>
> Changes in V2:
> --------------
> - Removed all the power specific ptrace requests corresponding to new NT_PPC_*
> elf core note types. Now all the register sets can be accessed from ptrace
> through PTRACE_GETREGSET/PTRACE_SETREGSET using the individual NT_PPC* core
> note type instead
> - Fixed couple of attribute values for REGSET_TM_CGPR register set
> - Renamed flush_tmreg_to_thread as flush_tmregs_to_thread
> - Fixed 32 bit checkpointed GPR support
> - Changed commit messages accordingly
>
>
> Anshuman Khandual (28):
> elf: Add powerpc specific core note sections
> powerpc, process: Add the function flush_tmregs_to_thread
> powerpc, ptrace: Enable in transaction NT_PRFPREG ptrace requests
> powerpc, ptrace: Enable in transaction NT_PPC_VMX ptrace requests
> powerpc, ptrace: Enable in transaction NT_PPC_VSX ptrace requests
> powerpc, ptrace: Adapt gpr32_get, gpr32_set functions for transaction
> powerpc, ptrace: Enable support for NT_PPC_CGPR
> powerpc, ptrace: Enable support for NT_PPC_CFPR
> powerpc, ptrace: Enable support for NT_PPC_CVMX
> powerpc, ptrace: Enable support for NT_PPC_CVSX
> powerpc, ptrace: Enable support for TM SPR state
> powerpc, ptrace: Enable NT_PPC_TM_CTAR, NT_PPC_TM_CPPR, NT_PPC_TM_CDSCR
> powerpc, ptrace: Enable support for NT_PPPC_TAR, NT_PPC_PPR, NT_PPC_DSCR
> powerpc, ptrace: Enable support for EBB registers
> selftests, powerpc: Move 'reg.h' file outside of 'ebb' sub directory
> selftests, powerpc: Add more SPR numbers, TM & VMX instructions to 'reg.h'
> selftests, powerpc: Add ptrace tests for EBB
> selftests, powerpc: Add ptrace tests for GPR/FPR registers
> selftests, powerpc: Add ptrace tests for GPR/FPR registers in TM
> selftests, powerpc: Add ptrace tests for GPR/FPR registers in suspended TM
> selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR registers
> selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR in TM
> selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR in suspended TM
> selftests, powerpc: Add ptrace tests for VSX, VMX registers
> selftests, powerpc: Add ptrace tests for VSX, VMX registers in TM
> selftests, powerpc: Add ptrace tests for VSX, VMX registers in suspended TM
> selftests, powerpc: Add ptrace tests for TM SPR registers
> selftests, powerpc: Add .gitignore file for ptrace executables
>
> arch/powerpc/include/asm/switch_to.h | 8 +
> arch/powerpc/include/uapi/asm/elf.h | 6 +
> arch/powerpc/kernel/process.c | 20 +
> arch/powerpc/kernel/ptrace.c | 1737 ++++++++++++++++++--
> include/uapi/linux/elf.h | 12 +
> tools/testing/selftests/powerpc/Makefile | 3 +-
> tools/testing/selftests/powerpc/pmu/ebb/ebb.c | 2 +-
> tools/testing/selftests/powerpc/pmu/ebb/ebb.h | 2 +-
> .../selftests/powerpc/pmu/ebb/ebb_handler.S | 2 +-
> tools/testing/selftests/powerpc/pmu/ebb/reg.h | 49 -
> .../selftests/powerpc/pmu/ebb/reg_access_test.c | 2 +-
> tools/testing/selftests/powerpc/ptrace/.gitignore | 11 +
> tools/testing/selftests/powerpc/ptrace/Makefile | 12 +
> .../testing/selftests/powerpc/ptrace/ptrace-ebb.c | 150 ++
> .../testing/selftests/powerpc/ptrace/ptrace-ebb.h | 103 ++
> .../testing/selftests/powerpc/ptrace/ptrace-gpr.c | 191 +++
> .../testing/selftests/powerpc/ptrace/ptrace-gpr.h | 73 +
> .../testing/selftests/powerpc/ptrace/ptrace-tar.c | 151 ++
> .../testing/selftests/powerpc/ptrace/ptrace-tar.h | 50 +
> .../selftests/powerpc/ptrace/ptrace-tm-gpr.c | 288 ++++
> .../selftests/powerpc/ptrace/ptrace-tm-spd-gpr.c | 319 ++++
> .../selftests/powerpc/ptrace/ptrace-tm-spd-tar.c | 184 +++
> .../selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c | 212 +++
> .../selftests/powerpc/ptrace/ptrace-tm-spr.c | 157 ++
> .../selftests/powerpc/ptrace/ptrace-tm-tar.c | 170 ++
> .../selftests/powerpc/ptrace/ptrace-tm-vsx.c | 196 +++
> .../testing/selftests/powerpc/ptrace/ptrace-vsx.c | 138 ++
> .../testing/selftests/powerpc/ptrace/ptrace-vsx.h | 104 ++
> tools/testing/selftests/powerpc/ptrace/ptrace.S | 396 +++++
> tools/testing/selftests/powerpc/ptrace/ptrace.h | 766 +++++++++
> tools/testing/selftests/powerpc/reg.h | 70 +
> 31 files changed, 5406 insertions(+), 178 deletions(-)
> delete mode 100644 tools/testing/selftests/powerpc/pmu/ebb/reg.h
> create mode 100644 tools/testing/selftests/powerpc/ptrace/.gitignore
> create mode 100644 tools/testing/selftests/powerpc/ptrace/Makefile
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-ebb.h
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tar.c
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tar.h
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-gpr.c
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-gpr.c
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spr.c
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar.c
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-vsx.c
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-vsx.c
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-vsx.h
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace.S
> create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace.h
> create mode 100644 tools/testing/selftests/powerpc/reg.h
>
On 7 April 2016 7:23:46 pm AEST, Laurent Dufour <[email protected]> wrote:
>On 16/02/2016 09:59, Anshuman Khandual wrote:
>> This patch series adds twelve new ELF core note sections which can
>> be used with existing ptrace request PTRACE_GETREGSET-SETREGSET for
>accessing
>> various transactional memory and other miscellaneous debug register
>sets on
>> powerpc platform.
>
>Hi Michael,
>
>This series is required to handle TM state in CRIU.
>Is there a chance to get it upstream soon ?
We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU?
cheers
--
Sent from my Android phone with K-9 Mail. Please excuse my brevity.
On 04/07/2016 06:49 PM, Michael Ellerman wrote:
>
>
> On 7 April 2016 7:23:46 pm AEST, Laurent Dufour <[email protected]> wrote:
>> On 16/02/2016 09:59, Anshuman Khandual wrote:
>>> This patch series adds twelve new ELF core note sections which can
>>> be used with existing ptrace request PTRACE_GETREGSET-SETREGSET for
>> accessing
>>> various transactional memory and other miscellaneous debug register
>> sets on
>>> powerpc platform.
>>
>> Hi Michael,
>>
>> This series is required to handle TM state in CRIU.
>> Is there a chance to get it upstream soon ?
>
> We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU?
>
> cheers
>
Hi Michael, Anshuman,
I've managed to implement the GDB support for the new regsets and test
on Power8 (BE and LE). The following is an example of GDB 'info
registers all' partial output showing the new registers when inside a
suspended transaction on Power8 LE using this patchset. Please let me
know if you need any additional information or tests from GDB side.
(gdb) info registers all
...
dscr 0x0 0
ppr 0xc000000000000 3377699720527872
tar 0x0 0
ebbrr <unavailable>
ebbhr <unavailable>
bescr <unavailable>
siar <unavailable>
sdar <unavailable>
sier <unavailable>
mmcr2 <unavailable>
mmcr0 <unavailable>
tfhar 0x10002b30 268446512
texasr 0x110000098000001 76561196215435265
tfiar 0x10002ad9 268446425
cr0 0x10002b2c 268446508
cr1 0x3fffffffeb20 70368744172320
cr2 0x10027f00 268599040
cr3 0x10020278 268567160
cr4 0x1000339c 268448668
cr5 0x42000488 1107297416
cr6 0x4000 16384
cr7 0x3fffb7ea0f28 70367534780200
cr8 0x800000010280f033 9223372041191747635
cr9 0x10020178 268566904
cr10 0x10020278 268567160
cr11 0x0 0
cr12 0x0 0
cr13 0x3fffb7ffc350 70367536202576
cr14 0x0 0
cr15 0x0 0
cr16 0x0 0
cr17 0x0 0
cr18 0x0 0
cr19 0x0 0
cr20 0x0 0
cr21 0x0 0
cr22 0x0 0
cr23 0x0 0
cr24 0x0 0
cr25 0x0 0
cr26 0x0 0
cr27 0x3fffb7fef718 70367536150296
cr28 0x0 0
cr29 0x3fffb7fef720 70367536150304
cr30 0x0 0
cr31 0x3fffffffeb20 70368744172320
cf0 0.30000001192092896 (raw 0x3fd3333340000000)
cf1 0.30000001192092896 (raw 0x3fd3333340000000)
cf2 0.30000001192092896 (raw 0x3fd3333340000000)
cf3 0.30000001192092896 (raw 0x3fd3333340000000)
cf4 0.30000001192092896 (raw 0x3fd3333340000000)
cf5 0.30000001192092896 (raw 0x3fd3333340000000)
cf6 0.30000001192092896 (raw 0x3fd3333340000000)
cf7 0.30000001192092896 (raw 0x3fd3333340000000)
cf8 0.30000001192092896 (raw 0x3fd3333340000000)
cf9 0.30000001192092896 (raw 0x3fd3333340000000)
cf10 0.30000001192092896 (raw 0x3fd3333340000000)
cf11 0.30000001192092896 (raw 0x3fd3333340000000)
cf12 0.30000001192092896 (raw 0x3fd3333340000000)
cf13 0.30000001192092896 (raw 0x3fd3333340000000)
cf14 0.30000001192092896 (raw 0x3fd3333340000000)
cf15 0.30000001192092896 (raw 0x3fd3333340000000)
cf16 0.30000001192092896 (raw 0x3fd3333340000000)
cf17 0.30000001192092896 (raw 0x3fd3333340000000)
cf18 0.30000001192092896 (raw 0x3fd3333340000000)
cf19 0.30000001192092896 (raw 0x3fd3333340000000)
cf20 0.30000001192092896 (raw 0x3fd3333340000000)
cf21 0.30000001192092896 (raw 0x3fd3333340000000)
cf22 0.30000001192092896 (raw 0x3fd3333340000000)
cf23 0.30000001192092896 (raw 0x3fd3333340000000)
cf24 0.30000001192092896 (raw 0x3fd3333340000000)
cf25 0.30000001192092896 (raw 0x3fd3333340000000)
cf26 0.30000001192092896 (raw 0x3fd3333340000000)
cf27 0.30000001192092896 (raw 0x3fd3333340000000)
cf28 0.30000001192092896 (raw 0x3fd3333340000000)
cf29 0.30000001192092896 (raw 0x3fd3333340000000)
cf30 0.30000001192092896 (raw 0x3fd3333340000000)
cf31 0.30000001192092896 (raw 0x3fd3333340000000)
cfpscr 0x0 0
cvr0 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr1 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr2 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr3 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr4 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr5 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr6 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr7 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr8 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr9 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr10 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr11 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr12 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr13 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr14 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr15 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr16 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr17 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr18 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr19 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr20 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr21 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr22 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr23 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr24 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr25 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr26 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr27 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr28 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr29 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr30 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr31 {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvscr 0x0 0
cvrsave 0xffffffff -1
cdscr 0x0 0
cppr 0xc000000000000 3377699720527872
ctar 0x0 0
cvs0 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs1 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs2 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs3 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs4 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs5 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs6 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs7 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs8 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs9 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs10 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs11 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs12 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs13 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs14 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs15 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs16 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs17 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs18 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs19 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs20 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs21 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs22 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs23 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs24 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs25 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs26 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs27 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs28 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs29 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs30 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs31 {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs32 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs33 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs34 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs35 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs36 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs37 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs38 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs39 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs40 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs41 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs42 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs43 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs44 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs45 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs46 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs47 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs48 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs49 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs50 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs51 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs52 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs53 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs54 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs55 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs56 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs57 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs58 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs59 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs60 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs61 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs62 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs63 {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cf32 0 (raw 0x0000000000000000)
cf33 0 (raw 0x0000000000000000)
cf34 0 (raw 0x0000000000000000)
cf35 0 (raw 0x0000000000000000)
cf36 0 (raw 0x0000000000000000)
cf37 0 (raw 0x0000000000000000)
cf38 0 (raw 0x0000000000000000)
cf39 0 (raw 0x0000000000000000)
cf40 0 (raw 0x0000000000000000)
cf41 0 (raw 0x0000000000000000)
cf42 0 (raw 0x0000000000000000)
cf43 0 (raw 0x0000000000000000)
cf44 0 (raw 0x0000000000000000)
cf45 0 (raw 0x0000000000000000)
cf46 0 (raw 0x0000000000000000)
cf47 0 (raw 0x0000000000000000)
cf48 0 (raw 0x0000000000000000)
cf49 0 (raw 0x0000000000000000)
cf50 0 (raw 0x0000000000000000)
cf51 0 (raw 0x0000000000000000)
cf52 0 (raw 0x0000000000000000)
cf53 0 (raw 0x0000000000000000)
cf54 0 (raw 0x0000000000000000)
cf55 0 (raw 0x0000000000000000)
cf56 0 (raw 0x0000000000000000)
cf57 0 (raw 0x0000000000000000)
cf58 0 (raw 0x0000000000000000)
cf59 0 (raw 0x0000000000000000)
cf60 0 (raw 0x0000000000000000)
cf61 0 (raw 0x0000000000000000)
cf62 0 (raw 0x0000000000000000)
cf63 0 (raw 0x0000000000000000)
Thanks and regards,
--
Edjunior Barbosa Machado
On 07/04/2016 23:49, Michael Ellerman wrote:
>
>
> On 7 April 2016 7:23:46 pm AEST, Laurent Dufour <[email protected]> wrote:
>> On 16/02/2016 09:59, Anshuman Khandual wrote:
>>> This patch series adds twelve new ELF core note sections which can
>>> be used with existing ptrace request PTRACE_GETREGSET-SETREGSET for
>> accessing
>>> various transactional memory and other miscellaneous debug register
>> sets on
>>> powerpc platform.
>>
>> Hi Michael,
>>
>> This series is required to handle TM state in CRIU.
>> Is there a chance to get it upstream soon ?
>
> We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU?
I just started integrating it in CRIU, my basic tests didn't report any
issue with the new ptrace API, but I can't state that it is bug free ;)
Cheers,
Laurent.
On Mon, 2016-04-11 at 09:40 +0200, Laurent Dufour wrote:
> On 07/04/2016 23:49, Michael Ellerman wrote:
> > On 7 April 2016 7:23:46 pm AEST, Laurent Dufour <[email protected]> wrote:
> > > This series is required to handle TM state in CRIU.
> > > Is there a chance to get it upstream soon ?
> >
> > We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU?
>
> I just started integrating it in CRIU, my basic tests didn't report any
> issue with the new ptrace API, but I can't state that it is bug free ;)
Sure. But if it's working for CRIU that's at least postive :)
cheers
On Mon, 2016-04-11 at 03:32 -0300, Edjunior Barbosa Machado wrote:
> Hi Michael, Anshuman,
>
> I've managed to implement the GDB support for the new regsets and test
> on Power8 (BE and LE).
Great work thanks!
> The following is an example of GDB 'info
> registers all' partial output showing the new registers when inside a
> suspended transaction on Power8 LE using this patchset. Please let me
> know if you need any additional information or tests from GDB side.
What's the plan for merging the gdb changes?
> (gdb) info registers all
> ...
> dscr 0x0 0
> ppr 0xc000000000000 3377699720527872
> tar 0x0 0
> ebbrr <unavailable>
> ebbhr <unavailable>
> bescr <unavailable>
> siar <unavailable>
> sdar <unavailable>
> sier <unavailable>
> mmcr2 <unavailable>
> mmcr0 <unavailable>
> tfhar 0x10002b30 268446512
> texasr 0x110000098000001 76561196215435265
> tfiar 0x10002ad9 268446425
> cr0 0x10002b2c 268446508
Using 'c' as the prefix is a bit confusing here, as 'cr0' is usually used to
refer to the CR0 field of CR.
Speaking of which, I don't see CR here? Or is it somewhere above in the ... ?
Maybe the prefix could be 'c_' ?
Or do other arches already use 'c' as the prefix?
Otherwise looks good.
cheers
On 13/04/2016 07:14, Michael Ellerman wrote:
> On Mon, 2016-04-11 at 09:40 +0200, Laurent Dufour wrote:
>> On 07/04/2016 23:49, Michael Ellerman wrote:
>>> On 7 April 2016 7:23:46 pm AEST, Laurent Dufour <[email protected]> wrote:
>>>> This series is required to handle TM state in CRIU.
>>>> Is there a chance to get it upstream soon ?
>>>
>>> We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU?
>>
>> I just started integrating it in CRIU, my basic tests didn't report any
>> issue with the new ptrace API, but I can't state that it is bug free ;)
>
> Sure. But if it's working for CRIU that's at least postive :)
I did additional tests and the Anshuman's series is working fine for
CRIU's support with the attached patch applied.
Michael, could you please applied the attached patch among the
Anshuman's series ?
Thanks,
Laurent.
On 04/13/2016 02:36 AM, Michael Ellerman wrote:
> On Mon, 2016-04-11 at 03:32 -0300, Edjunior Barbosa Machado wrote:
>> Hi Michael, Anshuman,
>>
>> I've managed to implement the GDB support for the new regsets and test
>> on Power8 (BE and LE).
>
> Great work thanks!
>
>> The following is an example of GDB 'info
>> registers all' partial output showing the new registers when inside a
>> suspended transaction on Power8 LE using this patchset. Please let me
>> know if you need any additional information or tests from GDB side.
>
> What's the plan for merging the gdb changes?
Thanks for the feedback, Michael. I intend to submit the patches to the
gdb mailing list for review right after the kernel patchset is checked in.
>
>> (gdb) info registers all
>> ...
>> dscr 0x0 0
>> ppr 0xc000000000000 3377699720527872
>> tar 0x0 0
>> ebbrr <unavailable>
>> ebbhr <unavailable>
>> bescr <unavailable>
>> siar <unavailable>
>> sdar <unavailable>
>> sier <unavailable>
>> mmcr2 <unavailable>
>> mmcr0 <unavailable>
>> tfhar 0x10002b30 268446512
>> texasr 0x110000098000001 76561196215435265
>> tfiar 0x10002ad9 268446425
>> cr0 0x10002b2c 268446508
>
> Using 'c' as the prefix is a bit confusing here, as 'cr0' is usually used to
> refer to the CR0 field of CR.
>
> Speaking of which, I don't see CR here? Or is it somewhere above in the ... ?
>
> Maybe the prefix could be 'c_' ?
>
> Or do other arches already use 'c' as the prefix?
Good point, I hadn't thought about the possible confusion with CR
register (CR doesn't appear in the excerpt because it is just a partial
output of 'info registers all', reduced to the new registers only). As
far as I am aware, we don't have other arches that use 'c' as prefix
(Are there other arches that provide checkpointed registers? s390 gdb
uses 't' as prefix, but for the transactional regs, which would be the
"opposite" of our checkpointed ones here, if I'm not mistaken), but this
can be changed with no difficult in gdb code.
Thanks and regards,
--
Edjunior Barbosa Machado