The MediaTek xHCI dt-binding expects a specific order for the clocks,
but the mt8192 and mt8195 devicetrees were skipping some of the middle
clocks. These clocks are wired to the controller hardware but aren't
controllable.
Add the missing clocks as handles to fixed clocks, so that the clock
order is respected and the dtbs_check warnings are gone.
Signed-off-by: Nícolas F. R. A. Prado <[email protected]>
---
A previous attempt to solve this also made all clocks required and
updated all MediaTek DTs using the xhci binding [1].
To avoid the DT change noise, the binding change is now being reverted
[2] and only mt8192 and mt8195 DTs are updated in this commit to get rid
of the warnings.
[1] https://lore.kernel.org/all/[email protected]/
[2] https://lore.kernel.org/all/[email protected]
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 9 ++++++---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++----
2 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index cbae5a5ee4a0..869958fd420c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -724,9 +724,12 @@ xhci: usb@11200000 {
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
<&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&infracfg CLK_INFRA_SSUSB>,
- <&infracfg CLK_INFRA_SSUSB_XHCI>,
- <&apmixedsys CLK_APMIXED_USBPLL>;
- clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ <&apmixedsys CLK_APMIXED_USBPLL>,
+ <&clk26m>,
+ <&clk26m>,
+ <&infracfg CLK_INFRA_SSUSB_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
+ "xhci_ck";
wakeup-source;
mediatek,syscon-wakeup = <&pericfg 0x420 102>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 066c14989708..725985e599be 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -560,8 +560,10 @@ xhci0: usb@11200000 {
clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
<&topckgen CLK_TOP_SSUSB_REF>,
<&apmixedsys CLK_APMIXED_USB1PLL>,
+ <&clk26m>,
<&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
- clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck";
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
+ "xhci_ck";
mediatek,syscon-wakeup = <&pericfg 0x400 103>;
wakeup-source;
status = "disabled";
@@ -625,8 +627,10 @@ xhci1: usb@11290000 {
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
<&topckgen CLK_TOP_SSUSB_P1_REF>,
<&apmixedsys CLK_APMIXED_USB1PLL>,
+ <&clk26m>,
<&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
- clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck";
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
+ "xhci_ck";
mediatek,syscon-wakeup = <&pericfg 0x400 104>;
wakeup-source;
status = "disabled";
@@ -646,8 +650,11 @@ xhci2: usb@112a0000 {
<&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
<&topckgen CLK_TOP_SSUSB_P2_REF>,
+ <&clk26m>,
+ <&clk26m>,
<&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
- clock-names = "sys_ck", "ref_ck", "xhci_ck";
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
+ "xhci_ck";
mediatek,syscon-wakeup = <&pericfg 0x400 105>;
wakeup-source;
status = "disabled";
@@ -667,8 +674,11 @@ xhci3: usb@112b0000 {
<&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
<&topckgen CLK_TOP_SSUSB_P3_REF>,
+ <&clk26m>,
+ <&clk26m>,
<&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
- clock-names = "sys_ck", "ref_ck", "xhci_ck";
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
+ "xhci_ck";
mediatek,syscon-wakeup = <&pericfg 0x400 106>;
wakeup-source;
status = "disabled";
--
2.37.0
Il 08/07/22 21:43, Nícolas F. R. A. Prado ha scritto:
> The MediaTek xHCI dt-binding expects a specific order for the clocks,
> but the mt8192 and mt8195 devicetrees were skipping some of the middle
> clocks. These clocks are wired to the controller hardware but aren't
> controllable.
>
> Add the missing clocks as handles to fixed clocks, so that the clock
> order is respected and the dtbs_check warnings are gone.
>
> Signed-off-by: Nícolas F. R. A. Prado <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
> ---
> A previous attempt to solve this also made all clocks required and
> updated all MediaTek DTs using the xhci binding [1].
>
> To avoid the DT change noise, the binding change is now being reverted
> [2] and only mt8192 and mt8195 DTs are updated in this commit to get rid
> of the warnings.
>
> [1] https://lore.kernel.org/all/[email protected]/
> [2] https://lore.kernel.org/all/[email protected]
>
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 9 ++++++---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++----
> 2 files changed, 20 insertions(+), 7 deletions(-)
On 11/07/2022 11:34, AngeloGioacchino Del Regno wrote:
> Il 08/07/22 21:43, Nícolas F. R. A. Prado ha scritto:
>> The MediaTek xHCI dt-binding expects a specific order for the clocks,
>> but the mt8192 and mt8195 devicetrees were skipping some of the middle
>> clocks. These clocks are wired to the controller hardware but aren't
>> controllable.
>>
>> Add the missing clocks as handles to fixed clocks, so that the clock
>> order is respected and the dtbs_check warnings are gone.
>>
>> Signed-off-by: Nícolas F. R. A. Prado <[email protected]>
>
> Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
>
applied, thanks!
>> ---
>> A previous attempt to solve this also made all clocks required and
>> updated all MediaTek DTs using the xhci binding [1].
>>
>> To avoid the DT change noise, the binding change is now being reverted
>> [2] and only mt8192 and mt8195 DTs are updated in this commit to get rid
>> of the warnings.
>>
>> [1] https://lore.kernel.org/all/[email protected]/
>> [2] https://lore.kernel.org/all/[email protected]
>>
>> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 9 ++++++---
>> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++----
>> 2 files changed, 20 insertions(+), 7 deletions(-)