From: Srinivasa Rao Mandadapu <[email protected]>
This patch set is to add support for Audio over wcd codec,
digital mics, through digital codecs and without ADSP.
Changes Since V6:
-- Split cdc dma regmap config macros.
-- Add write dma reg fields for i2s path.
-- Add helper function to distinguish rxtx and va dma ports.
-- Optimizing clock and reg name in cpu dt-bindings.
-- Update buffer management for cdc dma path.
-- Remove Kconfig fields of machine driver.
Changes Since V5:
-- Include MI2S primary node to snd_soc_dai_driver in lpass-sc7280 platform driver.
-- Move dependency patch list to corresponding patch.
-- Add support for missing cdc-dma ports.
-- Change if/else conditional statements to switch cases.
-- Add missing error handlings.
-- Typo errors fix.
Changes Since V4:
-- Remove unused variable in lpass-sc7280 platform driver.
Changes Since V3:
-- Remove redundant power domain controls. As power domains can be configured from dtsi.
Changes Since V2:
-- Split lpass sc7280 cpu driver patch and create regmap config patch.
-- Create patches based on latest kernel tip.
-- Add helper function to get dma control and lpaif handle.
-- Remove unused variables.
Changes Since V1:
-- Typo errors fix
-- CPU driver readable/writable apis optimization.
-- Add Missing config patch
-- Add Common api for repeated dmactl initialization.
Srinivasa Rao Mandadapu (10):
ASoC: qcom: Move lpass_pcm_data structure to lpass header
ASoC: qcom: lpass: Add dma fields for codec dma lpass interface
ASoC: qcom: Add register definition for codec rddma and wrdma
ASoC: qcom: Add lpass CPU driver for codec dma control
ASoC: qcom: Add helper function to get dma control and lpaif handle
ASoC: qcom: Add support for codec dma driver
ASoC: qcom: Add regmap config support for codec dma driver
ASoC: dt-bindings: Add SC7280 lpass cpu bindings
ASoC: qcom: lpass-sc7280: Add platform driver for lpass audio
ASoC: qcom: SC7280: Update config for building codec dma drivers
.../devicetree/bindings/sound/qcom,lpass-cpu.yaml | 70 ++-
sound/soc/qcom/Kconfig | 11 +
sound/soc/qcom/Makefile | 4 +
sound/soc/qcom/lpass-cdc-dma.c | 275 +++++++++
sound/soc/qcom/lpass-cpu.c | 244 +++++++-
sound/soc/qcom/lpass-lpaif-reg.h | 127 ++++-
sound/soc/qcom/lpass-platform.c | 617 ++++++++++++++++++---
sound/soc/qcom/lpass-sc7280.c | 441 +++++++++++++++
sound/soc/qcom/lpass.h | 162 ++++++
9 files changed, 1864 insertions(+), 87 deletions(-)
create mode 100644 sound/soc/qcom/lpass-cdc-dma.c
create mode 100644 sound/soc/qcom/lpass-sc7280.c
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
From: Srinivasa Rao Mandadapu <[email protected]>
Add bindings for sc7280 lpass cpu driver which supports
audio over i2s based speaker, soundwire based headset, msm dmics
and HDMI Port.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
---
.../devicetree/bindings/sound/qcom,lpass-cpu.yaml | 70 +++++++++++++++++++---
1 file changed, 62 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.yaml
index 1e23c0e..efaaa8ea 100644
--- a/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.yaml
+++ b/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.yaml
@@ -22,35 +22,36 @@ properties:
- qcom,lpass-cpu
- qcom,apq8016-lpass-cpu
- qcom,sc7180-lpass-cpu
+ - qcom,sc7280-lpass-cpu
reg:
- maxItems: 2
+ maxItems: 5
description: LPAIF core registers
reg-names:
- maxItems: 2
+ maxItems: 5
clocks:
minItems: 3
- maxItems: 6
+ maxItems: 7
clock-names:
minItems: 3
- maxItems: 6
+ maxItems: 7
interrupts:
- maxItems: 2
+ maxItems: 4
description: LPAIF DMA buffer interrupt
interrupt-names:
- maxItems: 2
+ maxItems: 4
qcom,adsp:
$ref: /schemas/types.yaml#/definitions/phandle
description: Phandle for the audio DSP node
iommus:
- maxItems: 2
+ maxItems: 3
description: Phandle to apps_smmu node with sid mask
power-domains:
@@ -69,7 +70,7 @@ patternProperties:
"^dai-link@[0-9a-f]$":
type: object
description: |
- LPASS CPU dai node for each I2S device. Bindings of each node
+ LPASS CPU dai node for each I2S device or Soundwire device. Bindings of each node
depends on the specific driver providing the functionality and
properties.
properties:
@@ -174,6 +175,59 @@ allOf:
- iommus
- power-domains
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sc7280-lpass-cpu
+
+ then:
+ properties:
+ clock-names:
+ oneOf:
+ - items: #for I2S
+ - const: aon_cc_audio_hm_h
+ - const: core_cc_sysnoc_mport_core
+ - const: core_cc_ext_if1_ibit
+ - items: #for Soundwire
+ - const: aon_cc_audio_hm_h
+ - const: audio_cc_codec_mem0
+ - const: audio_cc_codec_mem1
+ - const: audio_cc_codec_mem2
+ - items: #for HDMI
+ - const: aon_cc_audio_hm_h
+
+ reg-names:
+ anyOf:
+ - items: #for I2S
+ - const: lpass-lpaif
+ - items: #for I2S and HDMI
+ - const: lpass-hdmiif
+ - const: lpass-lpaif
+ - items: #for I2S, soundwire and HDMI
+ - const: lpass-hdmiif
+ - const: lpass-lpaif
+ - const: lpass-rxtx-cdc-dma-lpm
+ - const: lpass-rxtx-lpaif
+ - const: lpass-va-lpaif
+ - const: lpass-va-cdc-dma-lpm
+ interrupt-names:
+ anyOf:
+ - items: #for I2S
+ - const: lpass-irq-lpaif
+ - items: #for I2S and HDMI
+ - const: lpass-irq-lpaif
+ - const: lpass-irq-hdmi
+ - items: #for I2S, soundwire and HDMI
+ - const: lpass-irq-lpaif
+ - const: lpass-irq-hdmi
+ - const: lpass-irq-vaif
+ - const: lpass-irq-rxtxif
+
+ required:
+ - iommus
+ - power-domains
+
examples:
- |
#include <dt-bindings/sound/sc7180-lpass.h>
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
From: Srinivasa Rao Mandadapu <[email protected]>
This patch adds register definitions for codec read dma and write dma
lpass interface.
Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
Co-developed-by: Venkata Prasad Potturu <[email protected]>
Signed-off-by: Venkata Prasad Potturu <[email protected]>
---
sound/soc/qcom/lpass-lpaif-reg.h | 127 +++++++++++++++++++++++++++++++++++++--
1 file changed, 121 insertions(+), 6 deletions(-)
diff --git a/sound/soc/qcom/lpass-lpaif-reg.h b/sound/soc/qcom/lpass-lpaif-reg.h
index 2eb03ad..6d9d9d1 100644
--- a/sound/soc/qcom/lpass-lpaif-reg.h
+++ b/sound/soc/qcom/lpass-lpaif-reg.h
@@ -74,6 +74,21 @@
#define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port))
#define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port))
+/* LPAIF RXTX IRQ */
+#define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \
+ (v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * (port))
+
+#define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port)
+#define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port)
+#define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port)
+
+/* LPAIF VA IRQ */
+#define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \
+ (v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port))
+
+#define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x0, port)
+#define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x4, port)
+#define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0xC, port)
#define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr) \
((v->hdmi_irq_reg_base) + (addr))
@@ -139,12 +154,112 @@
(LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
LPAIF_WRDMA##reg##_REG(v, chan))
-#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id)
-#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id)
-#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id)
-#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id)
-#define LPAIF_DMAPER_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PER, dai_id)
-#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id)
+#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) \
+ (is_cdc_dma_port(dai_id) ? \
+ __LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \
+ __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id))
+#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) \
+ (is_cdc_dma_port(dai_id) ? \
+ __LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \
+ __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id))
+#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) \
+ (is_cdc_dma_port(dai_id) ? \
+ __LPAIF_CDC_DMA_REG(v, chan, dir, BUFF, dai_id) : \
+ __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id))
+#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) \
+ (is_cdc_dma_port(dai_id) ? \
+ __LPAIF_CDC_DMA_REG(v, chan, dir, CURR, dai_id) : \
+ __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id))
+#define LPAIF_DMAPER_REG(v, chan, dir, dai_id) \
+ (is_cdc_dma_port(dai_id) ? \
+ __LPAIF_CDC_DMA_REG(v, chan, dir, PER, dai_id) : \
+ __LPAIF_DMA_REG(v, chan, dir, PER, dai_id))
+#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) \
+ (is_cdc_dma_port(dai_id) ? \
+ __LPAIF_CDC_DMA_REG(v, chan, dir, PERCNT, dai_id) : \
+ __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id))
+
+#define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, dai_id) \
+ (is_rxtx_cdc_dma_port(dai_id) ? \
+ (v->rxtx_rdma_reg_base + (addr) + v->rxtx_rdma_reg_stride * (chan)) : \
+ (v->va_rdma_reg_base + (addr) + v->va_rdma_reg_stride * (chan)))
+
+#define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, dai_id) \
+ LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
+#define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, dai_id) \
+ LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
+#define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, dai_id) \
+ LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
+#define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, dai_id) \
+ LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
+#define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, dai_id) \
+ LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
+#define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, dai_id) \
+ LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
+
+#define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
+#define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
+#define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
+#define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
+#define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
+#define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, dai_id) \
+ LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
+
+#define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan, dai_id) \
+ (is_rxtx_cdc_dma_port(dai_id) ? \
+ (v->rxtx_wrdma_reg_base + (addr) + \
+ v->rxtx_wrdma_reg_stride * (chan - v->rxtx_wrdma_channel_start)) : \
+ (v->va_wrdma_reg_base + (addr) + \
+ v->va_wrdma_reg_stride * (chan - v->va_wrdma_channel_start)))
+
+#define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, dai_id) \
+ LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
+#define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, dai_id) \
+ LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
+#define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, dai_id) \
+ LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
+#define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, dai_id) \
+ LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
+#define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, dai_id) \
+ LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
+#define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, dai_id) \
+ LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
+
+#define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai_id) \
+ LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
+#define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, dai_id) \
+ LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
+#define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, dai_id) \
+ LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
+#define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, dai_id) \
+ LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
+#define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai_id) \
+ LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
+#define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, dai_id) \
+ LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
+
+#define __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) \
+ (is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \
+ LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))
+
+#define __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id) \
+ (is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \
+ LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))
+
+#define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, dai_id) \
+ ((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
+ __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) : \
+ __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id))
+
+#define LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) \
+ ((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
+ LPAIF_CDC_RDMA_INTF_REG(v, chan, dai_id) : \
+ LPAIF_CDC_WRDMA_INTF_REG(v, chan, dai_id))
+
+#define LPAIF_INTF_REG(v, chan, dir, dai_id) \
+ (is_cdc_dma_port(dai_id) ? \
+ LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) : \
+ LPAIF_DMACTL_REG(v, chan, dir, dai_id))
#define LPAIF_DMACTL_BURSTEN_SINGLE 0
#define LPAIF_DMACTL_BURSTEN_INCR4 1
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
On Thu, 02 Dec 2021 21:13:24 +0530, Srinivasa Rao Mandadapu wrote:
> From: Srinivasa Rao Mandadapu <[email protected]>
>
> Add bindings for sc7280 lpass cpu driver which supports
> audio over i2s based speaker, soundwire based headset, msm dmics
> and HDMI Port.
>
> Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
> Co-developed-by: Venkata Prasad Potturu <[email protected]>
> Signed-off-by: Venkata Prasad Potturu <[email protected]>
> ---
> .../devicetree/bindings/sound/qcom,lpass-cpu.yaml | 70 +++++++++++++++++++---
> 1 file changed, 62 insertions(+), 8 deletions(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.example.dt.yaml: lpass@62d80000: reg: [[0, 1658351616, 0, 425984], [0, 1659895808, 0, 167936]] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.example.dt.yaml: lpass@62d80000: reg-names: ['lpass-hdmiif', 'lpass-lpaif'] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.example.dt.yaml: lpass@62d80000: interrupts: [[0, 160, 1], [0, 268, 1]] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.example.dt.yaml: lpass@62d80000: interrupt-names: ['lpass-irq-lpaif', 'lpass-irq-hdmi'] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.example.dt.yaml: lpass@62d80000: iommus: [[4294967295, 4128, 0], [4294967295, 4146, 0]] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/sound/qcom,lpass-cpu.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1562819
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On 02/12/2021 15:43, Srinivasa Rao Mandadapu wrote:
> From: Srinivasa Rao Mandadapu <[email protected]>
>
> This patch adds register definitions for codec read dma and write dma
> lpass interface.
>
> Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
> Co-developed-by: Venkata Prasad Potturu <[email protected]>
> Signed-off-by: Venkata Prasad Potturu <[email protected]>
Overall the patch LGTM,
but for bisectablity reasons, pleas make sure these macros
is_rxtx_cdc_dma_port()
is_cdc_dma_port()
to be avaiable in this patch.
Once that is fixed you could add my
Reviewed-by: Srinivas Kandagatla <[email protected]>
--srini
> ---
> sound/soc/qcom/lpass-lpaif-reg.h | 127 +++++++++++++++++++++++++++++++++++++--
> 1 file changed, 121 insertions(+), 6 deletions(-)
>
> diff --git a/sound/soc/qcom/lpass-lpaif-reg.h b/sound/soc/qcom/lpass-lpaif-reg.h
> index 2eb03ad..6d9d9d1 100644
> --- a/sound/soc/qcom/lpass-lpaif-reg.h
> +++ b/sound/soc/qcom/lpass-lpaif-reg.h
> @@ -74,6 +74,21 @@
> #define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port))
> #define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port))
>
> +/* LPAIF RXTX IRQ */
> +#define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \
> + (v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * (port))
> +
> +#define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port)
> +#define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port)
> +#define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port)
> +
> +/* LPAIF VA IRQ */
> +#define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \
> + (v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port))
> +
> +#define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x0, port)
> +#define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x4, port)
> +#define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0xC, port)
>
> #define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr) \
> ((v->hdmi_irq_reg_base) + (addr))
> @@ -139,12 +154,112 @@
> (LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
> LPAIF_WRDMA##reg##_REG(v, chan))
>
> -#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id)
> -#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id)
> -#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id)
> -#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id)
> -#define LPAIF_DMAPER_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PER, dai_id)
> -#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id)
> +#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) \
> + (is_cdc_dma_port(dai_id) ? \
> + __LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \
> + __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id))
> +#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) \
> + (is_cdc_dma_port(dai_id) ? \
> + __LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \
> + __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id))
> +#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) \
> + (is_cdc_dma_port(dai_id) ? \
> + __LPAIF_CDC_DMA_REG(v, chan, dir, BUFF, dai_id) : \
> + __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id))
> +#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) \
> + (is_cdc_dma_port(dai_id) ? \
> + __LPAIF_CDC_DMA_REG(v, chan, dir, CURR, dai_id) : \
> + __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id))
> +#define LPAIF_DMAPER_REG(v, chan, dir, dai_id) \
> + (is_cdc_dma_port(dai_id) ? \
> + __LPAIF_CDC_DMA_REG(v, chan, dir, PER, dai_id) : \
> + __LPAIF_DMA_REG(v, chan, dir, PER, dai_id))
> +#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) \
> + (is_cdc_dma_port(dai_id) ? \
> + __LPAIF_CDC_DMA_REG(v, chan, dir, PERCNT, dai_id) : \
> + __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id))
> +
> +#define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, dai_id) \
> + (is_rxtx_cdc_dma_port(dai_id) ? \
> + (v->rxtx_rdma_reg_base + (addr) + v->rxtx_rdma_reg_stride * (chan)) : \
> + (v->va_rdma_reg_base + (addr) + v->va_rdma_reg_stride * (chan)))
> +
> +#define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, dai_id) \
> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
> +#define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, dai_id) \
> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
> +#define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, dai_id) \
> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
> +#define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, dai_id) \
> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
> +#define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, dai_id) \
> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
> +#define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, dai_id) \
> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
> +
> +#define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
> +#define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
> +#define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
> +#define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
> +#define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
> +#define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, dai_id) \
> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
> +
> +#define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan, dai_id) \
> + (is_rxtx_cdc_dma_port(dai_id) ? \
> + (v->rxtx_wrdma_reg_base + (addr) + \
> + v->rxtx_wrdma_reg_stride * (chan - v->rxtx_wrdma_channel_start)) : \
> + (v->va_wrdma_reg_base + (addr) + \
> + v->va_wrdma_reg_stride * (chan - v->va_wrdma_channel_start)))
> +
> +#define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, dai_id) \
> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
> +#define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, dai_id) \
> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
> +#define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, dai_id) \
> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
> +#define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, dai_id) \
> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
> +#define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, dai_id) \
> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
> +#define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, dai_id) \
> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
> +
> +#define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai_id) \
> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
> +#define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, dai_id) \
> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
> +#define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, dai_id) \
> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
> +#define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, dai_id) \
> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
> +#define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai_id) \
> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
> +#define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, dai_id) \
> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
> +
> +#define __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) \
> + (is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \
> + LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))
> +
> +#define __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id) \
> + (is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \
> + LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))
> +
> +#define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, dai_id) \
> + ((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
> + __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) : \
> + __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id))
> +
> +#define LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) \
> + ((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
> + LPAIF_CDC_RDMA_INTF_REG(v, chan, dai_id) : \
> + LPAIF_CDC_WRDMA_INTF_REG(v, chan, dai_id))
> +
> +#define LPAIF_INTF_REG(v, chan, dir, dai_id) \
> + (is_cdc_dma_port(dai_id) ? \
> + LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) : \
> + LPAIF_DMACTL_REG(v, chan, dir, dai_id))
>
> #define LPAIF_DMACTL_BURSTEN_SINGLE 0
> #define LPAIF_DMACTL_BURSTEN_INCR4 1
>
On 12/3/2021 6:58 PM, Srinivas Kandagatla wrote:
Thanks for your time Srini!!!
>
> On 02/12/2021 15:43, Srinivasa Rao Mandadapu wrote:
>> From: Srinivasa Rao Mandadapu <[email protected]>
>>
>> This patch adds register definitions for codec read dma and write dma
>> lpass interface.
>>
>> Signed-off-by: Srinivasa Rao Mandadapu <[email protected]>
>> Co-developed-by: Venkata Prasad Potturu <[email protected]>
>> Signed-off-by: Venkata Prasad Potturu <[email protected]>
>
> Overall the patch LGTM,
> but for bisectablity reasons, pleas make sure these macros
>
> is_rxtx_cdc_dma_port()
> is_cdc_dma_port()
>
> to be avaiable in this patch.
Okay. Will change accordingly.
>
> Once that is fixed you could add my
>
> Reviewed-by: Srinivas Kandagatla <[email protected]>
>
> --srini
>
>
>> ---
>> sound/soc/qcom/lpass-lpaif-reg.h | 127
>> +++++++++++++++++++++++++++++++++++++--
>> 1 file changed, 121 insertions(+), 6 deletions(-)
>>
>> diff --git a/sound/soc/qcom/lpass-lpaif-reg.h
>> b/sound/soc/qcom/lpass-lpaif-reg.h
>> index 2eb03ad..6d9d9d1 100644
>> --- a/sound/soc/qcom/lpass-lpaif-reg.h
>> +++ b/sound/soc/qcom/lpass-lpaif-reg.h
>> @@ -74,6 +74,21 @@
>> #define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4,
>> (port))
>> #define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC,
>> (port))
>> +/* LPAIF RXTX IRQ */
>> +#define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \
>> + (v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride *
>> (port))
>> +
>> +#define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v,
>> 0x0, port)
>> +#define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v,
>> 0x4, port)
>> +#define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v,
>> 0xC, port)
>> +
>> +/* LPAIF VA IRQ */
>> +#define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \
>> + (v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port))
>> +
>> +#define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x0, port)
>> +#define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x4,
>> port)
>> +#define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0xC,
>> port)
>> #define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr) \
>> ((v->hdmi_irq_reg_base) + (addr))
>> @@ -139,12 +154,112 @@
>> (LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
>> LPAIF_WRDMA##reg##_REG(v, chan))
>> -#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v,
>> chan, dir, CTL, dai_id)
>> -#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v,
>> chan, dir, BASE, dai_id)
>> -#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id)
>> __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id)
>> -#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v,
>> chan, dir, CURR, dai_id)
>> -#define LPAIF_DMAPER_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v,
>> chan, dir, PER, dai_id)
>> -#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id)
>> __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id)
>> +#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) \
>> + (is_cdc_dma_port(dai_id) ? \
>> + __LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \
>> + __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id))
>> +#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) \
>> + (is_cdc_dma_port(dai_id) ? \
>> + __LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \
>> + __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id))
>> +#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) \
>> + (is_cdc_dma_port(dai_id) ? \
>> + __LPAIF_CDC_DMA_REG(v, chan, dir, BUFF, dai_id) : \
>> + __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id))
>> +#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) \
>> + (is_cdc_dma_port(dai_id) ? \
>> + __LPAIF_CDC_DMA_REG(v, chan, dir, CURR, dai_id) : \
>> + __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id))
>> +#define LPAIF_DMAPER_REG(v, chan, dir, dai_id) \
>> + (is_cdc_dma_port(dai_id) ? \
>> + __LPAIF_CDC_DMA_REG(v, chan, dir, PER, dai_id) : \
>> + __LPAIF_DMA_REG(v, chan, dir, PER, dai_id))
>> +#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) \
>> + (is_cdc_dma_port(dai_id) ? \
>> + __LPAIF_CDC_DMA_REG(v, chan, dir, PERCNT, dai_id) : \
>> + __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id))
>> +
>> +#define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, dai_id) \
>> + (is_rxtx_cdc_dma_port(dai_id) ? \
>> + (v->rxtx_rdma_reg_base + (addr) + v->rxtx_rdma_reg_stride *
>> (chan)) : \
>> + (v->va_rdma_reg_base + (addr) + v->va_rdma_reg_stride * (chan)))
>> +
>> +#define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, dai_id) \
>> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, dai_id) \
>> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, dai_id) \
>> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, dai_id) \
>> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, dai_id) \
>> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, dai_id) \
>> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
>> +
>> +#define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_id)
>> LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
>> +#define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai_id)
>> LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
>> +#define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai_id)
>> LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
>> +#define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai_id)
>> LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
>> +#define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_id)
>> LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
>> +#define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, dai_id) \
>> + LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
>> +
>> +#define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan, dai_id) \
>> + (is_rxtx_cdc_dma_port(dai_id) ? \
>> + (v->rxtx_wrdma_reg_base + (addr) + \
>> + v->rxtx_wrdma_reg_stride * (chan -
>> v->rxtx_wrdma_channel_start)) : \
>> + (v->va_wrdma_reg_base + (addr) + \
>> + v->va_wrdma_reg_stride * (chan - v->va_wrdma_channel_start)))
>> +
>> +#define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
>> +#define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
>> +
>> +#define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
>> +#define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
>> +#define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
>> +#define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
>> +#define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
>> +#define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, dai_id) \
>> + LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
>> +
>> +#define __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) \
>> + (is_rxtx_cdc_dma_port(dai_id) ?
>> LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \
>> + LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))
>> +
>> +#define __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id) \
>> + (is_rxtx_cdc_dma_port(dai_id) ?
>> LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \
>> + LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))
>> +
>> +#define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, dai_id) \
>> + ((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
>> + __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) : \
>> + __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id))
>> +
>> +#define LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) \
>> + ((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \
>> + LPAIF_CDC_RDMA_INTF_REG(v, chan, dai_id) : \
>> + LPAIF_CDC_WRDMA_INTF_REG(v, chan, dai_id))
>> +
>> +#define LPAIF_INTF_REG(v, chan, dir, dai_id) \
>> + (is_cdc_dma_port(dai_id) ? \
>> + LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) : \
>> + LPAIF_DMACTL_REG(v, chan, dir, dai_id))
>> #define LPAIF_DMACTL_BURSTEN_SINGLE 0
>> #define LPAIF_DMACTL_BURSTEN_INCR4 1
>>
--
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