Add driver for OpenCores PWM Controller. And add compatibility code
which based on StarFive SoC.
Co-developed-by: Hal Feng <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
Signed-off-by: William Qiu <[email protected]>
---
MAINTAINERS | 7 ++
drivers/pwm/Kconfig | 12 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-ocores.c | 229 +++++++++++++++++++++++++++++++++++++++
4 files changed, 249 insertions(+)
create mode 100644 drivers/pwm/pwm-ocores.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 788be9ab5b73..7a11a22da09e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16204,6 +16204,13 @@ F: Documentation/i2c/busses/i2c-ocores.rst
F: drivers/i2c/busses/i2c-ocores.c
F: include/linux/platform_data/i2c-ocores.h
+OPENCORES PWM DRIVER
+M: William Qiu <[email protected]>
+M: Hal Feng <[email protected]>
+S: Supported
+F: Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
+F: drivers/pwm/pwm-ocores.c
+
OPENRISC ARCHITECTURE
M: Jonas Bonn <[email protected]>
M: Stefan Kristiansson <[email protected]>
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 4b956d661755..d87e1bb350ba 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -444,6 +444,18 @@ config PWM_NTXEC
controller found in certain e-book readers designed by the original
design manufacturer Netronix.
+config PWM_OCORES
+ tristate "OpenCores PWM support"
+ depends on HAS_IOMEM && OF
+ depends on COMMON_CLK && RESET_CONTROLLER
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ help
+ If you say yes to this option, support will be included for the
+ OpenCores PWM. For details see https://opencores.org/projects/ptc.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-ocores.
+
config PWM_OMAP_DMTIMER
tristate "OMAP Dual-Mode Timer PWM support"
depends on OF
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index c5ec9e168ee7..517c4f643058 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o
obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o
+obj-$(CONFIG_PWM_OCORES) += pwm-ocores.o
obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o
obj-$(CONFIG_PWM_PXA) += pwm-pxa.o
diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c
new file mode 100644
index 000000000000..996ca3805901
--- /dev/null
+++ b/drivers/pwm/pwm-ocores.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * OpenCores PWM Driver
+ *
+ * https://opencores.org/projects/ptc
+ *
+ * Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
+ *
+ * Limitations:
+ * - The hardware only do inverted polarity.
+ * - The hardware minimum period / duty_cycle is (1 / pwm_apb clock frequency) ns.
+ * - The hardware maximum period / duty_cycle is (U32_MAX / pwm_apb clock frequency) ns.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+
+/* OCPWM_CTRL register bits*/
+#define REG_OCPWM_EN BIT(0)
+#define REG_OCPWM_ECLK BIT(1)
+#define REG_OCPWM_NEC BIT(2)
+#define REG_OCPWM_OE BIT(3)
+#define REG_OCPWM_SIGNLE BIT(4)
+#define REG_OCPWM_INTE BIT(5)
+#define REG_OCPWM_INT BIT(6)
+#define REG_OCPWM_CNTRRST BIT(7)
+#define REG_OCPWM_CAPTE BIT(8)
+
+struct ocores_pwm_device {
+ struct pwm_chip chip;
+ struct clk *clk;
+ struct reset_control *rst;
+ const struct ocores_pwm_data *data;
+ void __iomem *regs;
+ u32 clk_rate; /* PWM APB clock frequency */
+};
+
+struct ocores_pwm_data {
+ void __iomem *(*get_ch_base)(void __iomem *base, unsigned int channel);
+};
+
+static inline u32 ocores_readl(struct ocores_pwm_device *ddata,
+ unsigned int channel,
+ unsigned int offset)
+{
+ void __iomem *base = ddata->data->get_ch_base ?
+ ddata->data->get_ch_base(ddata->regs, channel) : ddata->regs;
+
+ return readl(base + offset);
+}
+
+static inline void ocores_writel(struct ocores_pwm_device *ddata,
+ unsigned int channel,
+ unsigned int offset, u32 val)
+{
+ void __iomem *base = ddata->data->get_ch_base ?
+ ddata->data->get_ch_base(ddata->regs, channel) : ddata->regs;
+
+ writel(val, base + offset);
+}
+
+static inline struct ocores_pwm_device *chip_to_ocores(struct pwm_chip *chip)
+{
+ return container_of(chip, struct ocores_pwm_device, chip);
+}
+
+static void __iomem *starfive_jh71x0_get_ch_base(void __iomem *base,
+ unsigned int channel)
+{
+ unsigned int offset = (channel > 3 ? 1 << 15 : 0) + (channel & 3) * 0x10;
+
+ return base + offset;
+}
+
+static int ocores_pwm_get_state(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct ocores_pwm_device *ddata = chip_to_ocores(chip);
+ u32 period_data, duty_data, ctrl_data;
+
+ period_data = ocores_readl(ddata, pwm->hwpwm, 0x8);
+ duty_data = ocores_readl(ddata, pwm->hwpwm, 0x4);
+ ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC);
+
+ state->period = DIV_ROUND_UP_ULL((u64)period_data * NSEC_PER_SEC, ddata->clk_rate);
+ state->duty_cycle = DIV_ROUND_UP_ULL((u64)duty_data * NSEC_PER_SEC, ddata->clk_rate);
+ state->polarity = PWM_POLARITY_INVERSED;
+ state->enabled = (ctrl_data & REG_OCPWM_EN) ? true : false;
+
+ return 0;
+}
+
+static int ocores_pwm_apply(struct pwm_chip *chip,
+ struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct ocores_pwm_device *ddata = chip_to_ocores(chip);
+ u32 ctrl_data = 0;
+ u64 period_data, duty_data;
+
+ if (state->polarity != PWM_POLARITY_INVERSED)
+ return -EINVAL;
+
+ ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC);
+ ocores_writel(ddata, pwm->hwpwm, 0xC, 0);
+
+ period_data = DIV_ROUND_DOWN_ULL(state->period * ddata->clk_rate, NSEC_PER_SEC);
+ if (period_data <= U32_MAX)
+ ocores_writel(ddata, pwm->hwpwm, 0x8, (u32)period_data);
+ else
+ return -EINVAL;
+
+ duty_data = DIV_ROUND_DOWN_ULL(state->duty_cycle * ddata->clk_rate, NSEC_PER_SEC);
+ if (duty_data <= U32_MAX)
+ ocores_writel(ddata, pwm->hwpwm, 0x4, (u32)duty_data);
+ else
+ return -EINVAL;
+
+ ocores_writel(ddata, pwm->hwpwm, 0xC, 0);
+
+ if (state->enabled) {
+ ctrl_data = ocores_readl(ddata, pwm->hwpwm, 0xC);
+ ocores_writel(ddata, pwm->hwpwm, 0xC, ctrl_data | REG_OCPWM_EN | REG_OCPWM_OE);
+ }
+
+ return 0;
+}
+
+static const struct pwm_ops ocores_pwm_ops = {
+ .get_state = ocores_pwm_get_state,
+ .apply = ocores_pwm_apply,
+};
+
+static const struct ocores_pwm_data jh7100_pwm_data = {
+ .get_ch_base = starfive_jh71x0_get_ch_base,
+};
+
+static const struct ocores_pwm_data jh7110_pwm_data = {
+ .get_ch_base = starfive_jh71x0_get_ch_base,
+};
+
+static const struct of_device_id ocores_pwm_of_match[] = {
+ { .compatible = "opencores,pwm-v1" },
+ { .compatible = "starfive,jh7100-pwm", .data = &jh7100_pwm_data},
+ { .compatible = "starfive,jh7110-pwm", .data = &jh7110_pwm_data},
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ocores_pwm_of_match);
+
+static void ocores_reset_control_assert(void *data)
+{
+ reset_control_assert(data);
+}
+
+static int ocores_pwm_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *id;
+ struct device *dev = &pdev->dev;
+ struct ocores_pwm_device *ddata;
+ struct pwm_chip *chip;
+ int ret;
+
+ id = of_match_device(ocores_pwm_of_match, dev);
+ if (!id)
+ return -EINVAL;
+
+ ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
+ if (!ddata)
+ return -ENOMEM;
+
+ ddata->data = id->data;
+ chip = &ddata->chip;
+ chip->dev = dev;
+ chip->ops = &ocores_pwm_ops;
+ chip->npwm = 8;
+ chip->of_pwm_n_cells = 3;
+
+ ddata->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(ddata->regs))
+ return dev_err_probe(dev, PTR_ERR(ddata->regs),
+ "Unable to map IO resources\n");
+
+ ddata->clk = devm_clk_get_enabled(dev, NULL);
+ if (IS_ERR(ddata->clk))
+ return dev_err_probe(dev, PTR_ERR(ddata->clk),
+ "Unable to get pwm's clock\n");
+
+ ddata->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
+ reset_control_deassert(ddata->rst);
+
+ ret = devm_add_action_or_reset(dev, ocores_reset_control_assert, ddata->rst);
+ if (ret)
+ return ret;
+
+ ddata->clk_rate = clk_get_rate(ddata->clk);
+ if (ddata->clk_rate <= 0)
+ return dev_err_probe(dev, ddata->clk_rate,
+ "Unable to get clock's rate\n");
+
+ ret = devm_pwmchip_add(dev, chip);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Could not register PWM chip\n");
+
+ platform_set_drvdata(pdev, ddata);
+
+ return ret;
+}
+
+static struct platform_driver ocores_pwm_driver = {
+ .probe = ocores_pwm_probe,
+ .driver = {
+ .name = "ocores-pwm",
+ .of_match_table = ocores_pwm_of_match,
+ },
+};
+module_platform_driver(ocores_pwm_driver);
+
+MODULE_AUTHOR("Jieqin Chen");
+MODULE_AUTHOR("Hal Feng <[email protected]>");
+MODULE_DESCRIPTION("OpenCores PWM PTC driver");
+MODULE_LICENSE("GPL");
--
2.34.1
Hi William,
On Fr, 2023-12-08 at 17:42 +0800, William Qiu wrote:
> Add driver for OpenCores PWM Controller. And add compatibility code
> which based on StarFive SoC.
>
> Co-developed-by: Hal Feng <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> Signed-off-by: William Qiu <[email protected]>
> ---
[...]
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 4b956d661755..d87e1bb350ba 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -444,6 +444,18 @@ config PWM_NTXEC
> controller found in certain e-book readers designed by the original
> design manufacturer Netronix.
>
> +config PWM_OCORES
> + tristate "OpenCores PWM support"
> + depends on HAS_IOMEM && OF
> + depends on COMMON_CLK && RESET_CONTROLLER
There is no need for reset consumers to depend on RESET_CONTROLLER.
[...]
> diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c
> new file mode 100644
> index 000000000000..996ca3805901
> --- /dev/null
> +++ b/drivers/pwm/pwm-ocores.c
> @@ -0,0 +1,229 @@
[...]
> +static int ocores_pwm_probe(struct platform_device *pdev)
> +{
[...]
> + ddata->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
Missing error handling.
> + reset_control_deassert(ddata->rst);
Missing error handling.
regards
Philipp
On Fri, Dec 8, 2023 at 3:42 AM William Qiu <[email protected]> wrote:
>
> Add driver for OpenCores PWM Controller. And add compatibility code
> which based on StarFive SoC.
>
> Co-developed-by: Hal Feng <[email protected]>
> Signed-off-by: Hal Feng <[email protected]>
> Signed-off-by: William Qiu <[email protected]>
> ---
> MAINTAINERS | 7 ++
> drivers/pwm/Kconfig | 12 ++
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-ocores.c | 229 +++++++++++++++++++++++++++++++++++++++
> 4 files changed, 249 insertions(+)
> create mode 100644 drivers/pwm/pwm-ocores.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 788be9ab5b73..7a11a22da09e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -16204,6 +16204,13 @@ F: Documentation/i2c/busses/i2c-ocores.rst
> F: drivers/i2c/busses/i2c-ocores.c
> F: include/linux/platform_data/i2c-ocores.h
>
> +OPENCORES PWM DRIVER
> +M: William Qiu <[email protected]>
> +M: Hal Feng <[email protected]>
> +S: Supported
> +F: Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
> +F: drivers/pwm/pwm-ocores.c
> +
> OPENRISC ARCHITECTURE
> M: Jonas Bonn <[email protected]>
> M: Stefan Kristiansson <[email protected]>
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 4b956d661755..d87e1bb350ba 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -444,6 +444,18 @@ config PWM_NTXEC
> controller found in certain e-book readers designed by the original
> design manufacturer Netronix.
>
> +config PWM_OCORES
> + tristate "OpenCores PWM support"
> + depends on HAS_IOMEM && OF
> + depends on COMMON_CLK && RESET_CONTROLLER
> + depends on ARCH_STARFIVE || COMPILE_TEST
> + help
> + If you say yes to this option, support will be included for the
> + OpenCores PWM. For details see https://opencores.org/projects/ptc.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called pwm-ocores.
> +
> config PWM_OMAP_DMTIMER
> tristate "OMAP Dual-Mode Timer PWM support"
> depends on OF
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index c5ec9e168ee7..517c4f643058 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -40,6 +40,7 @@ obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o
> obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
> obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
> obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o
> +obj-$(CONFIG_PWM_OCORES) += pwm-ocores.o
> obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
> obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o
> obj-$(CONFIG_PWM_PXA) += pwm-pxa.o
> diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c
> new file mode 100644
> index 000000000000..996ca3805901
> --- /dev/null
> +++ b/drivers/pwm/pwm-ocores.c
> @@ -0,0 +1,229 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * OpenCores PWM Driver
> + *
> + * https://opencores.org/projects/ptc
> + *
> + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
> + *
> + * Limitations:
> + * - The hardware only do inverted polarity.
> + * - The hardware minimum period / duty_cycle is (1 / pwm_apb clock frequency) ns.
> + * - The hardware maximum period / duty_cycle is (U32_MAX / pwm_apb clock frequency) ns.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
You probably don't need this header and the implicit includes it makes
are dropped now in linux-next. Please check what you actually need and
make them explicit.
Rob
On 2023/12/8 19:47, Philipp Zabel wrote:
> Hi William,
>
> On Fr, 2023-12-08 at 17:42 +0800, William Qiu wrote:
>> Add driver for OpenCores PWM Controller. And add compatibility code
>> which based on StarFive SoC.
>>
>> Co-developed-by: Hal Feng <[email protected]>
>> Signed-off-by: Hal Feng <[email protected]>
>> Signed-off-by: William Qiu <[email protected]>
>> ---
> [...]
>> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
>> index 4b956d661755..d87e1bb350ba 100644
>> --- a/drivers/pwm/Kconfig
>> +++ b/drivers/pwm/Kconfig
>> @@ -444,6 +444,18 @@ config PWM_NTXEC
>> controller found in certain e-book readers designed by the original
>> design manufacturer Netronix.
>>
>> +config PWM_OCORES
>> + tristate "OpenCores PWM support"
>> + depends on HAS_IOMEM && OF
>> + depends on COMMON_CLK && RESET_CONTROLLER
>
> There is no need for reset consumers to depend on RESET_CONTROLLER.
>
Will drop
> [...]
>> diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c
>> new file mode 100644
>> index 000000000000..996ca3805901
>> --- /dev/null
>> +++ b/drivers/pwm/pwm-ocores.c
>> @@ -0,0 +1,229 @@
> [...]
>> +static int ocores_pwm_probe(struct platform_device *pdev)
>> +{
> [...]
>> + ddata->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
>
> Missing error handling.
>
Will add.
>> + reset_control_deassert(ddata->rst);
>
> Missing error handling.
>
Will add.
>
Thank you for spending time on this patch series.
Best Regards,
William
> regards
> Philipp
On 2023/12/12 1:41, Rob Herring wrote:
> On Fri, Dec 8, 2023 at 3:42 AM William Qiu <[email protected]> wrote:
>>
>> Add driver for OpenCores PWM Controller. And add compatibility code
>> which based on StarFive SoC.
>>
>> Co-developed-by: Hal Feng <[email protected]>
>> Signed-off-by: Hal Feng <[email protected]>
>> Signed-off-by: William Qiu <[email protected]>
>> ---
>> MAINTAINERS | 7 ++
>> drivers/pwm/Kconfig | 12 ++
>> drivers/pwm/Makefile | 1 +
>> drivers/pwm/pwm-ocores.c | 229 +++++++++++++++++++++++++++++++++++++++
>> 4 files changed, 249 insertions(+)
>> create mode 100644 drivers/pwm/pwm-ocores.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 788be9ab5b73..7a11a22da09e 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -16204,6 +16204,13 @@ F: Documentation/i2c/busses/i2c-ocores.rst
>> F: drivers/i2c/busses/i2c-ocores.c
>> F: include/linux/platform_data/i2c-ocores.h
>>
>> +OPENCORES PWM DRIVER
>> +M: William Qiu <[email protected]>
>> +M: Hal Feng <[email protected]>
>> +S: Supported
>> +F: Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
>> +F: drivers/pwm/pwm-ocores.c
>> +
>> OPENRISC ARCHITECTURE
>> M: Jonas Bonn <[email protected]>
>> M: Stefan Kristiansson <[email protected]>
>> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
>> index 4b956d661755..d87e1bb350ba 100644
>> --- a/drivers/pwm/Kconfig
>> +++ b/drivers/pwm/Kconfig
>> @@ -444,6 +444,18 @@ config PWM_NTXEC
>> controller found in certain e-book readers designed by the original
>> design manufacturer Netronix.
>>
>> +config PWM_OCORES
>> + tristate "OpenCores PWM support"
>> + depends on HAS_IOMEM && OF
>> + depends on COMMON_CLK && RESET_CONTROLLER
>> + depends on ARCH_STARFIVE || COMPILE_TEST
>> + help
>> + If you say yes to this option, support will be included for the
>> + OpenCores PWM. For details see https://opencores.org/projects/ptc.
>> +
>> + To compile this driver as a module, choose M here: the module
>> + will be called pwm-ocores.
>> +
>> config PWM_OMAP_DMTIMER
>> tristate "OMAP Dual-Mode Timer PWM support"
>> depends on OF
>> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
>> index c5ec9e168ee7..517c4f643058 100644
>> --- a/drivers/pwm/Makefile
>> +++ b/drivers/pwm/Makefile
>> @@ -40,6 +40,7 @@ obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o
>> obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
>> obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
>> obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o
>> +obj-$(CONFIG_PWM_OCORES) += pwm-ocores.o
>> obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
>> obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o
>> obj-$(CONFIG_PWM_PXA) += pwm-pxa.o
>> diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c
>> new file mode 100644
>> index 000000000000..996ca3805901
>> --- /dev/null
>> +++ b/drivers/pwm/pwm-ocores.c
>> @@ -0,0 +1,229 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * OpenCores PWM Driver
>> + *
>> + * https://opencores.org/projects/ptc
>> + *
>> + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
>> + *
>> + * Limitations:
>> + * - The hardware only do inverted polarity.
>> + * - The hardware minimum period / duty_cycle is (1 / pwm_apb clock frequency) ns.
>> + * - The hardware maximum period / duty_cycle is (U32_MAX / pwm_apb clock frequency) ns.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>
> You probably don't need this header and the implicit includes it makes
> are dropped now in linux-next. Please check what you actually need and
> make them explicit.
>
> Rob
Will drop.
Thank you for spending time on this patchset.
Best Regards
William
On 2023/12/13 17:27, William Qiu wrote:
>
>
> On 2023/12/12 1:41, Rob Herring wrote:
>> On Fri, Dec 8, 2023 at 3:42 AM William Qiu <[email protected]> wrote:
>>>
>>> Add driver for OpenCores PWM Controller. And add compatibility code
>>> which based on StarFive SoC.
>>>
>>> Co-developed-by: Hal Feng <[email protected]>
>>> Signed-off-by: Hal Feng <[email protected]>
>>> Signed-off-by: William Qiu <[email protected]>
>>> ---
>>> MAINTAINERS | 7 ++
>>> drivers/pwm/Kconfig | 12 ++
>>> drivers/pwm/Makefile | 1 +
>>> drivers/pwm/pwm-ocores.c | 229 +++++++++++++++++++++++++++++++++++++++
>>> 4 files changed, 249 insertions(+)
>>> create mode 100644 drivers/pwm/pwm-ocores.c
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index 788be9ab5b73..7a11a22da09e 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -16204,6 +16204,13 @@ F: Documentation/i2c/busses/i2c-ocores.rst
>>> F: drivers/i2c/busses/i2c-ocores.c
>>> F: include/linux/platform_data/i2c-ocores.h
>>>
>>> +OPENCORES PWM DRIVER
>>> +M: William Qiu <[email protected]>
>>> +M: Hal Feng <[email protected]>
>>> +S: Supported
>>> +F: Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
>>> +F: drivers/pwm/pwm-ocores.c
>>> +
>>> OPENRISC ARCHITECTURE
>>> M: Jonas Bonn <[email protected]>
>>> M: Stefan Kristiansson <[email protected]>
>>> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
>>> index 4b956d661755..d87e1bb350ba 100644
>>> --- a/drivers/pwm/Kconfig
>>> +++ b/drivers/pwm/Kconfig
>>> @@ -444,6 +444,18 @@ config PWM_NTXEC
>>> controller found in certain e-book readers designed by the original
>>> design manufacturer Netronix.
>>>
>>> +config PWM_OCORES
>>> + tristate "OpenCores PWM support"
>>> + depends on HAS_IOMEM && OF
>>> + depends on COMMON_CLK && RESET_CONTROLLER
>>> + depends on ARCH_STARFIVE || COMPILE_TEST
>>> + help
>>> + If you say yes to this option, support will be included for the
>>> + OpenCores PWM. For details see https://opencores.org/projects/ptc.
>>> +
>>> + To compile this driver as a module, choose M here: the module
>>> + will be called pwm-ocores.
>>> +
>>> config PWM_OMAP_DMTIMER
>>> tristate "OMAP Dual-Mode Timer PWM support"
>>> depends on OF
>>> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
>>> index c5ec9e168ee7..517c4f643058 100644
>>> --- a/drivers/pwm/Makefile
>>> +++ b/drivers/pwm/Makefile
>>> @@ -40,6 +40,7 @@ obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o
>>> obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
>>> obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
>>> obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o
>>> +obj-$(CONFIG_PWM_OCORES) += pwm-ocores.o
>>> obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
>>> obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o
>>> obj-$(CONFIG_PWM_PXA) += pwm-pxa.o
>>> diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c
>>> new file mode 100644
>>> index 000000000000..996ca3805901
>>> --- /dev/null
>>> +++ b/drivers/pwm/pwm-ocores.c
>>> @@ -0,0 +1,229 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * OpenCores PWM Driver
>>> + *
>>> + * https://opencores.org/projects/ptc
>>> + *
>>> + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd.
>>> + *
>>> + * Limitations:
>>> + * - The hardware only do inverted polarity.
>>> + * - The hardware minimum period / duty_cycle is (1 / pwm_apb clock frequency) ns.
>>> + * - The hardware maximum period / duty_cycle is (U32_MAX / pwm_apb clock frequency) ns.
>>> + */
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/io.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_device.h>
>>
>> You probably don't need this header and the implicit includes it makes
>> are dropped now in linux-next. Please check what you actually need and
>> make them explicit.
>>
>> Rob
> Will drop.
>
> Thank you for spending time on this patchset.
>
> Best Regards
> William
Hi Rob,
After checking, I need to use of_match_device() in of_device.h, so this
interface will be moved to which header in linux-next?
Thanks,
William