From: Shiju Jose <[email protected]>
1. Add support for CXL feature mailbox commands.
2. Add CXL device scrub driver supporting patrol scrub control and DDR5 ECS
control features.
3. Add scrub driver supports configuring memory scrubs in the system.
4. Add scrub attributes for DDR5 ECS control to the memory scrub driver.
5. Register CXL device patrol scrub and ECS with scrub control driver.
6. Add documentation for common attributes in the scrub configure driver.
7. Add documentation for CXL memory device scrub control attributes.
Changes
v3 -> v4:
1. Fixes for the warnings/errors reported by kernel test robot.
2. Add support for reading the 'enable' attribute of CXL patrol scrub.
Changes
v2 -> v3:
1. Changes for comments from Davidlohr, Thanks.
- Updated cxl scrub kconfig
- removed usage of the flag is_support_feature from
the function cxl_mem_get_supported_feature_entry().
- corrected spelling error.
- removed unnecessary debug message.
- removed export feature commands to the userspace.
2. Possible fix for the warnings/errors reported by kernel
test robot.
3. Add documentation for the common scrub configure atrributes.
v1 -> v2:
1. Changes for comments from Dave Jiang, Thanks.
- Split patches.
- reversed xmas tree declarations.
- declared flags as enums.
- removed few unnecessary variable initializations.
- replaced PTR_ERR_OR_ZERO() with IS_ERR() and PTR_ERR().
- add auto clean declarations.
- replaced while loop with for loop.
- Removed allocation from cxl_get_supported_features() and
cxl_get_feature() and make change to take allocated memory
pointer from the caller.
- replaced if/else with switch case.
- replaced sprintf() with sysfs_emit() in 2 places.
- replaced goto label with return in few functions.
2. removed unused code for supported attributes from ecs.
3. Included following common patch for scrub configure driver
to this series.
"memory: scrub: Add scrub driver supports configuring memory scrubbers
in the system"
Shiju Jose (11):
cxl/mbox: Add GET_SUPPORTED_FEATURES mailbox command
cxl/mbox: Add GET_FEATURE mailbox command
cxl/mbox: Add SET_FEATURE mailbox command
cxl/memscrub: Add CXL device patrol scrub control feature
cxl/memscrub: Add CXL device DDR5 ECS control feature
memory: scrub: Add scrub driver supports configuring memory scrubs in
the system
cxl/memscrub: Register CXL device patrol scrub with scrub configure
driver
memory: scrub: Add scrub control attributes for the DDR5 ECS
cxl/memscrub: Register CXL device DDR5 ECS with scrub configure driver
memory: scrub: sysfs: Add Documentation for set of common scrub
attributes
cxl: scrub: sysfs: Add Documentation for CXL memory device scrub
control attributes
.../testing/sysfs-class-cxl-scrub-configure | 79 ++
.../ABI/testing/sysfs-class-scrub-configure | 82 ++
drivers/cxl/Kconfig | 23 +
drivers/cxl/core/Makefile | 1 +
drivers/cxl/core/mbox.c | 59 +
drivers/cxl/core/memscrub.c | 1002 +++++++++++++++++
drivers/cxl/cxlmem.h | 120 ++
drivers/cxl/pci.c | 6 +
drivers/memory/Kconfig | 1 +
drivers/memory/Makefile | 1 +
drivers/memory/scrub/Kconfig | 11 +
drivers/memory/scrub/Makefile | 6 +
drivers/memory/scrub/memory-scrub.c | 481 ++++++++
include/memory/memory-scrub.h | 90 ++
14 files changed, 1962 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-class-cxl-scrub-configure
create mode 100644 Documentation/ABI/testing/sysfs-class-scrub-configure
create mode 100644 drivers/cxl/core/memscrub.c
create mode 100644 drivers/memory/scrub/Kconfig
create mode 100644 drivers/memory/scrub/Makefile
create mode 100755 drivers/memory/scrub/memory-scrub.c
create mode 100755 include/memory/memory-scrub.h
--
2.34.1
From: Shiju Jose <[email protected]>
Add scrub control attributes for the DDR5 ECS feature.
The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
Specification (JESD79-5) and allows the DRAM to internally read, correct
single-bit errors, and write back corrected data bits to the DRAM array
while providing transparency to error counts. The ECS control feature
allows the request to configure ECS input configurations during system
boot or at run-time.
The ECS control allows the requester to change the ECS threshold count
provided that the request is within the definition specified in DDR5 mode
registers, change mode between codeword mode and row count mode, and reset
the ECS counter.
Signed-off-by: Shiju Jose <[email protected]>
---
drivers/memory/scrub/memory-scrub.c | 13 ++++++++++++-
include/memory/memory-scrub.h | 10 ++++++++++
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/scrub/memory-scrub.c b/drivers/memory/scrub/memory-scrub.c
index c2d794b2624b..43b7da43114f 100755
--- a/drivers/memory/scrub/memory-scrub.c
+++ b/drivers/memory/scrub/memory-scrub.c
@@ -208,7 +208,8 @@ static bool is_hex_attr(u32 attr)
static bool is_string_attr(u32 attr)
{
- return attr == scrub_speed_available;
+ return attr == scrub_speed_available ||
+ attr == scrub_threshold_available;
}
static struct attribute *scrub_genattr(const void *drvdata,
@@ -269,6 +270,16 @@ static const char * const scrub_common_attrs[] = {
[scrub_enable] = "enable",
[scrub_speed] = "speed",
[scrub_speed_available] = "speed_available",
+ /* scrub attributes - DDR5 ECS/common */
+ [scrub_ecs_log_entry_type] = "ecs_log_entry_type",
+ [scrub_ecs_log_entry_type_per_dram] = "ecs_log_entry_type_per_dram",
+ [scrub_ecs_log_entry_type_per_memory_media] = "ecs_log_entry_type_per_memory_media",
+ [scrub_mode] = "mode",
+ [scrub_mode_counts_rows] = "mode_counts_rows",
+ [scrub_mode_counts_codewords] = "mode_counts_codewords",
+ [scrub_reset_counter] = "reset_counter",
+ [scrub_threshold] = "threshold",
+ [scrub_threshold_available] = "threshold_available",
};
static struct attribute **
diff --git a/include/memory/memory-scrub.h b/include/memory/memory-scrub.h
index d7cbde4718d0..74ad5addd5b3 100755
--- a/include/memory/memory-scrub.h
+++ b/include/memory/memory-scrub.h
@@ -23,6 +23,16 @@ enum scrub_attributes {
scrub_enable,
scrub_speed,
scrub_speed_available,
+ /* scrub attributes - DDR5 ECS/common */
+ scrub_ecs_log_entry_type,
+ scrub_ecs_log_entry_type_per_dram,
+ scrub_ecs_log_entry_type_per_memory_media,
+ scrub_mode,
+ scrub_mode_counts_rows,
+ scrub_mode_counts_codewords,
+ scrub_reset_counter,
+ scrub_threshold,
+ scrub_threshold_available,
max_attrs,
};
--
2.34.1
From: Shiju Jose <[email protected]>
Add support for GET_FEATURE mailbox command.
CXL spec 3.0 section 8.2.9.6 describes optional device specific features.
The settings of a feature can be retrieved using Get Feature command.
Signed-off-by: Shiju Jose <[email protected]>
---
drivers/cxl/core/mbox.c | 22 ++++++++++++++++++++++
drivers/cxl/cxlmem.h | 23 +++++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index 6960ce935e73..a50c874edebc 100644
--- a/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@ -1326,6 +1326,28 @@ int cxl_get_supported_features(struct cxl_memdev_state *mds,
}
EXPORT_SYMBOL_NS_GPL(cxl_get_supported_features, CXL);
+int cxl_get_feature(struct cxl_memdev_state *mds,
+ struct cxl_mbox_get_feat_in *pi, void *feat_out)
+{
+ struct cxl_mbox_cmd mbox_cmd;
+ int rc;
+
+ mbox_cmd = (struct cxl_mbox_cmd) {
+ .opcode = CXL_MBOX_OP_GET_FEATURE,
+ .size_in = sizeof(*pi),
+ .payload_in = pi,
+ .size_out = le16_to_cpu(pi->count),
+ .payload_out = feat_out,
+ .min_out = le16_to_cpu(pi->count),
+ };
+ rc = cxl_internal_send_cmd(mds, &mbox_cmd);
+ if (rc < 0)
+ return rc;
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_get_feature, CXL);
+
int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
struct cxl_region *cxlr)
{
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index d831dad748f5..92c1f2a44713 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -507,6 +507,7 @@ enum cxl_opcode {
CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400,
CXL_MBOX_OP_GET_LOG = 0x0401,
CXL_MBOX_OP_GET_SUPPORTED_FEATURES = 0x0500,
+ CXL_MBOX_OP_GET_FEATURE = 0x0501,
CXL_MBOX_OP_IDENTIFY = 0x4000,
CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
@@ -796,6 +797,26 @@ struct cxl_mbox_get_supp_feats_out {
struct cxl_mbox_supp_feat_entry feat_entries[];
} __packed;
+/* Get Feature CXL 3.0 Spec 8.2.9.6.2 */
+/*
+ * Get Feature input payload
+ * CXL rev 3.0 section 8.2.9.6.2; Table 8-79
+ */
+/* Get Feature : Payload in selection */
+enum cxl_get_feat_selection {
+ CXL_GET_FEAT_SEL_CURRENT_VALUE = 0x0,
+ CXL_GET_FEAT_SEL_DEFAULT_VALUE = 0x1,
+ CXL_GET_FEAT_SEL_SAVED_VALUE = 0x2,
+ CXL_GET_FEAT_SEL_MAX
+};
+
+struct cxl_mbox_get_feat_in {
+ uuid_t uuid;
+ __le16 offset;
+ __le16 count;
+ u8 selection;
+} __packed;
+
/* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */
struct cxl_mbox_poison_in {
__le64 offset;
@@ -926,6 +947,8 @@ int cxl_set_timestamp(struct cxl_memdev_state *mds);
int cxl_get_supported_features(struct cxl_memdev_state *mds,
struct cxl_mbox_get_supp_feats_in *pi,
void *feats_out);
+int cxl_get_feature(struct cxl_memdev_state *mds,
+ struct cxl_mbox_get_feat_in *pi, void *feat_out);
int cxl_poison_state_init(struct cxl_memdev_state *mds);
int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
struct cxl_region *cxlr);
--
2.34.1
From: Shiju Jose <[email protected]>
Register with the scrub configure driver to expose the sysfs attributes
to the user for configuring the CXL memory device's ECS feature. Add
the callback functions to support configuring the CXL memory device ECS.
Signed-off-by: Shiju Jose <[email protected]>
---
drivers/cxl/core/memscrub.c | 239 +++++++++++++++++++++++++++++++++++-
1 file changed, 236 insertions(+), 3 deletions(-)
diff --git a/drivers/cxl/core/memscrub.c b/drivers/cxl/core/memscrub.c
index 4d778ffa3322..f1273615bbdd 100644
--- a/drivers/cxl/core/memscrub.c
+++ b/drivers/cxl/core/memscrub.c
@@ -473,6 +473,11 @@ EXPORT_SYMBOL_NS_GPL(cxl_mem_patrol_scrub_init, CXL);
#define CXL_MEMDEV_ECS_GET_FEAT_VERSION 0x01
#define CXL_MEMDEV_ECS_SET_FEAT_VERSION 0x01
+#define CXL_DDR5_ECS "cxl_ecs"
+
+/* The default number of regions for CXL memory device ECS */
+#define CXL_MEMDEV_ECS_NUM_REGIONS 1
+
static const uuid_t cxl_ecs_uuid =
UUID_INIT(0xe5b13f22, 0x2328, 0x4a14, 0xb8, 0xba, 0xb9, 0x69, 0x1e, \
0x89, 0x33, 0x86);
@@ -590,9 +595,8 @@ static int cxl_mem_ecs_get_attrbs(struct device *dev, int fru_id,
return 0;
}
-static int __maybe_unused
-cxl_mem_ecs_set_attrbs(struct device *dev, int fru_id,
- struct cxl_memdev_ecs_params *params, u8 param_type)
+static int cxl_mem_ecs_set_attrbs(struct device *dev, int fru_id,
+ struct cxl_memdev_ecs_params *params, u8 param_type)
{
struct cxl_memdev_ecs_feat_read_attrbs *rd_attrbs __free(kvfree) = NULL;
struct cxl_memdev_ecs_set_feat_pi *set_pi __free(kvfree) = NULL;
@@ -739,10 +743,231 @@ cxl_mem_ecs_set_attrbs(struct device *dev, int fru_id,
return 0;
}
+static int cxl_mem_ecs_log_entry_type_write(struct device *dev, int region_id, long val)
+{
+ struct cxl_memdev_ecs_params params;
+ int ret;
+
+ params.log_entry_type = val;
+ ret = cxl_mem_ecs_set_attrbs(dev, region_id, ¶ms,
+ CXL_MEMDEV_ECS_PARAM_LOG_ENTRY_TYPE);
+ if (ret) {
+ dev_err(dev->parent, "Set CXL ECS params for log entry type fail ret=%d\n",
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cxl_mem_ecs_threshold_write(struct device *dev, int region_id, long val)
+{
+ struct cxl_memdev_ecs_params params;
+ int ret;
+
+ params.threshold = val;
+ ret = cxl_mem_ecs_set_attrbs(dev, region_id, ¶ms,
+ CXL_MEMDEV_ECS_PARAM_THRESHOLD);
+ if (ret) {
+ dev_err(dev->parent, "Set CXL ECS params for threshold fail ret=%d\n",
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cxl_mem_ecs_mode_write(struct device *dev, int region_id, long val)
+{
+ struct cxl_memdev_ecs_params params;
+ int ret;
+
+ params.mode = val;
+ ret = cxl_mem_ecs_set_attrbs(dev, region_id, ¶ms,
+ CXL_MEMDEV_ECS_PARAM_MODE);
+ if (ret) {
+ dev_err(dev->parent, "Set CXL ECS params for mode fail ret=%d\n",
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cxl_mem_ecs_reset_counter_write(struct device *dev, int region_id, long val)
+{
+ struct cxl_memdev_ecs_params params;
+ int ret;
+
+ params.reset_counter = val;
+ ret = cxl_mem_ecs_set_attrbs(dev, region_id, ¶ms,
+ CXL_MEMDEV_ECS_PARAM_RESET_COUNTER);
+ if (ret) {
+ dev_err(dev->parent, "Set CXL ECS params for reset ECC counter fail ret=%d\n",
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * cxl_mem_ecs_is_visible() - Callback to return attribute visibility
+ * @drv_data: Pointer to driver-private data structure passed
+ * as argument to devm_scrub_device_register().
+ * @attr: Scrub attribute
+ * @region_id: ID of the memory region
+ *
+ * Returns: 0 on success, an error otherwise
+ */
+static umode_t cxl_mem_ecs_is_visible(const void *drv_data, u32 attr, int region_id)
+{
+ switch (attr) {
+ case scrub_reset_counter:
+ return 0200;
+ case scrub_ecs_log_entry_type_per_dram:
+ case scrub_ecs_log_entry_type_per_memory_media:
+ case scrub_mode_counts_rows:
+ case scrub_mode_counts_codewords:
+ case scrub_threshold_available:
+ return 0444;
+ case scrub_ecs_log_entry_type:
+ case scrub_mode:
+ case scrub_threshold:
+ return 0644;
+ default:
+ return 0;
+ }
+}
+
+/**
+ * cxl_mem_ecs_read() - Read callback for data attributes
+ * @dev: Pointer to scrub device
+ * @attr: Scrub attribute
+ * @region_id: ID of the memory region
+ * @val: Pointer to the returned data
+ *
+ * Returns: 0 on success, an error otherwise
+ */
+static int cxl_mem_ecs_read(struct device *dev, u32 attr, int region_id, u64 *val)
+{
+ struct cxl_memdev_ecs_params params;
+ int ret;
+
+ if (attr == scrub_ecs_log_entry_type ||
+ attr == scrub_ecs_log_entry_type_per_dram ||
+ attr == scrub_ecs_log_entry_type_per_memory_media ||
+ attr == scrub_mode ||
+ attr == scrub_mode_counts_rows ||
+ attr == scrub_mode_counts_codewords ||
+ attr == scrub_threshold) {
+ ret = cxl_mem_ecs_get_attrbs(dev, region_id, ¶ms);
+ if (ret) {
+ dev_err(dev->parent, "Get CXL ECS params fail ret=%d\n", ret);
+ return ret;
+ }
+ }
+
+ switch (attr) {
+ case scrub_ecs_log_entry_type:
+ *val = params.log_entry_type;
+ break;
+ case scrub_ecs_log_entry_type_per_dram:
+ if (params.log_entry_type == ECS_LOG_ENTRY_TYPE_DRAM)
+ *val = 1;
+ else
+ *val = 0;
+ break;
+ case scrub_ecs_log_entry_type_per_memory_media:
+ if (params.log_entry_type == ECS_LOG_ENTRY_TYPE_MEM_MEDIA_FRU)
+ *val = 1;
+ else
+ *val = 0;
+ break;
+ case scrub_mode:
+ *val = params.mode;
+ break;
+ case scrub_mode_counts_rows:
+ if (params.mode == ECS_MODE_COUNTS_ROWS)
+ *val = 1;
+ else
+ *val = 0;
+ break;
+ case scrub_mode_counts_codewords:
+ if (params.mode == ECS_MODE_COUNTS_CODEWORDS)
+ *val = 1;
+ else
+ *val = 0;
+ break;
+ case scrub_threshold:
+ *val = params.threshold;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ return 0;
+}
+
+/**
+ * cxl_mem_ecs_write() - Write callback for data attributes
+ * @dev: Pointer to scrub device
+ * @attr: Scrub attribute
+ * @region_id: ID of the memory region
+ * @val: Value to write
+ *
+ * Returns: 0 on success, an error otherwise
+ */
+static int cxl_mem_ecs_write(struct device *dev, u32 attr, int region_id, u64 val)
+{
+ switch (attr) {
+ case scrub_ecs_log_entry_type:
+ return cxl_mem_ecs_log_entry_type_write(dev, region_id, val);
+ case scrub_mode:
+ return cxl_mem_ecs_mode_write(dev, region_id, val);
+ case scrub_reset_counter:
+ return cxl_mem_ecs_reset_counter_write(dev, region_id, val);
+ case scrub_threshold:
+ return cxl_mem_ecs_threshold_write(dev, region_id, val);
+ default:
+ return -ENOTSUPP;
+ }
+}
+
+/**
+ * cxl_mem_ecs_read_strings() - Read callback for DDR5 ECS string attributes
+ * @dev: Pointer to ECS scrub device
+ * @attr: ECS scrub attribute
+ * @region_id: ID of the memory media FRU.
+ * @buf: Pointer to the buffer for copying returned string
+ *
+ * Returns: 0 on success, an error otherwise
+ */
+static int cxl_mem_ecs_read_strings(struct device *dev, u32 attr,
+ int region_id, char *buf)
+{
+
+ switch (attr) {
+ case scrub_threshold_available:
+ return sysfs_emit(buf, "256,1024,4096\n");
+ default:
+ return -ENOTSUPP;
+ }
+}
+
+static const struct scrub_ops cxl_ecs_ops = {
+ .is_visible = cxl_mem_ecs_is_visible,
+ .read = cxl_mem_ecs_read,
+ .write = cxl_mem_ecs_write,
+ .read_string = cxl_mem_ecs_read_strings,
+};
+
int cxl_mem_ddr5_ecs_init(struct cxl_memdev *cxlmd)
{
+ char scrub_name[CXL_MEMDEV_MAX_NAME_LENGTH];
struct cxl_mbox_supp_feat_entry feat_entry;
struct cxl_ecs_context *cxl_ecs_ctx;
+ struct device *cxl_scrub_dev;
int nmedia_frus;
int ret;
@@ -762,6 +987,14 @@ int cxl_mem_ddr5_ecs_init(struct cxl_memdev *cxlmd)
cxl_ecs_ctx->nregions = nmedia_frus;
cxl_ecs_ctx->get_feat_size = feat_entry.get_feat_size;
cxl_ecs_ctx->set_feat_size = feat_entry.set_feat_size;
+
+ snprintf(scrub_name, sizeof(scrub_name), "%s_%s",
+ CXL_DDR5_ECS, dev_name(&cxlmd->dev));
+ cxl_scrub_dev = devm_scrub_device_register(&cxlmd->dev, scrub_name,
+ cxl_ecs_ctx, &cxl_ecs_ops,
+ cxl_ecs_ctx->nregions);
+ if (IS_ERR(cxl_scrub_dev))
+ return PTR_ERR(cxl_scrub_dev);
}
return 0;
--
2.34.1
From: Shiju Jose <[email protected]>
CXL spec 3.1 section 8.2.9.9.11.1 describes the device patrol scrub control
feature. The device patrol scrub proactively locates and makes corrections
to errors in regular cycle. The patrol scrub control allows the request to
configure patrol scrub input configurations.
The patrol scrub control allows the requester to specify the number of
hours for which the patrol scrub cycles must be completed, provided that
the requested number is not less than the minimum number of hours for the
patrol scrub cycle that the device is capable of. In addition, the patrol
scrub controls allow the host to disable and enable the feature in case
disabling of the feature is needed for other purposes such as
performance-aware operations which require the background operations to be
turned off.
Signed-off-by: Shiju Jose <[email protected]>
---
drivers/cxl/Kconfig | 17 +++
drivers/cxl/core/Makefile | 1 +
drivers/cxl/core/memscrub.c | 266 ++++++++++++++++++++++++++++++++++++
drivers/cxl/cxlmem.h | 8 ++
drivers/cxl/pci.c | 5 +
5 files changed, 297 insertions(+)
create mode 100644 drivers/cxl/core/memscrub.c
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index 8ea1d340e438..67d88f9bf52b 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -154,4 +154,21 @@ config CXL_PMU
monitoring units and provide standard perf based interfaces.
If unsure say 'm'.
+
+config CXL_SCRUB
+ bool "CXL: Memory scrub feature"
+ depends on CXL_PCI
+ depends on CXL_MEM
+ help
+ The CXL memory scrub control is an optional feature allows host to
+ control the scrub configurations of CXL Type 3 devices, which
+ support patrol scrub and/or DDR5 ECS(Error Check Scrub).
+
+ Say 'y/n' to enable/disable the CXL memory scrub driver that will
+ attach to CXL.mem devices for memory scrub control feature. See
+ sections 8.2.9.9.11.1 and 8.2.9.9.11.2 in the CXL 3.1 specification
+ for a detailed description of CXL memory scrub control features.
+
+ If unsure say 'n'.
+
endif
diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
index 1f66b5d4d935..99e3202f868f 100644
--- a/drivers/cxl/core/Makefile
+++ b/drivers/cxl/core/Makefile
@@ -15,3 +15,4 @@ cxl_core-y += hdm.o
cxl_core-y += pmu.o
cxl_core-$(CONFIG_TRACING) += trace.o
cxl_core-$(CONFIG_CXL_REGION) += region.o
+cxl_core-$(CONFIG_CXL_SCRUB) += memscrub.o
diff --git a/drivers/cxl/core/memscrub.c b/drivers/cxl/core/memscrub.c
new file mode 100644
index 000000000000..a74f4efa207e
--- /dev/null
+++ b/drivers/cxl/core/memscrub.c
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * cxl_memscrub.c - CXL memory scrub driver
+ *
+ * Copyright (c) 2023 HiSilicon Limited.
+ *
+ * - Provides functions to configure patrol scrub
+ * feature of the CXL memory devices.
+ */
+
+#define pr_fmt(fmt) "CXL_MEM_SCRUB: " fmt
+
+#include <cxlmem.h>
+
+/* CXL memory scrub feature common definitions */
+#define CXL_SCRUB_MAX_ATTRB_RANGE_LENGTH 128
+
+static int cxl_mem_get_supported_feature_entry(struct cxl_memdev *cxlmd, const uuid_t *feat_uuid,
+ struct cxl_mbox_supp_feat_entry *feat_entry_out)
+{
+ struct cxl_mbox_get_supp_feats_out *feats_out __free(kvfree) = NULL;
+ struct cxl_mbox_supp_feat_entry *feat_entry;
+ struct cxl_dev_state *cxlds = cxlmd->cxlds;
+ struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
+ struct cxl_mbox_get_supp_feats_in pi;
+ int feat_index, count;
+ int nentries;
+ int ret;
+
+ feat_index = 0;
+ pi.count = sizeof(struct cxl_mbox_get_supp_feats_out) +
+ sizeof(struct cxl_mbox_supp_feat_entry);
+ feats_out = kvmalloc(pi.count, GFP_KERNEL);
+ if (!feats_out)
+ return -ENOMEM;
+
+ do {
+ pi.start_index = feat_index;
+ memset(feats_out, 0, pi.count);
+ ret = cxl_get_supported_features(mds, &pi, feats_out);
+ if (ret)
+ return ret;
+
+ nentries = feats_out->entries;
+ if (!nentries)
+ break;
+
+ /* Check CXL memdev supports the feature */
+ feat_entry = (void *)feats_out->feat_entries;
+ for (count = 0; count < nentries; count++, feat_entry++) {
+ if (uuid_equal(&feat_entry->uuid, feat_uuid)) {
+ memcpy(feat_entry_out, feat_entry, sizeof(*feat_entry_out));
+ return 0;
+ }
+ }
+ feat_index += nentries;
+ } while (nentries);
+
+ return -ENOTSUPP;
+}
+
+/* CXL memory patrol scrub control definitions */
+#define CXL_MEMDEV_PS_GET_FEAT_VERSION 0x01
+#define CXL_MEMDEV_PS_SET_FEAT_VERSION 0x01
+
+static const uuid_t cxl_patrol_scrub_uuid =
+ UUID_INIT(0x96dad7d6, 0xfde8, 0x482b, 0xa7, 0x33, 0x75, 0x77, 0x4e, \
+ 0x06, 0xdb, 0x8a);
+
+/* CXL memory patrol scrub control functions */
+struct cxl_patrol_scrub_context {
+ struct device *dev;
+ u16 get_feat_size;
+ u16 set_feat_size;
+ bool scrub_cycle_changeable;
+};
+
+/**
+ * struct cxl_memdev_ps_params - CXL memory patrol scrub parameter data structure.
+ * @enable: [IN] enable(1)/disable(0) patrol scrub.
+ * @scrub_cycle_changeable: [OUT] scrub cycle attribute of patrol scrub is changeable.
+ * @speed: [IN] Requested patrol scrub cycle in hours.
+ * [OUT] Current patrol scrub cycle in hours.
+ * @min_speed:[OUT] minimum patrol scrub cycle, in hours, supported.
+ * @speed_avail:[OUT] Supported patrol scrub cycle in hours.
+ */
+struct cxl_memdev_ps_params {
+ bool enable;
+ bool scrub_cycle_changeable;
+ u16 speed;
+ u16 min_speed;
+ char speed_avail[CXL_SCRUB_MAX_ATTRB_RANGE_LENGTH];
+};
+
+enum {
+ CXL_MEMDEV_PS_PARAM_ENABLE = 0,
+ CXL_MEMDEV_PS_PARAM_SPEED,
+};
+
+#define CXL_MEMDEV_PS_SCRUB_CYCLE_CHANGE_CAP_MASK BIT(0)
+#define CXL_MEMDEV_PS_SCRUB_CYCLE_REALTIME_REPORT_CAP_MASK BIT(1)
+#define CXL_MEMDEV_PS_CUR_SCRUB_CYCLE_MASK GENMASK(7, 0)
+#define CXL_MEMDEV_PS_MIN_SCRUB_CYCLE_MASK GENMASK(15, 8)
+#define CXL_MEMDEV_PS_FLAG_ENABLED_MASK BIT(0)
+
+struct cxl_memdev_ps_feat_read_attrbs {
+ u8 scrub_cycle_cap;
+ __le16 scrub_cycle;
+ u8 scrub_flags;
+} __packed;
+
+struct cxl_memdev_ps_set_feat_pi {
+ struct cxl_mbox_set_feat_in pi;
+ u8 scrub_cycle_hr;
+ u8 scrub_flags;
+} __packed;
+
+static int cxl_mem_ps_get_attrbs(struct device *dev,
+ struct cxl_memdev_ps_params *params)
+{
+ struct cxl_memdev_ps_feat_read_attrbs *rd_attrbs __free(kvfree) = NULL;
+ struct cxl_mbox_get_feat_in pi = {
+ .uuid = cxl_patrol_scrub_uuid,
+ .offset = 0,
+ .count = sizeof(struct cxl_memdev_ps_feat_read_attrbs),
+ .selection = CXL_GET_FEAT_SEL_CURRENT_VALUE,
+ };
+ struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
+ struct cxl_dev_state *cxlds = cxlmd->cxlds;
+ struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
+ int ret;
+
+ if (!mds)
+ return -EFAULT;
+
+ rd_attrbs = kvmalloc(pi.count, GFP_KERNEL);
+ if (!rd_attrbs)
+ return -ENOMEM;
+
+ ret = cxl_get_feature(mds, &pi, rd_attrbs);
+ if (ret) {
+ params->enable = 0;
+ params->speed = 0;
+ snprintf(params->speed_avail, CXL_SCRUB_MAX_ATTRB_RANGE_LENGTH,
+ "Unavailable");
+ return ret;
+ }
+ params->scrub_cycle_changeable = FIELD_GET(CXL_MEMDEV_PS_SCRUB_CYCLE_CHANGE_CAP_MASK,
+ rd_attrbs->scrub_cycle_cap);
+ params->enable = FIELD_GET(CXL_MEMDEV_PS_FLAG_ENABLED_MASK,
+ rd_attrbs->scrub_flags);
+ params->speed = FIELD_GET(CXL_MEMDEV_PS_CUR_SCRUB_CYCLE_MASK,
+ rd_attrbs->scrub_cycle);
+ params->min_speed = FIELD_GET(CXL_MEMDEV_PS_MIN_SCRUB_CYCLE_MASK,
+ rd_attrbs->scrub_cycle);
+ snprintf(params->speed_avail, CXL_SCRUB_MAX_ATTRB_RANGE_LENGTH,
+ "Minimum scrub cycle = %d hour", params->min_speed);
+
+ return 0;
+}
+
+static int __maybe_unused
+cxl_mem_ps_set_attrbs(struct device *dev, struct cxl_memdev_ps_params *params,
+ u8 param_type)
+{
+ struct cxl_memdev_ps_set_feat_pi set_pi = {
+ .pi.uuid = cxl_patrol_scrub_uuid,
+ .pi.flags = CXL_SET_FEAT_FLAG_MOD_VALUE_SAVED_ACROSS_RESET |
+ CXL_SET_FEAT_FLAG_FULL_DATA_TRANSFER,
+ .pi.offset = 0,
+ .pi.version = CXL_MEMDEV_PS_SET_FEAT_VERSION,
+ };
+ struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
+ struct cxl_dev_state *cxlds = cxlmd->cxlds;
+ struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
+ struct cxl_memdev_ps_params rd_params;
+ int ret;
+
+ if (!mds)
+ return -EFAULT;
+
+ ret = cxl_mem_ps_get_attrbs(dev, &rd_params);
+ if (ret) {
+ dev_err(dev, "Get cxlmemdev patrol scrub params fail ret=%d\n",
+ ret);
+ return ret;
+ }
+
+ switch (param_type) {
+ case CXL_MEMDEV_PS_PARAM_ENABLE:
+ set_pi.scrub_flags = FIELD_PREP(CXL_MEMDEV_PS_FLAG_ENABLED_MASK,
+ params->enable);
+ set_pi.scrub_cycle_hr = FIELD_PREP(CXL_MEMDEV_PS_CUR_SCRUB_CYCLE_MASK,
+ rd_params.speed);
+ break;
+ case CXL_MEMDEV_PS_PARAM_SPEED:
+ if (params->speed < rd_params.min_speed) {
+ dev_err(dev, "Invalid CXL patrol scrub cycle(%d) to set\n",
+ params->speed);
+ dev_err(dev, "Minimum supported CXL patrol scrub cycle in hour %d\n",
+ params->min_speed);
+ return -EINVAL;
+ }
+ set_pi.scrub_cycle_hr = FIELD_PREP(CXL_MEMDEV_PS_CUR_SCRUB_CYCLE_MASK,
+ params->speed);
+ set_pi.scrub_flags = FIELD_PREP(CXL_MEMDEV_PS_FLAG_ENABLED_MASK,
+ rd_params.enable);
+ break;
+ default:
+ dev_err(dev, "Invalid CXL patrol scrub parameter to set\n");
+ return -EINVAL;
+ }
+
+ ret = cxl_set_feature(mds, &set_pi, sizeof(set_pi));
+ if (ret) {
+ dev_err(dev, "CXL patrol scrub set feature fail ret=%d\n",
+ ret);
+ return ret;
+ }
+
+ /* Verify attribute set successfully */
+ if (param_type == CXL_MEMDEV_PS_PARAM_SPEED) {
+ ret = cxl_mem_ps_get_attrbs(dev, &rd_params);
+ if (ret) {
+ dev_err(dev, "Get cxlmemdev patrol scrub params fail ret=%d\n", ret);
+ return ret;
+ }
+ if (rd_params.speed != params->speed)
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+int cxl_mem_patrol_scrub_init(struct cxl_memdev *cxlmd)
+{
+ struct cxl_patrol_scrub_context *cxl_ps_ctx;
+ struct cxl_mbox_supp_feat_entry feat_entry;
+ struct cxl_memdev_ps_params params;
+ int ret;
+
+ ret = cxl_mem_get_supported_feature_entry(cxlmd, &cxl_patrol_scrub_uuid,
+ &feat_entry);
+ if (ret < 0)
+ return ret;
+
+ if (!(feat_entry.attrb_flags & CXL_FEAT_ENTRY_FLAG_CHANGABLE))
+ return -ENOTSUPP;
+
+ cxl_ps_ctx = devm_kzalloc(&cxlmd->dev, sizeof(*cxl_ps_ctx), GFP_KERNEL);
+ if (!cxl_ps_ctx)
+ return -ENOMEM;
+
+ cxl_ps_ctx->get_feat_size = feat_entry.get_feat_size;
+ cxl_ps_ctx->set_feat_size = feat_entry.set_feat_size;
+ ret = cxl_mem_ps_get_attrbs(&cxlmd->dev, ¶ms);
+ if (ret) {
+ dev_err(&cxlmd->dev, "Get CXL patrol scrub params fail ret=%d\n",
+ ret);
+ return ret;
+ }
+ cxl_ps_ctx->scrub_cycle_changeable = params.scrub_cycle_changeable;
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_mem_patrol_scrub_init, CXL);
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 46131dcd0900..25c46e72af16 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -983,6 +983,14 @@ int cxl_trigger_poison_list(struct cxl_memdev *cxlmd);
int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa);
int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa);
+/* cxl memory scrub functions */
+#ifdef CONFIG_CXL_SCRUB
+int cxl_mem_patrol_scrub_init(struct cxl_memdev *cxlmd);
+#else
+static inline int cxl_mem_patrol_scrub_init(struct cxl_memdev *cxlmd)
+{ return -ENOTSUPP; }
+#endif
+
#ifdef CONFIG_CXL_SUSPEND
void cxl_mem_active_inc(void);
void cxl_mem_active_dec(void);
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 0155fb66b580..acc337b8c365 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -881,6 +881,11 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
if (rc)
return rc;
+ /*
+ * Initialize optional CXL scrub features
+ */
+ cxl_mem_patrol_scrub_init(cxlmd);
+
rc = devm_cxl_sanitize_setup_notifier(&pdev->dev, cxlmd);
if (rc)
return rc;
--
2.34.1
From: Shiju Jose <[email protected]>
Register with the scrub configure driver to expose the sysfs attributes
to the user for configuring the CXL device memory patrol scrub. Add the
callback functions to support configuring the CXL memory device patrol
scrub.
Signed-off-by: Shiju Jose <[email protected]>
---
drivers/cxl/Kconfig | 6 ++
drivers/cxl/core/memscrub.c | 210 +++++++++++++++++++++++++++++++++++-
2 files changed, 213 insertions(+), 3 deletions(-)
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index 67d88f9bf52b..964b5f789770 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -159,11 +159,17 @@ config CXL_SCRUB
bool "CXL: Memory scrub feature"
depends on CXL_PCI
depends on CXL_MEM
+ depends on SCRUB
help
The CXL memory scrub control is an optional feature allows host to
control the scrub configurations of CXL Type 3 devices, which
support patrol scrub and/or DDR5 ECS(Error Check Scrub).
+ Register with the scrub configure driver to expose sysfs attributes
+ to the user for configuring the CXL device memory patrol and DDR5 ECS
+ scrubs. Provides the interface functions to support configuring the
+ CXL memory device patrol and ECS scrubs.
+
Say 'y/n' to enable/disable the CXL memory scrub driver that will
attach to CXL.mem devices for memory scrub control feature. See
sections 8.2.9.9.11.1 and 8.2.9.9.11.2 in the CXL 3.1 specification
diff --git a/drivers/cxl/core/memscrub.c b/drivers/cxl/core/memscrub.c
index 7c58d56762b3..4d778ffa3322 100644
--- a/drivers/cxl/core/memscrub.c
+++ b/drivers/cxl/core/memscrub.c
@@ -6,14 +6,19 @@
*
* - Provides functions to configure patrol scrub
* and DDR5 ECS features of the CXL memory devices.
+ * - Registers with the scrub driver to expose
+ * the sysfs attributes to the user for configuring
+ * the memory patrol scrub and DDR5 ECS features.
*/
#define pr_fmt(fmt) "CXL_MEM_SCRUB: " fmt
#include <cxlmem.h>
+#include <memory/memory-scrub.h>
/* CXL memory scrub feature common definitions */
#define CXL_SCRUB_MAX_ATTRB_RANGE_LENGTH 128
+#define CXL_MEMDEV_MAX_NAME_LENGTH 128
static int cxl_mem_get_supported_feature_entry(struct cxl_memdev *cxlmd, const uuid_t *feat_uuid,
struct cxl_mbox_supp_feat_entry *feat_entry_out)
@@ -63,6 +68,16 @@ static int cxl_mem_get_supported_feature_entry(struct cxl_memdev *cxlmd, const u
#define CXL_MEMDEV_PS_GET_FEAT_VERSION 0x01
#define CXL_MEMDEV_PS_SET_FEAT_VERSION 0x01
+#define CXL_PATROL_SCRUB "cxl_patrol_scrub"
+
+/* The default number of regions for CXL memory device patrol scrubber
+ * Patrol scrub is a feature where the device controller scrubs the
+ * memory at a regular interval accroding to the CXL specification.
+ * Hence the number of memory regions to scrub assosiated to the patrol
+ * scrub is 1.
+ */
+#define CXL_MEMDEV_PATROL_SCRUB_NUM_REGIONS 1
+
static const uuid_t cxl_patrol_scrub_uuid =
UUID_INIT(0x96dad7d6, 0xfde8, 0x482b, 0xa7, 0x33, 0x75, 0x77, 0x4e, \
0x06, 0xdb, 0x8a);
@@ -159,9 +174,8 @@ static int cxl_mem_ps_get_attrbs(struct device *dev,
return 0;
}
-static int __maybe_unused
-cxl_mem_ps_set_attrbs(struct device *dev, struct cxl_memdev_ps_params *params,
- u8 param_type)
+static int cxl_mem_ps_set_attrbs(struct device *dev,
+ struct cxl_memdev_ps_params *params, u8 param_type)
{
struct cxl_memdev_ps_set_feat_pi set_pi = {
.pi.uuid = cxl_patrol_scrub_uuid,
@@ -232,11 +246,193 @@ cxl_mem_ps_set_attrbs(struct device *dev, struct cxl_memdev_ps_params *params,
return 0;
}
+static int cxl_mem_ps_enable_read(struct device *dev, u64 *val)
+{
+ struct cxl_memdev_ps_params params;
+ int ret;
+
+ ret = cxl_mem_ps_get_attrbs(dev, ¶ms);
+ if (ret) {
+ dev_err(dev, "Get CXL patrol scrub params fail ret=%d\n", ret);
+ return ret;
+ }
+ *val = params.enable;
+
+ return 0;
+}
+
+static int cxl_mem_ps_enable_write(struct device *dev, long val)
+{
+ struct cxl_memdev_ps_params params;
+ int ret;
+
+ params.enable = val;
+ ret = cxl_mem_ps_set_attrbs(dev, ¶ms, CXL_MEMDEV_PS_PARAM_ENABLE);
+ if (ret) {
+ dev_err(dev, "CXL patrol scrub enable fail, enable=%d ret=%d\n",
+ params.enable, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cxl_mem_ps_speed_read(struct device *dev, u64 *val)
+{
+ struct cxl_memdev_ps_params params;
+ int ret;
+
+ ret = cxl_mem_ps_get_attrbs(dev, ¶ms);
+ if (ret) {
+ dev_err(dev, "Get CXL patrol scrub params fail ret=%d\n", ret);
+ return ret;
+ }
+ *val = params.speed;
+
+ return 0;
+}
+
+static int cxl_mem_ps_speed_write(struct device *dev, long val)
+{
+ struct cxl_memdev_ps_params params;
+ int ret;
+
+ params.speed = val;
+ ret = cxl_mem_ps_set_attrbs(dev, ¶ms, CXL_MEMDEV_PS_PARAM_SPEED);
+ if (ret) {
+ dev_err(dev, "Set CXL patrol scrub params for speed fail ret=%d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cxl_mem_ps_speed_available_read(struct device *dev, char *buf)
+{
+ struct cxl_memdev_ps_params params;
+ int ret;
+
+ ret = cxl_mem_ps_get_attrbs(dev, ¶ms);
+ if (ret) {
+ dev_err(dev, "Get CXL patrol scrub params fail ret=%d\n", ret);
+ return ret;
+ }
+
+ sysfs_emit(buf, "%s\n", params.speed_avail);
+
+ return 0;
+}
+
+/**
+ * cxl_mem_patrol_scrub_is_visible() - Callback to return attribute visibility
+ * @drv_data: Pointer to driver-private data structure passed
+ * as argument to devm_scrub_device_register().
+ * @attr: Scrub attribute
+ * @region_id: ID of the memory region
+ *
+ * Returns: 0 on success, an error otherwise
+ */
+static umode_t cxl_mem_patrol_scrub_is_visible(const void *drv_data,
+ u32 attr, int region_id)
+{
+ const struct cxl_patrol_scrub_context *cxl_ps_ctx = drv_data;
+
+ if (attr == scrub_speed_available ||
+ attr == scrub_speed) {
+ if (!cxl_ps_ctx->scrub_cycle_changeable)
+ return 0;
+ }
+
+ switch (attr) {
+ case scrub_speed_available:
+ return 0444;
+ case scrub_enable:
+ case scrub_speed:
+ return 0644;
+ default:
+ return 0;
+ }
+}
+
+/**
+ * cxl_mem_patrol_scrub_read() - Read callback for data attributes
+ * @dev: Pointer to scrub device
+ * @attr: Scrub attribute
+ * @region_id: ID of the memory region
+ * @val: Pointer to the returned data
+ *
+ * Returns: 0 on success, an error otherwise
+ */
+static int cxl_mem_patrol_scrub_read(struct device *dev, u32 attr,
+ int region_id, u64 *val)
+{
+
+ switch (attr) {
+ case scrub_enable:
+ return cxl_mem_ps_enable_read(dev->parent, val);
+ case scrub_speed:
+ return cxl_mem_ps_speed_read(dev->parent, val);
+ default:
+ return -ENOTSUPP;
+ }
+}
+
+/**
+ * cxl_mem_patrol_scrub_write() - Write callback for data attributes
+ * @dev: Pointer to scrub device
+ * @attr: Scrub attribute
+ * @region_id: ID of the memory region
+ * @val: Value to write
+ *
+ * Returns: 0 on success, an error otherwise
+ */
+static int cxl_mem_patrol_scrub_write(struct device *dev, u32 attr,
+ int region_id, u64 val)
+{
+ switch (attr) {
+ case scrub_enable:
+ return cxl_mem_ps_enable_write(dev->parent, val);
+ case scrub_speed:
+ return cxl_mem_ps_speed_write(dev->parent, val);
+ default:
+ return -ENOTSUPP;
+ }
+}
+
+/**
+ * cxl_mem_patrol_scrub_read_strings() - Read callback for string attributes
+ * @dev: Pointer to scrub device
+ * @attr: Scrub attribute
+ * @region_id: ID of the memory region
+ * @buf: Pointer to the buffer for copying returned string
+ *
+ * Returns: 0 on success, an error otherwise
+ */
+static int cxl_mem_patrol_scrub_read_strings(struct device *dev, u32 attr,
+ int region_id, char *buf)
+{
+ switch (attr) {
+ case scrub_speed_available:
+ return cxl_mem_ps_speed_available_read(dev->parent, buf);
+ default:
+ return -ENOTSUPP;
+ }
+}
+
+static const struct scrub_ops cxl_ps_scrub_ops = {
+ .is_visible = cxl_mem_patrol_scrub_is_visible,
+ .read = cxl_mem_patrol_scrub_read,
+ .write = cxl_mem_patrol_scrub_write,
+ .read_string = cxl_mem_patrol_scrub_read_strings,
+};
+
int cxl_mem_patrol_scrub_init(struct cxl_memdev *cxlmd)
{
+ char scrub_name[CXL_MEMDEV_MAX_NAME_LENGTH];
struct cxl_patrol_scrub_context *cxl_ps_ctx;
struct cxl_mbox_supp_feat_entry feat_entry;
struct cxl_memdev_ps_params params;
+ struct device *cxl_scrub_dev;
int ret;
ret = cxl_mem_get_supported_feature_entry(cxlmd, &cxl_patrol_scrub_uuid,
@@ -261,6 +457,14 @@ int cxl_mem_patrol_scrub_init(struct cxl_memdev *cxlmd)
}
cxl_ps_ctx->scrub_cycle_changeable = params.scrub_cycle_changeable;
+ snprintf(scrub_name, sizeof(scrub_name), "%s_%s",
+ CXL_PATROL_SCRUB, dev_name(&cxlmd->dev));
+ cxl_scrub_dev = devm_scrub_device_register(&cxlmd->dev, scrub_name,
+ cxl_ps_ctx, &cxl_ps_scrub_ops,
+ CXL_MEMDEV_PATROL_SCRUB_NUM_REGIONS);
+ if (IS_ERR(cxl_scrub_dev))
+ return PTR_ERR(cxl_scrub_dev);
+
return 0;
}
EXPORT_SYMBOL_NS_GPL(cxl_mem_patrol_scrub_init, CXL);
--
2.34.1
From: Shiju Jose <[email protected]>
Add support for SET_FEATURE mailbox command.
CXL spec 3.0 section 8.2.9.6 describes optional device specific features.
CXL devices supports features with changeable attributes.
The settings of a feature can be optionally modified using Set Feature
command.
Signed-off-by: Shiju Jose <[email protected]>
---
drivers/cxl/core/mbox.c | 14 ++++++++++++++
drivers/cxl/cxlmem.h | 27 +++++++++++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index a50c874edebc..7f379cbb71a0 100644
--- a/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@ -1348,6 +1348,20 @@ int cxl_get_feature(struct cxl_memdev_state *mds,
}
EXPORT_SYMBOL_NS_GPL(cxl_get_feature, CXL);
+int cxl_set_feature(struct cxl_memdev_state *mds, void *feat_in, size_t size)
+{
+ struct cxl_mbox_cmd mbox_cmd;
+
+ mbox_cmd = (struct cxl_mbox_cmd) {
+ .opcode = CXL_MBOX_OP_SET_FEATURE,
+ .size_in = size,
+ .payload_in = feat_in,
+ };
+
+ return cxl_internal_send_cmd(mds, &mbox_cmd);
+}
+EXPORT_SYMBOL_NS_GPL(cxl_set_feature, CXL);
+
int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
struct cxl_region *cxlr)
{
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 92c1f2a44713..46131dcd0900 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -508,6 +508,7 @@ enum cxl_opcode {
CXL_MBOX_OP_GET_LOG = 0x0401,
CXL_MBOX_OP_GET_SUPPORTED_FEATURES = 0x0500,
CXL_MBOX_OP_GET_FEATURE = 0x0501,
+ CXL_MBOX_OP_SET_FEATURE = 0x0502,
CXL_MBOX_OP_IDENTIFY = 0x4000,
CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
@@ -817,6 +818,31 @@ struct cxl_mbox_get_feat_in {
u8 selection;
} __packed;
+/* Set Feature CXL 3.0 Spec 8.2.9.6.3 */
+/*
+ * Set Feature input payload
+ * CXL rev 3.0 section 8.2.9.6.3; Table 8-81
+ */
+/* Set Feature : Payload in flags */
+#define CXL_SET_FEAT_FLAG_DATA_TRANSFER_MASK GENMASK(2, 0)
+enum cxl_set_feat_flag_data_transfer {
+ CXL_SET_FEAT_FLAG_FULL_DATA_TRANSFER = 0x0,
+ CXL_SET_FEAT_FLAG_INITIATE_DATA_TRANSFER = 0x1,
+ CXL_SET_FEAT_FLAG_CONTINUE_DATA_TRANSFER = 0x2,
+ CXL_SET_FEAT_FLAG_FINISH_DATA_TRANSFER = 0x3,
+ CXL_SET_FEAT_FLAG_ABORT_DATA_TRANSFER = 0x4,
+ CXL_SET_FEAT_FLAG_DATA_TRANSFER_MAX
+};
+#define CXL_SET_FEAT_FLAG_MOD_VALUE_SAVED_ACROSS_RESET BIT(3)
+
+struct cxl_mbox_set_feat_in {
+ uuid_t uuid;
+ __le32 flags;
+ __le16 offset;
+ u8 version;
+ u8 rsvd[9];
+} __packed;
+
/* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */
struct cxl_mbox_poison_in {
__le64 offset;
@@ -949,6 +975,7 @@ int cxl_get_supported_features(struct cxl_memdev_state *mds,
void *feats_out);
int cxl_get_feature(struct cxl_memdev_state *mds,
struct cxl_mbox_get_feat_in *pi, void *feat_out);
+int cxl_set_feature(struct cxl_memdev_state *mds, void *feat_in, size_t size);
int cxl_poison_state_init(struct cxl_memdev_state *mds);
int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
struct cxl_region *cxlr);
--
2.34.1
From: Shiju Jose <[email protected]>
Add scrub driver supports configuring the memory scrubs in the system.
The scrub driver provides the interface for registering the scrub devices
and to configure the attributes of memory scrubs in the system.
Driver exposes the scrub parameter attributes to the user via sysfs in
/sys/class/scrub/scrubX/regionY/
This driver has been implemented referring to the hwmon subsystem.
Signed-off-by: Shiju Jose <[email protected]>
---
drivers/memory/Kconfig | 1 +
drivers/memory/Makefile | 1 +
drivers/memory/scrub/Kconfig | 11 +
drivers/memory/scrub/Makefile | 6 +
drivers/memory/scrub/memory-scrub.c | 470 ++++++++++++++++++++++++++++
include/memory/memory-scrub.h | 80 +++++
6 files changed, 569 insertions(+)
create mode 100644 drivers/memory/scrub/Kconfig
create mode 100644 drivers/memory/scrub/Makefile
create mode 100755 drivers/memory/scrub/memory-scrub.c
create mode 100755 include/memory/memory-scrub.h
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 8efdd1f97139..d2e015c09d83 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -227,5 +227,6 @@ config STM32_FMC2_EBI
source "drivers/memory/samsung/Kconfig"
source "drivers/memory/tegra/Kconfig"
+source "drivers/memory/scrub/Kconfig"
endif
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index d2e6ca9abbe0..4b37312cb342 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o
obj-$(CONFIG_SAMSUNG_MC) += samsung/
obj-$(CONFIG_TEGRA_MC) += tegra/
+obj-$(CONFIG_SCRUB) += scrub/
obj-$(CONFIG_TI_EMIF_SRAM) += ti-emif-sram.o
obj-$(CONFIG_FPGA_DFL_EMIF) += dfl-emif.o
diff --git a/drivers/memory/scrub/Kconfig b/drivers/memory/scrub/Kconfig
new file mode 100644
index 000000000000..fa7d68f53a69
--- /dev/null
+++ b/drivers/memory/scrub/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Memory scrub driver configurations
+#
+
+config SCRUB
+ bool "Memory scrub driver"
+ help
+ This option selects the memory scrub subsystem, supports
+ configuring the parameters of underlying scrubbers in the
+ system for the DRAM memories.
diff --git a/drivers/memory/scrub/Makefile b/drivers/memory/scrub/Makefile
new file mode 100644
index 000000000000..1b677132ca13
--- /dev/null
+++ b/drivers/memory/scrub/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for memory scrub drivers
+#
+
+obj-$(CONFIG_SCRUB) += memory-scrub.o
diff --git a/drivers/memory/scrub/memory-scrub.c b/drivers/memory/scrub/memory-scrub.c
new file mode 100755
index 000000000000..c2d794b2624b
--- /dev/null
+++ b/drivers/memory/scrub/memory-scrub.c
@@ -0,0 +1,470 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Memory scrub controller driver support to configure
+ * the parameters of the memory scrubbers and enable.
+ *
+ * Copyright (c) 2023 HiSilicon Limited.
+ */
+
+#define pr_fmt(fmt) "MEM SCRUB: " fmt
+
+#include <linux/acpi.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/kfifo.h>
+#include <linux/spinlock.h>
+#include <memory/memory-scrub.h>
+
+/* memory scrubber config definitions */
+#define SCRUB_ID_PREFIX "scrub"
+#define SCRUB_ID_FORMAT SCRUB_ID_PREFIX "%d"
+#define SCRUB_DEV_MAX_NAME_LENGTH 128
+
+static DEFINE_IDA(scrub_ida);
+
+struct scrub_device {
+ char name[SCRUB_DEV_MAX_NAME_LENGTH];
+ int id;
+ struct device dev;
+ const struct scrub_source_info *source_info;
+ struct list_head tzdata;
+ char (*region_name)[];
+ struct attribute_group group;
+ int ngroups;
+ struct attribute_group *region_groups;
+ const struct attribute_group **groups;
+};
+
+#define to_scrub_device(d) container_of(d, struct scrub_device, dev)
+#define SCRUB_MAX_SYSFS_ATTR_NAME_LENGTH 64
+
+struct scrub_device_attribute {
+ struct device_attribute dev_attr;
+ const struct scrub_ops *ops;
+ u32 attr;
+ int region_id;
+ char name[SCRUB_MAX_SYSFS_ATTR_NAME_LENGTH];
+};
+
+#define to_scrub_attr(d) \
+ container_of(d, struct scrub_device_attribute, dev_attr)
+#define to_dev_attr(a) container_of(a, struct device_attribute, attr)
+
+static ssize_t name_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%s\n", to_scrub_device(dev)->name);
+}
+static DEVICE_ATTR_RO(name);
+
+static struct attribute *scrub_dev_attrs[] = {
+ &dev_attr_name.attr,
+ NULL
+};
+
+static umode_t scrub_dev_attr_is_visible(struct kobject *kobj,
+ struct attribute *attr, int n)
+{
+ if (attr != &dev_attr_name.attr)
+ return 0;
+
+ return attr->mode;
+}
+
+static const struct attribute_group scrub_dev_attr_group = {
+ .attrs = scrub_dev_attrs,
+ .is_visible = scrub_dev_attr_is_visible,
+};
+
+static const struct attribute_group *scrub_dev_attr_groups[] = {
+ &scrub_dev_attr_group,
+ NULL
+};
+
+static void scrub_free_attrs(struct attribute **attrs)
+{
+ int i;
+
+ for (i = 0; attrs[i]; i++) {
+ struct device_attribute *dattr = to_dev_attr(attrs[i]);
+ struct scrub_device_attribute *hattr = to_scrub_attr(dattr);
+
+ kfree(hattr);
+ }
+ kfree(attrs);
+}
+
+static void scrub_dev_release(struct device *dev)
+{
+ int count;
+ struct attribute_group *group;
+ struct scrub_device *scrub_dev = to_scrub_device(dev);
+
+ for (count = 0; count < scrub_dev->ngroups; count++) {
+ group = (struct attribute_group *)scrub_dev->groups[count];
+ if (group)
+ scrub_free_attrs(group->attrs);
+ }
+ kfree(scrub_dev->region_name);
+ kfree(scrub_dev->region_groups);
+ kfree(scrub_dev->groups);
+ ida_free(&scrub_ida, scrub_dev->id);
+ kfree(scrub_dev);
+}
+
+static struct class scrub_class = {
+ .name = "scrub",
+ .dev_groups = scrub_dev_attr_groups,
+ .dev_release = scrub_dev_release,
+};
+
+/* sysfs attribute management */
+
+static ssize_t scrub_attr_show(struct device *dev,
+ struct device_attribute *devattr, char *buf)
+{
+ int ret;
+ u64 val;
+ struct scrub_device_attribute *hattr = to_scrub_attr(devattr);
+
+ ret = hattr->ops->read(dev, hattr->attr, hattr->region_id, &val);
+ if (ret < 0)
+ return ret;
+
+ return sprintf(buf, "%lld\n", val);
+}
+
+static ssize_t scrub_attr_show_hex(struct device *dev,
+ struct device_attribute *devattr, char *buf)
+{
+ int ret;
+ u64 val;
+ struct scrub_device_attribute *hattr = to_scrub_attr(devattr);
+
+ ret = hattr->ops->read(dev, hattr->attr, hattr->region_id, &val);
+ if (ret < 0)
+ return ret;
+
+ return sprintf(buf, "0x%llx\n", val);
+}
+
+static ssize_t scrub_attr_show_string(struct device *dev,
+ struct device_attribute *devattr,
+ char *buf)
+{
+ int ret;
+ struct scrub_device_attribute *hattr = to_scrub_attr(devattr);
+
+ ret = hattr->ops->read_string(dev, hattr->attr, hattr->region_id, buf);
+ if (ret < 0)
+ return ret;
+
+ return strlen(buf);
+}
+
+static ssize_t scrub_attr_store(struct device *dev,
+ struct device_attribute *devattr,
+ const char *buf, size_t count)
+{
+ int ret;
+ long val;
+ struct scrub_device_attribute *hattr = to_scrub_attr(devattr);
+
+ ret = kstrtol(buf, 10, &val);
+ if (ret < 0)
+ return ret;
+
+ ret = hattr->ops->write(dev, hattr->attr, hattr->region_id, val);
+ if (ret < 0)
+ return ret;
+
+ return count;
+}
+
+static ssize_t scrub_attr_store_hex(struct device *dev,
+ struct device_attribute *devattr,
+ const char *buf, size_t count)
+{
+ int ret;
+ u64 val;
+ struct scrub_device_attribute *hattr = to_scrub_attr(devattr);
+
+ ret = kstrtou64(buf, 16, &val);
+ if (ret < 0)
+ return ret;
+
+ ret = hattr->ops->write(dev, hattr->attr, hattr->region_id, val);
+ if (ret < 0)
+ return ret;
+
+ return count;
+}
+
+static bool is_hex_attr(u32 attr)
+{
+ return (attr == scrub_addr_base) ||
+ (attr == scrub_addr_size);
+}
+
+static bool is_string_attr(u32 attr)
+{
+ return attr == scrub_speed_available;
+}
+
+static struct attribute *scrub_genattr(const void *drvdata,
+ u32 attr,
+ const char *attrb_name,
+ const struct scrub_ops *ops,
+ int region_id)
+{
+ umode_t mode;
+ struct attribute *a;
+ struct device_attribute *dattr;
+ bool is_hex = is_hex_attr(attr);
+ struct scrub_device_attribute *hattr;
+ bool is_string = is_string_attr(attr);
+
+ /* The attribute is invisible if there is no template string */
+ if (!attrb_name)
+ return ERR_PTR(-ENOENT);
+
+ mode = ops->is_visible(drvdata, attr, region_id);
+ if (!mode)
+ return ERR_PTR(-ENOENT);
+
+ if ((mode & 0444) && ((is_string && !ops->read_string) ||
+ (!is_string && !ops->read)))
+ return ERR_PTR(-EINVAL);
+ if ((mode & 0222) && (!ops->write))
+ return ERR_PTR(-EINVAL);
+
+ hattr = kzalloc(sizeof(*hattr), GFP_KERNEL);
+ if (!hattr)
+ return ERR_PTR(-ENOMEM);
+
+ hattr->attr = attr;
+ hattr->ops = ops;
+ hattr->region_id = region_id;
+
+ dattr = &hattr->dev_attr;
+ if (is_string) {
+ dattr->show = scrub_attr_show_string;
+ } else {
+ dattr->show = is_hex ? scrub_attr_show_hex : scrub_attr_show;
+ dattr->store = is_hex ? scrub_attr_store_hex : scrub_attr_store;
+ }
+
+ a = &dattr->attr;
+ sysfs_attr_init(a);
+ a->name = attrb_name;
+ a->mode = mode;
+
+ return a;
+}
+
+static const char * const scrub_common_attrs[] = {
+ /* scrub attributes - common */
+ [scrub_addr_base] = "addr_base",
+ [scrub_addr_size] = "addr_size",
+ [scrub_enable] = "enable",
+ [scrub_speed] = "speed",
+ [scrub_speed_available] = "speed_available",
+};
+
+static struct attribute **
+scrub_create_attrs(const void *drvdata, const struct scrub_ops *ops, int region_id)
+{
+ u32 attr;
+ int aindex = 0;
+ struct attribute *a;
+ struct attribute **attrs;
+
+ attrs = kcalloc(max_attrs, sizeof(*attrs), GFP_KERNEL);
+ if (!attrs)
+ return ERR_PTR(-ENOMEM);
+
+ for (attr = 0; attr < max_attrs; attr++) {
+ a = scrub_genattr(drvdata, attr, scrub_common_attrs[attr],
+ ops, region_id);
+ if (IS_ERR(a)) {
+ if (PTR_ERR(a) != -ENOENT) {
+ scrub_free_attrs(attrs);
+ return ERR_PTR(PTR_ERR(a));
+ }
+ continue;
+ }
+ attrs[aindex++] = a;
+ }
+
+ return attrs;
+}
+
+static struct device *
+scrub_device_register(struct device *dev, const char *name, void *drvdata,
+ const struct scrub_ops *ops,
+ int nregions)
+{
+ struct device *hdev;
+ struct attribute **attrs;
+ int err, count, region_id;
+ struct attribute_group *group;
+ struct scrub_device *scrub_dev;
+ char (*region_name)[SCRUB_MAX_SYSFS_ATTR_NAME_LENGTH];
+
+ scrub_dev = kzalloc(sizeof(*scrub_dev), GFP_KERNEL);
+ if (!scrub_dev)
+ return ERR_PTR(-ENOMEM);
+ hdev = &scrub_dev->dev;
+
+ scrub_dev->id = ida_alloc(&scrub_ida, GFP_KERNEL);
+ if (scrub_dev->id < 0) {
+ err = -ENOMEM;
+ goto free_scrub_dev;
+ }
+ int ngroups = 2; /* terminating NULL plus &scrub_dev->groups */
+
+ ngroups += nregions;
+
+ scrub_dev->groups = kcalloc(ngroups, sizeof(struct attribute_group *), GFP_KERNEL);
+ if (!scrub_dev->groups) {
+ err = -ENOMEM;
+ goto free_ida;
+ }
+
+ if (nregions) {
+ scrub_dev->region_groups = kcalloc(nregions, sizeof(struct attribute_group),
+ GFP_KERNEL);
+ if (!scrub_dev->groups) {
+ err = -ENOMEM;
+ goto free_groups;
+ }
+ scrub_dev->region_name = kcalloc(nregions, SCRUB_MAX_SYSFS_ATTR_NAME_LENGTH,
+ GFP_KERNEL);
+ if (!scrub_dev->region_name) {
+ err = -ENOMEM;
+ goto free_region_groups;
+ }
+ }
+
+ ngroups = 0;
+ scrub_dev->ngroups = 0;
+ if (nregions) {
+ region_name = scrub_dev->region_name;
+ for (region_id = 0; region_id < nregions; region_id++) {
+ attrs = scrub_create_attrs(drvdata, ops, region_id);
+ if (IS_ERR(attrs)) {
+ err = PTR_ERR(attrs);
+ goto free_attrs;
+ }
+ snprintf((char *)region_name, SCRUB_MAX_SYSFS_ATTR_NAME_LENGTH,
+ "region%d", region_id);
+ scrub_dev->region_groups[region_id].name = (char *)region_name;
+ scrub_dev->region_groups[region_id].attrs = attrs;
+ region_name++;
+ scrub_dev->groups[ngroups++] = &scrub_dev->region_groups[region_id];
+ scrub_dev->ngroups = ngroups;
+ }
+ } else {
+ attrs = scrub_create_attrs(drvdata, ops, -1);
+ if (IS_ERR(attrs)) {
+ err = PTR_ERR(attrs);
+ goto free_region_name;
+ }
+ scrub_dev->group.attrs = attrs;
+ scrub_dev->groups[ngroups++] = &scrub_dev->group;
+ scrub_dev->ngroups = ngroups;
+ }
+
+ hdev->groups = scrub_dev->groups;
+ hdev->class = &scrub_class;
+ hdev->parent = dev;
+ dev_set_drvdata(hdev, drvdata);
+ dev_set_name(hdev, SCRUB_ID_FORMAT, scrub_dev->id);
+ snprintf(scrub_dev->name, SCRUB_DEV_MAX_NAME_LENGTH, "%s", name);
+ err = device_register(hdev);
+ if (err) {
+ put_device(hdev);
+ return ERR_PTR(err);
+ }
+
+ return hdev;
+
+free_attrs:
+ for (count = 0; count < scrub_dev->ngroups; count++) {
+ group = (struct attribute_group *)scrub_dev->groups[count];
+ if (group)
+ scrub_free_attrs(group->attrs);
+ }
+
+free_region_name:
+ kfree(scrub_dev->region_name);
+
+free_region_groups:
+ kfree(scrub_dev->region_groups);
+
+free_groups:
+ kfree(scrub_dev->groups);
+
+free_ida:
+ ida_free(&scrub_ida, scrub_dev->id);
+
+free_scrub_dev:
+ kfree(scrub_dev);
+ return ERR_PTR(err);
+}
+
+static void devm_scrub_release(void *dev)
+{
+ struct device *hdev = dev;
+
+ device_unregister(hdev);
+}
+
+/**
+ * devm_scrub_device_register - register hw scrubber device
+ * @dev: the parent device (mandatory)
+ * @name: hw scrubber name attribute (mandatory)
+ * @drvdata: driver data to attach to created device (mandatory)
+ * @ops: pointer to scrub_ops structure (mandatory)
+ * @nregions: number of scrub regions to create (optional)
+ *
+ * Returns the pointer to the new device. The new device is automatically
+ * unregistered with the parent device.
+ */
+struct device *
+devm_scrub_device_register(struct device *dev, const char *name,
+ void *drvdata,
+ const struct scrub_ops *ops,
+ int nregions)
+{
+ struct device *hdev;
+ int ret;
+
+ if (!dev || !name || !ops)
+ return ERR_PTR(-EINVAL);
+
+ hdev = scrub_device_register(dev, name, drvdata, ops, nregions);
+ if (IS_ERR(hdev))
+ return hdev;
+
+ ret = devm_add_action_or_reset(dev, devm_scrub_release, hdev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return hdev;
+}
+EXPORT_SYMBOL_GPL(devm_scrub_device_register);
+
+static int __init memory_scrub_control_init(void)
+{
+ int err;
+
+ err = class_register(&scrub_class);
+ if (err) {
+ pr_err("couldn't register memory scrub control sysfs class\n");
+ return err;
+ }
+
+ return 0;
+}
+subsys_initcall(memory_scrub_control_init);
diff --git a/include/memory/memory-scrub.h b/include/memory/memory-scrub.h
new file mode 100755
index 000000000000..d7cbde4718d0
--- /dev/null
+++ b/include/memory/memory-scrub.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Memory scrub controller driver support to configure
+ * the parameters of the memory scrubbers and enable.
+ *
+ * Copyright (c) 2023 HiSilicon Limited.
+ */
+
+#ifndef __MEMORY_SCRUB_H
+#define __MEMORY_SCRUB_H
+
+#include <linux/types.h>
+
+enum scrub_types {
+ scrub_common,
+ scrub_max,
+};
+
+enum scrub_attributes {
+ /* scrub attributes - common */
+ scrub_addr_base,
+ scrub_addr_size,
+ scrub_enable,
+ scrub_speed,
+ scrub_speed_available,
+ max_attrs,
+};
+
+/**
+ * struct scrub_ops - scrub device operations
+ * @is_visible: Callback to return attribute visibility. Mandatory.
+ * Parameters are:
+ * @drvdata:
+ * pointer to driver-private data structure passed
+ * as argument to scrub_device_register().
+ * @attr: scrubber attribute
+ * @region_id:
+ * memory region id
+ * The function returns the file permissions.
+ * If the return value is 0, no attribute will be created.
+ * @read: Read callback for data attributes. Mandatory if readable
+ * data attributes are present.
+ * Parameters are:
+ * @dev: pointer to hardware scrub device
+ * @attr: scrubber attribute
+ * @region_id:
+ * memory region id
+ * @val: pointer to returned value
+ * The function returns 0 on success or a negative error number.
+ * @read_string: Read callback for string attributes. Mandatory if string
+ * attributes are present.
+ * Parameters are:
+ * @dev: pointer to hardware scrub device
+ * @attr: scrubber attribute
+ * @region_id:
+ * memory region id
+ * @buf: pointer to buffer to copy string
+ * The function returns 0 on success or a negative error number.
+ * @write: Write callback for data attributes. Mandatory if writeable
+ * data attributes are present.
+ * Parameters are:
+ * @dev: pointer to hardware scrub device
+ * @attr: scrubber attribute
+ * @region_id:
+ * memory region id
+ * @val: value to write
+ * The function returns 0 on success or a negative error number.
+ */
+struct scrub_ops {
+ umode_t (*is_visible)(const void *drvdata, u32 attr, int region_id);
+ int (*read)(struct device *dev, u32 attr, int region_id, u64 *val);
+ int (*read_string)(struct device *dev, u32 attr, int region_id, char *buf);
+ int (*write)(struct device *dev, u32 attr, int region_id, u64 val);
+};
+
+struct device *
+devm_scrub_device_register(struct device *dev, const char *name,
+ void *drvdata, const struct scrub_ops *ops,
+ int nregions);
+#endif /* __MEMORY_SCRUB_H */
--
2.34.1
From: Shiju Jose <[email protected]>
Add sysfs documentation for the set of common scrub attributes those are
exposed in /sys/class/scrub/ by the scrub configure driver and support
user to configuring attributes of a scrub device.
Signed-off-by: Shiju Jose <[email protected]>
---
.../ABI/testing/sysfs-class-scrub-configure | 82 +++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-class-scrub-configure
diff --git a/Documentation/ABI/testing/sysfs-class-scrub-configure b/Documentation/ABI/testing/sysfs-class-scrub-configure
new file mode 100644
index 000000000000..5e965b3ad088
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-scrub-configure
@@ -0,0 +1,82 @@
+What: /sys/class/scrub/
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ The scrub/ class subdirectory belongs to the
+ scrubber subsystem.
+
+What: /sys/class/scrub/scrubX/
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ The /sys/class/scrub/scrub{0,1,2,3,...} directories
+ correspond to each scrub device.
+
+What: /sys/class/scrub/scrubX/name
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (RO) name of the memory scrub device
+
+What: /sys/class/scrub/scrubX/regionY/
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ The /sys/class/scrub/scrubX/region{0,1,2,3,...}
+ directories correspond to each scrub region under a scrub device.
+ Scrub region is a physical address range for which scrub may be
+ separately controlled. Regions may overlap in which case the
+ scrubbing rate of the overlapped memory will be at least that
+ expected due to each overlapping region.
+
+What: /sys/class/scrub/scrubX/regionY/addr_base
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (RW) The base of the address range of the memory region
+ to be scrubbed.
+ On reading, returns the base of the memory region for
+ the actual address range(The platform calculates
+ the nearest patrol scrub boundary address from where
+ it can start scrub).
+
+What: /sys/class/scrub/scrubX/regionY/addr_size
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (RW) The size of the address range to be scrubbed.
+ On reading, returns the size of the memory region for
+ the actual address range.
+
+What: /sys/class/scrub/scrubX/regionY/enable
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (WO) Start/Stop scrub the memory region.
+ 1 - enable the memory scrub.
+ 0 - disable the memory scrub..
+
+What: /sys/class/scrub/scrubX/regionY/speed_available
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (RO) Supported range for the scrub speed(scrub rate)
+ by the scrubber for a memory region.
+ The unit of the scrub rate vary depends on the scrub.
+
+What: /sys/class/scrub/scrubX/regionY/speed
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (RW) The scrub speed(scrub rate) on the memory region specified
+ and it must be with in the supported range by the scrub.
+ The unit of the scrub rate vary depends on the scrub.
--
2.34.1
From: Shiju Jose <[email protected]>
Add sysfs documentation for the CXL memory device scrub control
attributes those are exposed in /sys/class/scrub/ by the scrub
driver. These attributes support user configuring a CXL memory
device scrub.
Signed-off-by: Shiju Jose <[email protected]>
---
.../testing/sysfs-class-cxl-scrub-configure | 79 +++++++++++++++++++
1 file changed, 79 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-class-cxl-scrub-configure
diff --git a/Documentation/ABI/testing/sysfs-class-cxl-scrub-configure b/Documentation/ABI/testing/sysfs-class-cxl-scrub-configure
new file mode 100644
index 000000000000..3f55522134cd
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-cxl-scrub-configure
@@ -0,0 +1,79 @@
+See `Documentation/ABI/testing/sysfs-class-scrub-configure` for the
+documentation of common scrub configure directory layout (/sys/class/scrub/),
+including the attributes used for configuring the CXL patrol scrub.
+Following are the attributes used for configuring the CXL ECS.
+
+What: /sys/class/scrub/scrubX/regionY/ecs_log_entry_type
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (RW) The log entry type of how the DDR5 ECS log is
+ reported.
+ 00b - per DRAM.
+ 01b - per memory media FRU.
+
+What: /sys/class/scrub/scrubX/regionY/ecs_log_entry_type_per_dram
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (RO) Returns true if current log entry type of DDR5 ECS
+ region is per DRAM.
+
+What: /sys/class/scrub/scrubX/regionY/ecs_log_entry_type_per_memory_media
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (RO) Returns true if current log entry type of DDR5 ECS
+ region is per memory media FRU.
+
+What: /sys/class/scrub/scrubX/regionY/mode
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (RW) The mode of how the DDR5 ECS counts the errors.
+ 0 - ECS counts rows with errors.
+ 1 - ECS counts codewords with errors.
+
+What: /sys/class/scrub/scrubX/regionY/mode_counts_rows
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (RO) Returns true if current mode of DDR5 ECS region
+ is counts rows with errors.
+
+What: /sys/class/scrub/scrubX/regionY/mode_counts_codewords
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (RO) Returns true if current mode of DDR5 ECS region
+ is counts codewords with errors.
+
+What: /sys/class/scrub/scrubX/regionY/reset_counter
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (WO) DDR5 ECS reset ECC counter.
+ 0 - normal, ECC counter running actively.
+ 1 - reset ECC counter to the default value.
+
+What: /sys/class/scrub/scrubX/regionY/threshold
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (RW) DDR5 ECS threshold count per GB of memory cells.
+
+What: /sys/class/scrub/scrubX/regionY/threshold_available
+Date: November 2023
+KernelVersion: 6.8
+Contact: [email protected]
+Description:
+ (RO) Supported list of DDR5 ECS threshold count per GB of
+ memory cells.
--
2.34.1
From: Shiju Jose <[email protected]>
CXL spec 3.1 section 8.2.9.9.11.2 describes the DDR5 Error Check Scrub (ECS)
control feature.
The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM
Specification (JESD79-5) and allows the DRAM to internally read, correct
single-bit errors, and write back corrected data bits to the DRAM array
while providing transparency to error counts. The ECS control feature
allows the request to configure ECS input configurations during system
boot or at run-time.
The ECS control allows the requester to change the log entry type, the ECS
threshold count provided that the request is within the definition
specified in DDR5 mode registers, change mode between codeword mode and
row count mode, and reset the ECS counter.
Signed-off-by: Shiju Jose <[email protected]>
---
drivers/cxl/core/memscrub.c | 301 +++++++++++++++++++++++++++++++++++-
drivers/cxl/cxlmem.h | 3 +
drivers/cxl/pci.c | 1 +
3 files changed, 304 insertions(+), 1 deletion(-)
diff --git a/drivers/cxl/core/memscrub.c b/drivers/cxl/core/memscrub.c
index a74f4efa207e..7c58d56762b3 100644
--- a/drivers/cxl/core/memscrub.c
+++ b/drivers/cxl/core/memscrub.c
@@ -5,7 +5,7 @@
* Copyright (c) 2023 HiSilicon Limited.
*
* - Provides functions to configure patrol scrub
- * feature of the CXL memory devices.
+ * and DDR5 ECS features of the CXL memory devices.
*/
#define pr_fmt(fmt) "CXL_MEM_SCRUB: " fmt
@@ -264,3 +264,302 @@ int cxl_mem_patrol_scrub_init(struct cxl_memdev *cxlmd)
return 0;
}
EXPORT_SYMBOL_NS_GPL(cxl_mem_patrol_scrub_init, CXL);
+
+/* CXL DDR5 ECS control definitions */
+#define CXL_MEMDEV_ECS_GET_FEAT_VERSION 0x01
+#define CXL_MEMDEV_ECS_SET_FEAT_VERSION 0x01
+
+static const uuid_t cxl_ecs_uuid =
+ UUID_INIT(0xe5b13f22, 0x2328, 0x4a14, 0xb8, 0xba, 0xb9, 0x69, 0x1e, \
+ 0x89, 0x33, 0x86);
+
+struct cxl_ecs_context {
+ struct device *dev;
+ u16 nregions;
+ u16 get_feat_size;
+ u16 set_feat_size;
+};
+
+/**
+ * struct cxl_memdev_ecs_params - CXL memory DDR5 ECS parameter data structure.
+ * @log_entry_type: ECS log entry type, per DRAM or per memory media FRU.
+ * @threshold: ECS threshold count per GB of memory cells.
+ * @mode: codeword/row count mode
+ * 0 : ECS counts rows with errors
+ * 1 : ECS counts codeword with errors
+ * @reset_counter: [IN] reset ECC counter to default value.
+ */
+struct cxl_memdev_ecs_params {
+ u8 log_entry_type;
+ u16 threshold;
+ u8 mode;
+ bool reset_counter;
+};
+
+enum {
+ CXL_MEMDEV_ECS_PARAM_LOG_ENTRY_TYPE = 0,
+ CXL_MEMDEV_ECS_PARAM_THRESHOLD,
+ CXL_MEMDEV_ECS_PARAM_MODE,
+ CXL_MEMDEV_ECS_PARAM_RESET_COUNTER,
+};
+
+#define CXL_MEMDEV_ECS_LOG_ENTRY_TYPE_MASK GENMASK(1, 0)
+#define CXL_MEMDEV_ECS_REALTIME_REPORT_CAP_MASK BIT(0)
+#define CXL_MEMDEV_ECS_THRESHOLD_COUNT_MASK GENMASK(2, 0)
+#define CXL_MEMDEV_ECS_MODE_MASK BIT(3)
+#define CXL_MEMDEV_ECS_RESET_COUNTER_MASK BIT(4)
+
+static const u16 ecs_supp_threshold[] = { 0, 0, 0, 256, 1024, 4096 };
+
+enum {
+ ECS_LOG_ENTRY_TYPE_DRAM = 0x0,
+ ECS_LOG_ENTRY_TYPE_MEM_MEDIA_FRU = 0x1,
+};
+
+enum {
+ ECS_THRESHOLD_256 = 3,
+ ECS_THRESHOLD_1024 = 4,
+ ECS_THRESHOLD_4096 = 5,
+};
+
+enum {
+ ECS_MODE_COUNTS_ROWS = 0,
+ ECS_MODE_COUNTS_CODEWORDS = 1,
+};
+
+struct cxl_memdev_ecs_feat_read_attrbs {
+ u8 ecs_log_cap;
+ u8 ecs_cap;
+ __le16 ecs_config;
+ u8 ecs_flags;
+} __packed;
+
+struct cxl_memdev_ecs_set_feat_pi {
+ struct cxl_mbox_set_feat_in pi;
+ struct cxl_memdev_ecs_feat_wr_attrbs {
+ u8 ecs_log_cap;
+ __le16 ecs_config;
+ } __packed wr_attrbs[];
+} __packed;
+
+/* CXL DDR5 ECS control functions */
+static int cxl_mem_ecs_get_attrbs(struct device *dev, int fru_id,
+ struct cxl_memdev_ecs_params *params)
+{
+ struct cxl_memdev_ecs_feat_read_attrbs *rd_attrbs __free(kvfree) = NULL;
+ struct cxl_memdev *cxlmd = to_cxl_memdev(dev->parent);
+ struct cxl_dev_state *cxlds = cxlmd->cxlds;
+ struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
+ struct cxl_mbox_get_feat_in pi = {
+ .uuid = cxl_ecs_uuid,
+ .offset = 0,
+ .selection = CXL_GET_FEAT_SEL_CURRENT_VALUE,
+ };
+ struct cxl_ecs_context *cxl_ecs_ctx;
+ u8 threshold_index;
+ int ret;
+
+ if (!mds)
+ return -EFAULT;
+ cxl_ecs_ctx = dev_get_drvdata(dev);
+
+ pi.count = cxl_ecs_ctx->get_feat_size;
+ rd_attrbs = kvmalloc(pi.count, GFP_KERNEL);
+ if (!rd_attrbs)
+ return -ENOMEM;
+
+ ret = cxl_get_feature(mds, &pi, rd_attrbs);
+ if (ret) {
+ params->log_entry_type = 0;
+ params->threshold = 0;
+ params->mode = 0;
+ return ret;
+ }
+ params->log_entry_type = FIELD_GET(CXL_MEMDEV_ECS_LOG_ENTRY_TYPE_MASK,
+ rd_attrbs[fru_id].ecs_log_cap);
+ threshold_index = FIELD_GET(CXL_MEMDEV_ECS_THRESHOLD_COUNT_MASK,
+ rd_attrbs[fru_id].ecs_config);
+ params->threshold = ecs_supp_threshold[threshold_index];
+ params->mode = FIELD_GET(CXL_MEMDEV_ECS_MODE_MASK,
+ rd_attrbs[fru_id].ecs_config);
+
+ return 0;
+}
+
+static int __maybe_unused
+cxl_mem_ecs_set_attrbs(struct device *dev, int fru_id,
+ struct cxl_memdev_ecs_params *params, u8 param_type)
+{
+ struct cxl_memdev_ecs_feat_read_attrbs *rd_attrbs __free(kvfree) = NULL;
+ struct cxl_memdev_ecs_set_feat_pi *set_pi __free(kvfree) = NULL;
+ struct cxl_memdev *cxlmd = to_cxl_memdev(dev->parent);
+ struct cxl_dev_state *cxlds = cxlmd->cxlds;
+ struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);
+ struct cxl_mbox_get_feat_in pi = {
+ .uuid = cxl_ecs_uuid,
+ .offset = 0,
+ .selection = CXL_GET_FEAT_SEL_CURRENT_VALUE,
+ };
+ struct cxl_memdev_ecs_feat_wr_attrbs *wr_attrbs;
+ struct cxl_memdev_ecs_params rd_params;
+ struct cxl_ecs_context *cxl_ecs_ctx;
+ u16 nmedia_frus, count;
+ u32 set_pi_size;
+ int ret;
+
+ if (!mds)
+ return -EFAULT;
+
+ cxl_ecs_ctx = dev_get_drvdata(dev);
+ nmedia_frus = cxl_ecs_ctx->nregions;
+
+ rd_attrbs = kvmalloc(cxl_ecs_ctx->get_feat_size, GFP_KERNEL);
+ if (!rd_attrbs)
+ return -ENOMEM;
+
+ pi.count = cxl_ecs_ctx->get_feat_size;
+ ret = cxl_get_feature(mds, &pi, rd_attrbs);
+ if (ret)
+ return ret;
+ set_pi_size = sizeof(struct cxl_mbox_set_feat_in) +
+ cxl_ecs_ctx->set_feat_size;
+ set_pi = kvmalloc(set_pi_size, GFP_KERNEL);
+ if (!set_pi)
+ return -ENOMEM;
+
+ set_pi->pi.uuid = cxl_ecs_uuid;
+ set_pi->pi.flags = CXL_SET_FEAT_FLAG_MOD_VALUE_SAVED_ACROSS_RESET |
+ CXL_SET_FEAT_FLAG_FULL_DATA_TRANSFER;
+ set_pi->pi.offset = 0;
+ set_pi->pi.version = CXL_MEMDEV_ECS_SET_FEAT_VERSION;
+ /* Fill writable attributes from the current attributes read for all the media FRUs */
+ wr_attrbs = set_pi->wr_attrbs;
+ for (count = 0; count < nmedia_frus; count++) {
+ wr_attrbs[count].ecs_log_cap = rd_attrbs[count].ecs_log_cap;
+ wr_attrbs[count].ecs_config = rd_attrbs[count].ecs_config;
+ }
+
+ /* Fill attribute to be set for the media FRU */
+ switch (param_type) {
+ case CXL_MEMDEV_ECS_PARAM_LOG_ENTRY_TYPE:
+ if (params->log_entry_type != ECS_LOG_ENTRY_TYPE_DRAM &&
+ params->log_entry_type != ECS_LOG_ENTRY_TYPE_MEM_MEDIA_FRU) {
+ dev_err(dev->parent,
+ "Invalid CXL ECS scrub log entry type(%d) to set\n",
+ params->log_entry_type);
+ dev_err(dev->parent,
+ "Log Entry Type 0: per DRAM 1: per Memory Media FRU\n");
+ return -EINVAL;
+ }
+ wr_attrbs[fru_id].ecs_log_cap = FIELD_PREP(CXL_MEMDEV_ECS_LOG_ENTRY_TYPE_MASK,
+ params->log_entry_type);
+ break;
+ case CXL_MEMDEV_ECS_PARAM_THRESHOLD:
+ wr_attrbs[fru_id].ecs_config &= ~CXL_MEMDEV_ECS_THRESHOLD_COUNT_MASK;
+ switch (params->threshold) {
+ case 256:
+ wr_attrbs[fru_id].ecs_config |= FIELD_PREP(
+ CXL_MEMDEV_ECS_THRESHOLD_COUNT_MASK,
+ ECS_THRESHOLD_256);
+ break;
+ case 1024:
+ wr_attrbs[fru_id].ecs_config |= FIELD_PREP(
+ CXL_MEMDEV_ECS_THRESHOLD_COUNT_MASK,
+ ECS_THRESHOLD_1024);
+ break;
+ case 4096:
+ wr_attrbs[fru_id].ecs_config |= FIELD_PREP(
+ CXL_MEMDEV_ECS_THRESHOLD_COUNT_MASK,
+ ECS_THRESHOLD_4096);
+ break;
+ default:
+ dev_err(dev->parent,
+ "Invalid CXL ECS scrub threshold count(%d) to set\n",
+ params->threshold);
+ dev_err(dev->parent,
+ "Supported scrub threshold count: 256,1024,4096\n");
+ return -EINVAL;
+ }
+ break;
+ case CXL_MEMDEV_ECS_PARAM_MODE:
+ if (params->mode != ECS_MODE_COUNTS_ROWS &&
+ params->mode != ECS_MODE_COUNTS_CODEWORDS) {
+ dev_err(dev->parent,
+ "Invalid CXL ECS scrub mode(%d) to set\n",
+ params->mode);
+ dev_err(dev->parent,
+ "Mode 0: ECS counts rows with errors"
+ " 1: ECS counts codewords with errors\n");
+ return -EINVAL;
+ }
+ wr_attrbs[fru_id].ecs_config &= ~CXL_MEMDEV_ECS_MODE_MASK;
+ wr_attrbs[fru_id].ecs_config |= FIELD_PREP(CXL_MEMDEV_ECS_MODE_MASK,
+ params->mode);
+ break;
+ case CXL_MEMDEV_ECS_PARAM_RESET_COUNTER:
+ wr_attrbs[fru_id].ecs_config &= ~CXL_MEMDEV_ECS_RESET_COUNTER_MASK;
+ wr_attrbs[fru_id].ecs_config |= FIELD_PREP(CXL_MEMDEV_ECS_RESET_COUNTER_MASK,
+ params->reset_counter);
+ break;
+ default:
+ dev_err(dev->parent, "Invalid CXL ECS parameter to set\n");
+ return -EINVAL;
+ }
+ ret = cxl_set_feature(mds, set_pi, set_pi_size);
+ if (ret) {
+ dev_err(dev->parent, "CXL ECS set feature fail ret=%d\n", ret);
+ return ret;
+ }
+
+ /* Verify attribute is set successfully */
+ ret = cxl_mem_ecs_get_attrbs(dev, fru_id, &rd_params);
+ if (ret) {
+ dev_err(dev->parent, "Get cxlmemdev ECS params fail ret=%d\n", ret);
+ return ret;
+ }
+ switch (param_type) {
+ case CXL_MEMDEV_ECS_PARAM_LOG_ENTRY_TYPE:
+ if (rd_params.log_entry_type != params->log_entry_type)
+ return -EFAULT;
+ break;
+ case CXL_MEMDEV_ECS_PARAM_THRESHOLD:
+ if (rd_params.threshold != params->threshold)
+ return -EFAULT;
+ break;
+ case CXL_MEMDEV_ECS_PARAM_MODE:
+ if (rd_params.mode != params->mode)
+ return -EFAULT;
+ break;
+ }
+
+ return 0;
+}
+
+int cxl_mem_ddr5_ecs_init(struct cxl_memdev *cxlmd)
+{
+ struct cxl_mbox_supp_feat_entry feat_entry;
+ struct cxl_ecs_context *cxl_ecs_ctx;
+ int nmedia_frus;
+ int ret;
+
+ ret = cxl_mem_get_supported_feature_entry(cxlmd, &cxl_ecs_uuid, &feat_entry);
+ if (ret < 0)
+ return ret;
+
+ if (!(feat_entry.attrb_flags & CXL_FEAT_ENTRY_FLAG_CHANGABLE))
+ return -ENOTSUPP;
+ nmedia_frus = feat_entry.get_feat_size/
+ sizeof(struct cxl_memdev_ecs_feat_read_attrbs);
+ if (nmedia_frus) {
+ cxl_ecs_ctx = devm_kzalloc(&cxlmd->dev, sizeof(*cxl_ecs_ctx), GFP_KERNEL);
+ if (!cxl_ecs_ctx)
+ return -ENOMEM;
+
+ cxl_ecs_ctx->nregions = nmedia_frus;
+ cxl_ecs_ctx->get_feat_size = feat_entry.get_feat_size;
+ cxl_ecs_ctx->set_feat_size = feat_entry.set_feat_size;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(cxl_mem_ddr5_ecs_init, CXL);
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 25c46e72af16..c704d5c28d0d 100644
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -986,9 +986,12 @@ int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa);
/* cxl memory scrub functions */
#ifdef CONFIG_CXL_SCRUB
int cxl_mem_patrol_scrub_init(struct cxl_memdev *cxlmd);
+int cxl_mem_ddr5_ecs_init(struct cxl_memdev *cxlmd);
#else
static inline int cxl_mem_patrol_scrub_init(struct cxl_memdev *cxlmd)
{ return -ENOTSUPP; }
+static inline int cxl_mem_ddr5_ecs_init(struct cxl_memdev *cxlmd)
+{ return -ENOTSUPP; }
#endif
#ifdef CONFIG_CXL_SUSPEND
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index acc337b8c365..433a6cba94df 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -885,6 +885,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
* Initialize optional CXL scrub features
*/
cxl_mem_patrol_scrub_init(cxlmd);
+ cxl_mem_ddr5_ecs_init(cxlmd);
rc = devm_cxl_sanitize_setup_notifier(&pdev->dev, cxlmd);
if (rc)
--
2.34.1
Hi Shiju,
I have some general feedback at this point before digging too deep into
the details:
shiju.jose@ wrote:
> From: Shiju Jose <[email protected]>
>
> 1. Add support for CXL feature mailbox commands.
> 2. Add CXL device scrub driver supporting patrol scrub control and DDR5 ECS
> control features.
> 3. Add scrub driver supports configuring memory scrubs in the system.
> 4. Add scrub attributes for DDR5 ECS control to the memory scrub driver.
For a new a subsystem that is meant to generically abstract a "memory
scrub" facility the "DDR5 ECS" naming has too much precision. How much
of this interface is DDR5 ECS specific and how much of it is applicable
to a theoretical DDR6 scrub implementation?
My primary reaction is to boil down this interface so that only generic
scrub details are visible in the ABI, and DDR5 specifics are invisible
in the sysfs ABI.
For example the Linux NVDIMM subsystem has an address-range-scrub
facility that is independent of the specific memory technology scrub
mechanism. That one is based on ACPI NFIT, but I realize you also looked
at enabling the ACPI RASF scrub interface. It would be useful if this
patchset could plausibly enable one non-CXL scrubber along with the CXL
one.
> 5. Register CXL device patrol scrub and ECS with scrub control driver.
> 6. Add documentation for common attributes in the scrub configure driver.
Going forward, please include the Documentation in the patch that adds
the new ABI, it improves the readability / story-telling of the patches.
It also makes it easier to analyze which code is needed for which ABI,
and whether a given ABI is justified.
The regionY nomenclature in the sysfs ABI looks like a potential
opportunity to align with the "memregion" id scheme. See all the callers
of memregion_alloc() where those are tagging device-backed physical
address ranges with a common id namespace. It would be great if the
memory-scrub ABI reported failures in terms of region-ids that correlate
with CXL, DAX, or NVDIMM regions.
> 7. Add documentation for CXL memory device scrub control attributes.
Do the CXL specifics need to be in the ABI? One thing I missed was how
the series of log entries are conveyed. For CXL in contrast to what
NVDIMM did for address range scrub is that CXL makes use of trace-events
to emit log records. That allows the sysfs ABI to remain relatively
simple, but the various trace-events can get into more protocol specific
details. For example, see cxl_trigger_poison_list() and
trace_cxl_poison() as a way to genericly trigger the listing of a flow
of device-specific details. In other words put the DDR5 ECS specifics in
the trace-event, not the sysfs ABI if possible.
Lastly, dynamically defined sysfs groups are less palatable than
statically defined. See cxl_region_target_visible() for a scheme for
statically defining a runtime variable number of attributes.
Specifically I would like to see a way to define this new subsystem
without scrub_create_attrs() and all the runtime attribute definition.
Overall, I like the general approach to define a common subsystem for
this, and get off the treadmill of reinventing custom scrub interfaces
per bus, but that also requires that it be generic enough to subsume a
number of those per-bus-scrub-types.
Hi Dan,
Thanks for the feedbacks.
>-----Original Message-----
>From: Dan Williams <[email protected]>
>Sent: 06 December 2023 19:39
>To: Shiju Jose <[email protected]>; [email protected]; linux-
>[email protected]; [email protected]; Jonathan Cameron
><[email protected]>; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]
>Cc: [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected]; [email protected];
>[email protected]; [email protected];
>[email protected]; [email protected];
>tanxiaofei <[email protected]>; Zengtao (B) <[email protected]>;
>[email protected]; wanghuiqiang <[email protected]>;
>Linuxarm <[email protected]>; Shiju Jose <[email protected]>
>Subject: RE: [PATCH v4 00/11] cxl: Add support for CXL feature commands, CXL
>device patrol scrub control and DDR5 ECS control features
>
>Hi Shiju,
>
>I have some general feedback at this point before digging too deep into the
>details:
>
>shiju.jose@ wrote:
>> From: Shiju Jose <[email protected]>
>>
>> 1. Add support for CXL feature mailbox commands.
>> 2. Add CXL device scrub driver supporting patrol scrub control and
>> DDR5 ECS control features.
>> 3. Add scrub driver supports configuring memory scrubs in the system.
>> 4. Add scrub attributes for DDR5 ECS control to the memory scrub driver.
>
>For a new a subsystem that is meant to generically abstract a "memory scrub"
>facility the "DDR5 ECS" naming has too much precision. How much of this
>interface is DDR5 ECS specific and how much of it is applicable to a theoretical
>DDR6 scrub implementation?
>
>My primary reaction is to boil down this interface so that only generic scrub
>details are visible in the ABI, and DDR5 specifics are invisible in the sysfs ABI.
Sure. I will check this.
>
>For example the Linux NVDIMM subsystem has an address-range-scrub facility
>that is independent of the specific memory technology scrub mechanism. That
>one is based on ACPI NFIT, but I realize you also looked at enabling the ACPI
>RASF scrub interface. It would be useful if this patchset could plausibly enable
>one non-CXL scrubber along with the CXL one.
Sure. I will do this. I will add ACPI RASF scrub patches to this patch set.
>
>> 5. Register CXL device patrol scrub and ECS with scrub control driver.
>> 6. Add documentation for common attributes in the scrub configure driver.
>
>Going forward, please include the Documentation in the patch that adds the new
>ABI, it improves the readability / story-telling of the patches.
>It also makes it easier to analyze which code is needed for which ABI, and
>whether a given ABI is justified.
I will do.
>
>The regionY nomenclature in the sysfs ABI looks like a potential opportunity to
>align with the "memregion" id scheme. See all the callers of memregion_alloc()
>where those are tagging device-backed physical address ranges with a common
>id namespace. It would be great if the memory-scrub ABI reported failures in
>terms of region-ids that correlate with CXL, DAX, or NVDIMM regions.
For the CXL DDR5 ECS feature, presently the regionY corresponds to the IDs of the
memory media FRUs (1 to N), defined in the DDR5 ECS Control Feature tables Table 8-210 and Table 8-211.
>
>> 7. Add documentation for CXL memory device scrub control attributes.
>
>Do the CXL specifics need to be in the ABI? One thing I missed was how the
Ok. I will remove. Should these DDR5 ECS specifics consider as generic and
be part of the memory scrub ABI?
>series of log entries are conveyed. For CXL in contrast to what NVDIMM did for
>address range scrub is that CXL makes use of trace-events to emit log records.
>That allows the sysfs ABI to remain relatively simple, but the various trace-
>events can get into more protocol specific details. For example, see
>cxl_trigger_poison_list() and
>trace_cxl_poison() as a way to genericly trigger the listing of a flow of device-
>specific details. In other words put the DDR5 ECS specifics in the trace-event, not
>the sysfs ABI if possible.
Did you mean remove the readable attributes for DDR5 ECS from the sysfs?
For example the "ECS Threshold Count per Gb of Memory Cells" and "Codeword/Row Count Mode"
in the Table 8-78 DDR5 ECS log of section 8.2.9.5.2.4 DDR5 Error Check Scrub (ECS) Log.
>
>Lastly, dynamically defined sysfs groups are less palatable than statically
>defined. See cxl_region_target_visible() for a scheme for statically defining a
>runtime variable number of attributes.
>Specifically I would like to see a way to define this new subsystem without
>scrub_create_attrs() and all the runtime attribute definition.
>
Sure. I will check this.
>Overall, I like the general approach to define a common subsystem for this, and
>get off the treadmill of reinventing custom scrub interfaces per bus, but that
>also requires that it be generic enough to subsume a number of those per-bus-
>scrub-types.
This is the challenging part to make the scrub interface generic because the scrub control
varies between the scrub types, for example as seen in the CXL ECS.
Thanks,
Shiju