The patch adds description for DT binding for a new Exynos5422 Dynamic
Memory Controller device.
Signed-off-by: Lukasz Luba <[email protected]>
---
.../memory-controllers/exynos5422-dmc.txt | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
new file mode 100644
index 000000000000..989ee0839fdf
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
@@ -0,0 +1,84 @@
+* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
+
+The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
+memory chips are connected. The driver is to monitor the controller in runtime
+and switch frequency and voltage. To monitor the usage of the controller in
+runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
+is able to measure the current load of the memory.
+When 'userspace' governor is used for the driver, an application is able to
+switch the DMC and memory frequency.
+
+Required properties for DMC device for Exynos5422:
+- compatible: Should be "samsung,exynos5422-dmc".
+- clocks : list of clock specifiers, must contain an entry for each
+ required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
+ CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,
+ CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,
+ CLK_DOUT_CLK2X_PHY0, CLK_CLKM_PHY0, CLK_CLKM_PHY1
+- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
+ "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",
+ "mout_mx_mspll_ccore_phy", "mout_mclk_cdrex", "dout_clk2x_phy0", "clkm_phy0",
+ "clkm_phy1" entries
+- devfreq-events : phandles for PPMU devices connected to this DMC.
+- vdd-supply : phandle for voltage regulator which is connected.
+- reg : registers of two CDREX controllers.
+- operating-points-v2 : phandle for OPPs described in v2 definition.
+- device-handle : phandle of the connected DRAM memory device. For more
+ information please refer to documentation file:
+ Documentation/devicetree/bindings/ddr/lpddr3.txt
+- devfreq-events : phandles of the PPMU events used by the controller.
+- samsung,syscon-clk : phandle of the clock register set used by the controller,
+ these registers are used for enabling a 'pause' feature and are not
+ exposed by clock framework but they must be used in a safe way.
+ The register offsets are in the driver code and specyfic for this SoC
+ type.
+
+Example:
+
+ ppmu_dmc0_0: ppmu@10d00000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d00000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
+ event-name = "ppmu-event3-dmc0_0";
+ };
+ };
+ };
+
+ dmc: memory-controller@10c20000 {
+ compatible = "samsung,exynos5422-dmc";
+ reg = <0x10c20000 0x100>, <0x10c30000 0x100>,
+ clocks = <&clock CLK_FOUT_SPLL>,
+ <&clock CLK_MOUT_SCLK_SPLL>,
+ <&clock CLK_FF_DOUT_SPLL2>,
+ <&clock CLK_FOUT_BPLL>,
+ <&clock CLK_MOUT_BPLL>,
+ <&clock CLK_SCLK_BPLL>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
+ <&clock CLK_MOUT_MCLK_CDREX>,
+ <&clock CLK_DOUT_CLK2X_PHY0>,
+ <&clock CLK_CLKM_PHY0>,
+ <&clock CLK_CLKM_PHY1>;
+ clock-names = "fout_spll",
+ "mout_sclk_spll",
+ "ff_dout_spll2",
+ "fout_bpll",
+ "mout_bpll",
+ "sclk_bpll",
+ "mout_mx_mspll_ccore",
+ "mout_mx_mspll_ccore_phy",
+ "mout_mclk_cdrex",
+ "dout_clk2x_phy0",
+ "clkm_phy0",
+ "clkm_phy1";
+ operating-points-v2 = <&dmc_opp_table>;
+ devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
+ <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
+ operating-points-v2 = <&dmc_opp_table>;
+ device-handle = <&samsung_K3QF2F20DB>;
+ vdd-supply = <&buck1_reg>;
+ samsung,syscon-clk = <&clock>;
+ };
--
2.17.1
On Wed, 5 Jun 2019 at 18:54, Lukasz Luba <[email protected]> wrote:
>
> The patch adds description for DT binding for a new Exynos5422 Dynamic
> Memory Controller device.
>
> Signed-off-by: Lukasz Luba <[email protected]>
> ---
> .../memory-controllers/exynos5422-dmc.txt | 84 +++++++++++++++++++
> 1 file changed, 84 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
> new file mode 100644
> index 000000000000..989ee0839fdf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
> @@ -0,0 +1,84 @@
> +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
> +
> +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
> +memory chips are connected. The driver is to monitor the controller in runtime
> +and switch frequency and voltage. To monitor the usage of the controller in
> +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
> +is able to measure the current load of the memory.
> +When 'userspace' governor is used for the driver, an application is able to
> +switch the DMC and memory frequency.
> +
> +Required properties for DMC device for Exynos5422:
> +- compatible: Should be "samsung,exynos5422-dmc".
> +- clocks : list of clock specifiers, must contain an entry for each
> + required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
> + CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,
> + CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,
> + CLK_DOUT_CLK2X_PHY0, CLK_CLKM_PHY0, CLK_CLKM_PHY1
> +- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
> + "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",
> + "mout_mx_mspll_ccore_phy", "mout_mclk_cdrex", "dout_clk2x_phy0", "clkm_phy0",
> + "clkm_phy1" entries
> +- devfreq-events : phandles for PPMU devices connected to this DMC.
> +- vdd-supply : phandle for voltage regulator which is connected.
> +- reg : registers of two CDREX controllers.
> +- operating-points-v2 : phandle for OPPs described in v2 definition.
> +- device-handle : phandle of the connected DRAM memory device. For more
> + information please refer to documentation file:
> + Documentation/devicetree/bindings/ddr/lpddr3.txt
> +- devfreq-events : phandles of the PPMU events used by the controller.
> +- samsung,syscon-clk : phandle of the clock register set used by the controller,
> + these registers are used for enabling a 'pause' feature and are not
> + exposed by clock framework but they must be used in a safe way.
> + The register offsets are in the driver code and specyfic for this SoC
> + type.
> +
> +Example:
> +
> + ppmu_dmc0_0: ppmu@10d00000 {
> + compatible = "samsung,exynos-ppmu";
> + reg = <0x10d00000 0x2000>;
> + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
> + clock-names = "ppmu";
> + events {
> + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
> + event-name = "ppmu-event3-dmc0_0";
> + };
> + };
> + };
> +
> + dmc: memory-controller@10c20000 {
> + compatible = "samsung,exynos5422-dmc";
> + reg = <0x10c20000 0x100>, <0x10c30000 0x100>,
> + clocks = <&clock CLK_FOUT_SPLL>,
I think you should not have tab after '='. Instead align consecutive
lines with the first one.
> + <&clock CLK_MOUT_SCLK_SPLL>,
> + <&clock CLK_FF_DOUT_SPLL2>,
> + <&clock CLK_FOUT_BPLL>,
> + <&clock CLK_MOUT_BPLL>,
> + <&clock CLK_SCLK_BPLL>,
> + <&clock CLK_MOUT_MX_MSPLL_CCORE>,
> + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
> + <&clock CLK_MOUT_MCLK_CDREX>,
> + <&clock CLK_DOUT_CLK2X_PHY0>,
> + <&clock CLK_CLKM_PHY0>,
> + <&clock CLK_CLKM_PHY1>;
> + clock-names = "fout_spll",
> + "mout_sclk_spll",
> + "ff_dout_spll2",
> + "fout_bpll",
> + "mout_bpll",
> + "sclk_bpll",
> + "mout_mx_mspll_ccore",
> + "mout_mx_mspll_ccore_phy",
> + "mout_mclk_cdrex",
> + "dout_clk2x_phy0",
> + "clkm_phy0",
> + "clkm_phy1";
> + operating-points-v2 = <&dmc_opp_table>;
> + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
> + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
> + operating-points-v2 = <&dmc_opp_table>;
Duplicated property.
Beside that:
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
> + device-handle = <&samsung_K3QF2F20DB>;
> + vdd-supply = <&buck1_reg>;
> + samsung,syscon-clk = <&clock>;
> + };
> --
> 2.17.1
>
Hi Krzysztof,
On 6/6/19 10:29 AM, Krzysztof Kozlowski wrote:
> On Wed, 5 Jun 2019 at 18:54, Lukasz Luba <[email protected]> wrote:
>>
>> The patch adds description for DT binding for a new Exynos5422 Dynamic
>> Memory Controller device.
>>
>> Signed-off-by: Lukasz Luba <[email protected]>
>> ---
>> .../memory-controllers/exynos5422-dmc.txt | 84 +++++++++++++++++++
>> 1 file changed, 84 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
>> new file mode 100644
>> index 000000000000..989ee0839fdf
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
>> @@ -0,0 +1,84 @@
>> +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
>> +
>> +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
>> +memory chips are connected. The driver is to monitor the controller in runtime
>> +and switch frequency and voltage. To monitor the usage of the controller in
>> +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
>> +is able to measure the current load of the memory.
>> +When 'userspace' governor is used for the driver, an application is able to
>> +switch the DMC and memory frequency.
>> +
>> +Required properties for DMC device for Exynos5422:
>> +- compatible: Should be "samsung,exynos5422-dmc".
>> +- clocks : list of clock specifiers, must contain an entry for each
>> + required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
>> + CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,
>> + CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,
>> + CLK_DOUT_CLK2X_PHY0, CLK_CLKM_PHY0, CLK_CLKM_PHY1
>> +- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
>> + "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",
>> + "mout_mx_mspll_ccore_phy", "mout_mclk_cdrex", "dout_clk2x_phy0", "clkm_phy0",
>> + "clkm_phy1" entries
>> +- devfreq-events : phandles for PPMU devices connected to this DMC.
>> +- vdd-supply : phandle for voltage regulator which is connected.
>> +- reg : registers of two CDREX controllers.
>> +- operating-points-v2 : phandle for OPPs described in v2 definition.
>> +- device-handle : phandle of the connected DRAM memory device. For more
>> + information please refer to documentation file:
>> + Documentation/devicetree/bindings/ddr/lpddr3.txt
>> +- devfreq-events : phandles of the PPMU events used by the controller.
>> +- samsung,syscon-clk : phandle of the clock register set used by the controller,
>> + these registers are used for enabling a 'pause' feature and are not
>> + exposed by clock framework but they must be used in a safe way.
>> + The register offsets are in the driver code and specyfic for this SoC
>> + type.
>> +
>> +Example:
>> +
>> + ppmu_dmc0_0: ppmu@10d00000 {
>> + compatible = "samsung,exynos-ppmu";
>> + reg = <0x10d00000 0x2000>;
>> + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
>> + clock-names = "ppmu";
>> + events {
>> + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
>> + event-name = "ppmu-event3-dmc0_0";
>> + };
>> + };
>> + };
>> +
>> + dmc: memory-controller@10c20000 {
>> + compatible = "samsung,exynos5422-dmc";
>> + reg = <0x10c20000 0x100>, <0x10c30000 0x100>,
>> + clocks = <&clock CLK_FOUT_SPLL>,
>
> I think you should not have tab after '='. Instead align consecutive
> lines with the first one.
I will change it, since there is a need of removing the duplicates below
>
>> + <&clock CLK_MOUT_SCLK_SPLL>,
>> + <&clock CLK_FF_DOUT_SPLL2>,
>> + <&clock CLK_FOUT_BPLL>,
>> + <&clock CLK_MOUT_BPLL>,
>> + <&clock CLK_SCLK_BPLL>,
>> + <&clock CLK_MOUT_MX_MSPLL_CCORE>,
>> + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
>> + <&clock CLK_MOUT_MCLK_CDREX>,
>> + <&clock CLK_DOUT_CLK2X_PHY0>,
>> + <&clock CLK_CLKM_PHY0>,
>> + <&clock CLK_CLKM_PHY1>;
>> + clock-names = "fout_spll",
>> + "mout_sclk_spll",
>> + "ff_dout_spll2",
>> + "fout_bpll",
>> + "mout_bpll",
>> + "sclk_bpll",
>> + "mout_mx_mspll_ccore",
>> + "mout_mx_mspll_ccore_phy",
>> + "mout_mclk_cdrex",
>> + "dout_clk2x_phy0",
>> + "clkm_phy0",
>> + "clkm_phy1";
>> + operating-points-v2 = <&dmc_opp_table>;
>> + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
>> + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
>> + operating-points-v2 = <&dmc_opp_table>;
>
> Duplicated property.
Right, I will remove it and re-send it.
>
> Beside that:
> Acked-by: Krzysztof Kozlowski <[email protected]>
Thank you
Regards,
Lukasz
>
> Best regards,
> Krzysztof
>
>> + device-handle = <&samsung_K3QF2F20DB>;
>> + vdd-supply = <&buck1_reg>;
>> + samsung,syscon-clk = <&clock>;
>> + };
>> --
>> 2.17.1
>>
>
>