The patchset fixes some warnings reported by the kernel during boot.
The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section
2.2.1 Master Processor.
The cache line size and the set-associative info are from Cortex-A53
Documentation [2].
From the doc, it can be concluded that L1 i-cache is 4-way assoc, L1
d-cache is 2-way assoc and L2 cache is 16-way assoc. Calculate the dts
props accordingly.
Also, to use KVM's VGIC code, GICH, GICV registers spaces and maintenance
IRQ are added to the dts with verification.
[1]: https://github.com/96boards/documentation/blob/master/enterprise/poplar/hardware-docs/Processor_Datasheet_v2XX.pdf
[2]: https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System
Signed-off-by: Yang Xiwen <[email protected]>
---
Changes in v3:
- send patches to stable (Andrew Lunn)
- rewrite the commit logs more formally (Andrew Lunn)
- rename l2-cache0 to l2-cache (Krzysztof Kozlowski)
- Link to v2: https://lore.kernel.org/r/[email protected]
Changes in v2:
- arm64: dts: hi3798cv200: add GICH, GICV register spces and
maintainance IRQ.
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Yang Xiwen (3):
arm64: dts: hi3798cv200: fix the size of GICR
arm64: dts: hi3798cv200: add GICH, GICV register space and irq
arm64: dts: hi3798cv200: add cache info
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
---
base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d
change-id: 20240218-cache-11c8bf7566c2
Best regards,
--
Yang Xiwen <[email protected]>
From: Yang Xiwen <[email protected]>
During boot, Linux kernel complains:
[ 0.000000] GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
This SoC is using a regular GIC-400 and the GICR space size should be
8KB rather than 256B.
With this patch:
[ 0.000000] GIC: Using split EOI/Deactivate mode
So this should be the correct fix.
Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board")
Signed-off-by: Yang Xiwen <[email protected]>
Cc: [email protected]
---
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index ed1b5a7a6067..d01023401d7e 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -58,7 +58,7 @@ cpu@3 {
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
- <0x0 0xf1002000 0x0 0x100>; /* GICC */
+ <0x0 0xf1002000 0x0 0x2000>; /* GICC */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
--
2.43.0
On 2/19/2024 11:05 PM, Yang Xiwen via B4 Relay wrote:
> The patchset fixes some warnings reported by the kernel during boot.
>
> The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section
> 2.2.1 Master Processor.
>
> The cache line size and the set-associative info are from Cortex-A53
> Documentation [2].
>
> From the doc, it can be concluded that L1 i-cache is 4-way assoc, L1
> d-cache is 2-way assoc and L2 cache is 16-way assoc. Calculate the dts
> props accordingly.
>
> Also, to use KVM's VGIC code, GICH, GICV registers spaces and maintenance
> IRQ are added to the dts with verification.
>
> [1]: https://github.com/96boards/documentation/blob/master/enterprise/poplar/hardware-docs/Processor_Datasheet_v2XX.pdf
> [2]: https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System
>
> Signed-off-by: Yang Xiwen <[email protected]>
> ---
> Changes in v3:
> - send patches to stable (Andrew Lunn)
> - rewrite the commit logs more formally (Andrew Lunn)
> - rename l2-cache0 to l2-cache (Krzysztof Kozlowski)
> - Link to v2: https://lore.kernel.org/r/[email protected]
>
> Changes in v2:
> - arm64: dts: hi3798cv200: add GICH, GICV register spces and
> maintainance IRQ.
> - Link to v1: https://lore.kernel.org/r/[email protected]
>
> ---
> Yang Xiwen (3):
> arm64: dts: hi3798cv200: fix the size of GICR
> arm64: dts: hi3798cv200: add GICH, GICV register space and irq
> arm64: dts: hi3798cv200: add cache info
>
> arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++-
> 1 file changed, 42 insertions(+), 1 deletion(-)
> ---
> base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d
> change-id: 20240218-cache-11c8bf7566c2
>
> Best regards,
May someone apply this patchset to their tree so that it can land in
stable at the end? This is a fix, not adding new functionalities. It's
been 2 weeks already.
--
Regards,
Yang Xiwen
Hi Yang,
On 2024/3/12 19:19, Yang Xiwen wrote:
> On 2/19/2024 11:05 PM, Yang Xiwen via B4 Relay wrote:
>> The patchset fixes some warnings reported by the kernel during boot.
>>
>> The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section
>> 2.2.1 Master Processor.
>>
>> The cache line size and the set-associative info are from Cortex-A53
>> Documentation [2].
>>
>> From the doc, it can be concluded that L1 i-cache is 4-way assoc, L1
>> d-cache is 2-way assoc and L2 cache is 16-way assoc. Calculate the dts
>> props accordingly.
>>
>> Also, to use KVM's VGIC code, GICH, GICV registers spaces and maintenance
>> IRQ are added to the dts with verification.
>>
>> [1]: https://github.com/96boards/documentation/blob/master/enterprise/poplar/hardware-docs/Processor_Datasheet_v2XX.pdf
>> [2]: https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System
>>
>> Signed-off-by: Yang Xiwen <[email protected]>
>> ---
>> Changes in v3:
>> - send patches to stable (Andrew Lunn)
>> - rewrite the commit logs more formally (Andrew Lunn)
>> - rename l2-cache0 to l2-cache (Krzysztof Kozlowski)
>> - Link to v2: https://lore.kernel.org/r/[email protected]
>>
>> Changes in v2:
>> - arm64: dts: hi3798cv200: add GICH, GICV register spces and
>> maintainance IRQ.
>> - Link to v1: https://lore.kernel.org/r/[email protected]
>>
>> ---
>> Yang Xiwen (3):
>> arm64: dts: hi3798cv200: fix the size of GICR
>> arm64: dts: hi3798cv200: add GICH, GICV register space and irq
>> arm64: dts: hi3798cv200: add cache info
>>
>> arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++-
>> 1 file changed, 42 insertions(+), 1 deletion(-)
>> ---
>> base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d
>> change-id: 20240218-cache-11c8bf7566c2
>>
>> Best regards,
>
> May someone apply this patchset to their tree so that it can land in stable at the end? This is a fix, not adding new functionalities. It's been 2 weeks already.
>
Sorry for the delay, I am too busy to catch up with this cycle.
I will go through this patch set and maybe apply it during the next cycle.
Best Regards,
Wei
On 12/03/2024 12:19, Yang Xiwen wrote:
>> Yang Xiwen (3):
>> arm64: dts: hi3798cv200: fix the size of GICR
>> arm64: dts: hi3798cv200: add GICH, GICV register space and irq
>> arm64: dts: hi3798cv200: add cache info
>>
>> arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++-
>> 1 file changed, 42 insertions(+), 1 deletion(-)
>> ---
>> base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d
>> change-id: 20240218-cache-11c8bf7566c2
>>
>> Best regards,
>
> May someone apply this patchset to their tree so that it can land in
> stable at the end? This is a fix, not adding new functionalities. It's
> been 2 weeks already.
It's merge window, what do you expect to happen now? Please observe the
process timelines.
For arm-soc usually the cut-off is around rc6. When did you send it?
Week before rc6, so a bit late.
Anyway, I bookmarked this patchset, so if no one applies within some
time after merge window, I'll take it.
Best regards,
Krzysztof
On 3/12/2024 7:33 PM, Wei Xu wrote:
> Hi Yang,
>
> On 2024/3/12 19:19, Yang Xiwen wrote:
>> On 2/19/2024 11:05 PM, Yang Xiwen via B4 Relay wrote:
>>> The patchset fixes some warnings reported by the kernel during boot.
>>>
>>> The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section
>>> 2.2.1 Master Processor.
>>>
>>> The cache line size and the set-associative info are from Cortex-A53
>>> Documentation [2].
>>>
>>> From the doc, it can be concluded that L1 i-cache is 4-way assoc, L1
>>> d-cache is 2-way assoc and L2 cache is 16-way assoc. Calculate the dts
>>> props accordingly.
>>>
>>> Also, to use KVM's VGIC code, GICH, GICV registers spaces and maintenance
>>> IRQ are added to the dts with verification.
>>>
>>> [1]: https://github.com/96boards/documentation/blob/master/enterprise/poplar/hardware-docs/Processor_Datasheet_v2XX.pdf
>>> [2]: https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System
>>>
>>> Signed-off-by: Yang Xiwen <[email protected]>
>>> ---
>>> Changes in v3:
>>> - send patches to stable (Andrew Lunn)
>>> - rewrite the commit logs more formally (Andrew Lunn)
>>> - rename l2-cache0 to l2-cache (Krzysztof Kozlowski)
>>> - Link to v2: https://lore.kernel.org/r/[email protected]
>>>
>>> Changes in v2:
>>> - arm64: dts: hi3798cv200: add GICH, GICV register spces and
>>> maintainance IRQ.
>>> - Link to v1: https://lore.kernel.org/r/[email protected]
>>>
>>> ---
>>> Yang Xiwen (3):
>>> arm64: dts: hi3798cv200: fix the size of GICR
>>> arm64: dts: hi3798cv200: add GICH, GICV register space and irq
>>> arm64: dts: hi3798cv200: add cache info
>>>
>>> arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++-
>>> 1 file changed, 42 insertions(+), 1 deletion(-)
>>> ---
>>> base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d
>>> change-id: 20240218-cache-11c8bf7566c2
>>>
>>> Best regards,
>> May someone apply this patchset to their tree so that it can land in stable at the end? This is a fix, not adding new functionalities. It's been 2 weeks already.
>>
> Sorry for the delay, I am too busy to catch up with this cycle.
> I will go through this patch set and maybe apply it during the next cycle.
No problem. I'm just a bit worried if this patch is getting lost. It's
good to know it's still maintained. Because i've seen some maintainers
not reviewing any patches for over 1 year already, with their names and
emails still in MAINTAINERS.
By the way, I think fixes and new features are in different cycles? Most
maintainers seem to have multiple branches to handle this.
>
> Best Regards,
> Wei
--
Regards,
Yang Xiwen
Hi Yang,
On 2024/3/12 19:46, Yang Xiwen wrote:
> On 3/12/2024 7:33 PM, Wei Xu wrote:
>> Hi Yang,
>>
>> On 2024/3/12 19:19, Yang Xiwen wrote:
>>> On 2/19/2024 11:05 PM, Yang Xiwen via B4 Relay wrote:
>>>> The patchset fixes some warnings reported by the kernel during boot.
>>>>
>>>> The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section
>>>> 2.2.1 Master Processor.
>>>>
>>>> The cache line size and the set-associative info are from Cortex-A53
>>>> Documentation [2].
>>>>
>>>> From the doc, it can be concluded that L1 i-cache is 4-way assoc, L1
>>>> d-cache is 2-way assoc and L2 cache is 16-way assoc. Calculate the dts
>>>> props accordingly.
>>>>
>>>> Also, to use KVM's VGIC code, GICH, GICV registers spaces and maintenance
>>>> IRQ are added to the dts with verification.
>>>>
>>>> [1]: https://github.com/96boards/documentation/blob/master/enterprise/poplar/hardware-docs/Processor_Datasheet_v2XX.pdf
>>>> [2]: https://developer.arm.com/documentation/ddi0500/j/Level-1-Memory-System
>>>>
>>>> Signed-off-by: Yang Xiwen <[email protected]>
>>>> ---
>>>> Changes in v3:
>>>> - send patches to stable (Andrew Lunn)
>>>> - rewrite the commit logs more formally (Andrew Lunn)
>>>> - rename l2-cache0 to l2-cache (Krzysztof Kozlowski)
>>>> - Link to v2: https://lore.kernel.org/r/[email protected]
>>>>
>>>> Changes in v2:
>>>> - arm64: dts: hi3798cv200: add GICH, GICV register spces and
>>>> maintainance IRQ.
>>>> - Link to v1: https://lore.kernel.org/r/[email protected]
>>>>
>>>> ---
>>>> Yang Xiwen (3):
>>>> arm64: dts: hi3798cv200: fix the size of GICR
>>>> arm64: dts: hi3798cv200: add GICH, GICV register space and irq
>>>> arm64: dts: hi3798cv200: add cache info
>>>>
>>>> arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++-
>>>> 1 file changed, 42 insertions(+), 1 deletion(-)
>>>> ---
>>>> base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d
>>>> change-id: 20240218-cache-11c8bf7566c2
>>>>
>>>> Best regards,
>>> May someone apply this patchset to their tree so that it can land in stable at the end? This is a fix, not adding new functionalities. It's been 2 weeks already.
>>>
>> Sorry for the delay, I am too busy to catch up with this cycle.
>> I will go through this patch set and maybe apply it during the next cycle.
>
>
> No problem. I'm just a bit worried if this patch is getting lost. It's good to know it's still maintained. Because i've seen some maintainers not reviewing any patches for over 1 year already, with their names and emails still in MAINTAINERS.
Thanks for the understanding!
>
>
> By the way, I think fixes and new features are in different cycles? Most maintainers seem to have multiple branches to handle this.
Yes, they can be in different cycle. But now is the merge window.
Best Regards,
Wei
>
>
>>
>> Best Regards,
>> Wei
>
>
Hi Krzysztof,
On 2024/3/12 19:36, Krzysztof Kozlowski wrote:
> On 12/03/2024 12:19, Yang Xiwen wrote:
>>> Yang Xiwen (3):
>>> arm64: dts: hi3798cv200: fix the size of GICR
>>> arm64: dts: hi3798cv200: add GICH, GICV register space and irq
>>> arm64: dts: hi3798cv200: add cache info
>>>
>>> arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 43 +++++++++++++++++++++++++-
>>> 1 file changed, 42 insertions(+), 1 deletion(-)
>>> ---
>>> base-commit: 8d3dea210042f54b952b481838c1e7dfc4ec751d
>>> change-id: 20240218-cache-11c8bf7566c2
>>>
>>> Best regards,
>>
>> May someone apply this patchset to their tree so that it can land in
>> stable at the end? This is a fix, not adding new functionalities. It's
>> been 2 weeks already.
>
> It's merge window, what do you expect to happen now? Please observe the
> process timelines.
>
> For arm-soc usually the cut-off is around rc6. When did you send it?
> Week before rc6, so a bit late.
>
> Anyway, I bookmarked this patchset, so if no one applies within some
> time after merge window, I'll take it.
Thanks for your explanation and kindness!
Best Regards,
Wei
>
> Best regards,
> Krzysztof
>
> .
>
On Mon, 19 Feb 2024 23:05:25 +0800, Yang Xiwen wrote:
> The patchset fixes some warnings reported by the kernel during boot.
>
> The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section
> 2.2.1 Master Processor.
>
> The cache line size and the set-associative info are from Cortex-A53
> Documentation [2].
>
> [...]
It's rc3 and almost one month after last ping/talk, so apparently these got
lost. I'll take them, but let me know if this should go via different tree.
Applied, thanks!
[1/3] arm64: dts: hi3798cv200: fix the size of GICR
https://git.kernel.org/krzk/linux-dt/c/428a575dc9038846ad259466d5ba109858c0a023
[2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq
https://git.kernel.org/krzk/linux-dt/c/f00a6b9644a5668e25ad9ca5aff53b6de4b0aaf6
[3/3] arm64: dts: hi3798cv200: add cache info
https://git.kernel.org/krzk/linux-dt/c/c7a3ad884d1dc1302dcc3295baa18917180b8bec
Best regards,
--
Krzysztof Kozlowski <[email protected]>
Hi Krzysztof,
On 2024/4/8 15:31, Krzysztof Kozlowski wrote:
>
> On Mon, 19 Feb 2024 23:05:25 +0800, Yang Xiwen wrote:
>> The patchset fixes some warnings reported by the kernel during boot.
>>
>> The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section
>> 2.2.1 Master Processor.
>>
>> The cache line size and the set-associative info are from Cortex-A53
>> Documentation [2].
>>
>> [...]
>
> It's rc3 and almost one month after last ping/talk, so apparently these got
> lost. I'll take them, but let me know if this should go via different tree.
>
>
> Applied, thanks!
Thanks!
Fine to me.
Best Regards,
Wei
>
> [1/3] arm64: dts: hi3798cv200: fix the size of GICR
> https://git.kernel.org/krzk/linux-dt/c/428a575dc9038846ad259466d5ba109858c0a023
> [2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq
> https://git.kernel.org/krzk/linux-dt/c/f00a6b9644a5668e25ad9ca5aff53b6de4b0aaf6
> [3/3] arm64: dts: hi3798cv200: add cache info
> https://git.kernel.org/krzk/linux-dt/c/c7a3ad884d1dc1302dcc3295baa18917180b8bec
>
> Best regards,
>
On 4/8/2024 3:31 PM, Krzysztof Kozlowski wrote:
> On Mon, 19 Feb 2024 23:05:25 +0800, Yang Xiwen wrote:
>> The patchset fixes some warnings reported by the kernel during boot.
>>
>> The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section
>> 2.2.1 Master Processor.
>>
>> The cache line size and the set-associative info are from Cortex-A53
>> Documentation [2].
>>
>> [...]
> It's rc3 and almost one month after last ping/talk, so apparently these got
> lost. I'll take them, but let me know if this should go via different tree.
Thanks a lot. From my experience, i think this should go via HiSilicon's
tree first(which stalls now), then go to SOC tree
(git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git), finally in
torvald's tree. This was the case for some qcom dts changes about 1yr ago.
>
>
> Applied, thanks!
>
> [1/3] arm64: dts: hi3798cv200: fix the size of GICR
> https://git.kernel.org/krzk/linux-dt/c/428a575dc9038846ad259466d5ba109858c0a023
> [2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq
> https://git.kernel.org/krzk/linux-dt/c/f00a6b9644a5668e25ad9ca5aff53b6de4b0aaf6
> [3/3] arm64: dts: hi3798cv200: add cache info
> https://git.kernel.org/krzk/linux-dt/c/c7a3ad884d1dc1302dcc3295baa18917180b8bec
>
> Best regards,
--
Regards,
Yang Xiwen