This patch series tries to remove most of the imx6 and imx7 board
specific PHY configuration via fixup, as this breaks the PHYs when
connected to switch chips or USB Ethernet MACs.
Each patch has the possibility to break boards, but contains a
recommendation to fix the problem in a more portable and future-proof
way.
regards,
Oleksij
Oleksij Rempel (7):
ARM i.MX6q: remove PHY fixup for KSZ9031
ARM i.MX6q: remove TX clock delay of ar8031_phy_fixup()
ARM i.MX6q: remove hand crafted PHY power up in ar8035_phy_fixup()
ARM i.MX6q: remove clk-out fixup for the Atheros AR8031 and AR8035
PHYs
ARM i.MX6q: remove Atheros AR8035 SmartEEE fixup
ARM: imx6sx: remove Atheros AR8031 PHY fixup
ARM: imx7d: remove Atheros AR8031 PHY fixup
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 2 +-
arch/arm/mach-imx/mach-imx6q.c | 85 -------------------------
arch/arm/mach-imx/mach-imx6sx.c | 26 --------
arch/arm/mach-imx/mach-imx7d.c | 22 -------
4 files changed, 1 insertion(+), 134 deletions(-)
--
2.30.0
This fixup removes the Lpi_en bit.
If this patch breaks functionality of your board, use following device
tree properties:
ethernet-phy@X {
reg = <0xX>;
eee-broken-1000t;
eee-broken-100tx;
....
};
Signed-off-by: Oleksij Rempel <[email protected]>
---
arch/arm/mach-imx/mach-imx6q.c | 21 ---------------------
1 file changed, 21 deletions(-)
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index d12b571a61ac..c9d7c29d95e1 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -68,32 +68,11 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);
-static int ar8035_phy_fixup(struct phy_device *dev)
-{
- u16 val;
-
- /* Ar803x phy SmartEEE feature cause link status generates glitch,
- * which cause ethernet link down/up issue, so disable SmartEEE
- */
- phy_write(dev, 0xd, 0x3);
- phy_write(dev, 0xe, 0x805d);
- phy_write(dev, 0xd, 0x4003);
-
- val = phy_read(dev, 0xe);
- phy_write(dev, 0xe, val & ~(1 << 8));
-
- return 0;
-}
-
-#define PHY_ID_AR8035 0x004dd072
-
static void __init imx6q_enet_phy_init(void)
{
if (IS_BUILTIN(CONFIG_PHYLIB)) {
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
ksz9021rn_phy_fixup);
- phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
- ar8035_phy_fixup);
}
}
--
2.30.0
Starting with:
bcf3440c6dd7 ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY")
the micrel phy driver started respecting phy-mode for the KSZ9031 PHY.
At least with kernel v5.8 configuration provided by this fixup was
overwritten by the micrel driver.
This fixup was providing following configuration:
RX path: 2.58ns delay
rx -0.42 (left shift) + rx_clk +0.96ns (right shift) =
1,38 + 1,2 internal RX delay = 2.58ns
TX path: 0.96ns delay
tx (no delay) + tx_clk 0.96ns (right shift) = 0.96ns
This configuration is outside of the recommended RGMII clock skew delays
and about in the middle of: rgmii-idrx and rgmii-id
Since most embedded systems do not have enough place to introduce
significant clock skew, rgmii-id is the way to go.
In case this patch breaks network functionality on your system, build
kernel with enabled MICREL_PHY. If it is still not working then try
following device tree options:
1. Set (or change) phy-mode in DT to:
phy-mode = "rgmii-id";
This actives internal delay for both RX and TX.
1. Set (or change) phy-mode in DT to:
phy-mode = "rgmii-idrx";
This actives internal delay for RX only.
3. Use following DT properties:
phy-mode = "rgmii";
txen-skew-psec = <0>;
rxdv-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
rxc-skew-psec = <1860>;
txc-skew-psec = <1860>;
This activates the internal delays for RX and TX, with the value as
the fixup that is removed in this patch.
Signed-off-by: Oleksij Rempel <[email protected]>
---
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 2 +-
arch/arm/mach-imx/mach-imx6q.c | 23 -----------------------
2 files changed, 1 insertion(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index fa2307d8ce86..c713ac03b3b9 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -112,7 +112,7 @@ flash: m25p80@0 {
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-supply = <&vgen2_1v2_eth>;
status = "okay";
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 703998ebb52e..78205f90da27 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -40,27 +40,6 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
return 0;
}
-static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
-{
- phy_write(dev, 0x0d, device);
- phy_write(dev, 0x0e, reg);
- phy_write(dev, 0x0d, (1 << 14) | device);
- phy_write(dev, 0x0e, val);
-}
-
-static int ksz9031rn_phy_fixup(struct phy_device *dev)
-{
- /*
- * min rx data delay, max rx/tx clock delay,
- * min rx/tx control delay
- */
- mmd_write_reg(dev, 2, 4, 0);
- mmd_write_reg(dev, 2, 5, 0);
- mmd_write_reg(dev, 2, 8, 0x003ff);
-
- return 0;
-}
-
/*
* fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
* as they are used for slots1-7 PERST#
@@ -152,8 +131,6 @@ static void __init imx6q_enet_phy_init(void)
if (IS_BUILTIN(CONFIG_PHYLIB)) {
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
ksz9021rn_phy_fixup);
- phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
- ksz9031rn_phy_fixup);
phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef,
ar8031_phy_fixup);
phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
--
2.30.0
On Wed, Feb 03, 2021 at 10:18:50AM +0100, Oleksij Rempel wrote:
> This patch series tries to remove most of the imx6 and imx7 board
> specific PHY configuration via fixup, as this breaks the PHYs when
> connected to switch chips or USB Ethernet MACs.
>
> Each patch has the possibility to break boards, but contains a
> recommendation to fix the problem in a more portable and future-proof
> way.
Please wait a cycle for the changes I've submitted through net-next
to be merged, so we don't end up with stuff breaking during the merge
window because these changes have been merged before the changes in
net-next.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
On Wed, Feb 03, 2021 at 10:18:55AM +0100, Oleksij Rempel wrote:
> This fixup removes the Lpi_en bit.
>
> If this patch breaks functionality of your board, use following device
> tree properties:
>
> ethernet-phy@X {
> reg = <0xX>;
> eee-broken-1000t;
> eee-broken-100tx;
> ....
> };
That is the historical fix for this problem, but there is a better
solution now in net-next - configuring the Tw parameter for gigabit
connections. That solves the random link drop issue when EEE is
enabled.
Support for this configuration has only recently been merged into
net-next and other trees for this merge window, so I ask that you
hold off at least this patch until the next cycle.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
On Wed, 2021-02-03 at 10:18 +0100, Oleksij Rempel wrote:
> Starting with:
>
> bcf3440c6dd7 ("net: phy: micrel: add phy-mode support for the
> KSZ9031 PHY")
>
> the micrel phy driver started respecting phy-mode for the KSZ9031 PHY.
> At least with kernel v5.8 configuration provided by this fixup was
> overwritten by the micrel driver.
>
> This fixup was providing following configuration:
>
> RX path: 2.58ns delay
> rx -0.42 (left shift) + rx_clk +0.96ns (right shift) =
> 1,38 + 1,2 internal RX delay = 2.58ns
> TX path: 0.96ns delay
> tx (no delay) + tx_clk 0.96ns (right shift) = 0.96ns
>
> This configuration is outside of the recommended RGMII clock skew
> delays
> and about in the middle of: rgmii-idrx and rgmii-id
>
> Since most embedded systems do not have enough place to introduce
> significant clock skew, rgmii-id is the way to go.
>
> In case this patch breaks network functionality on your system, build
> kernel with enabled MICREL_PHY. If it is still not working then try
> following device tree options:
> 1. Set (or change) phy-mode in DT to:
> phy-mode = "rgmii-id";
> This actives internal delay for both RX and TX.
> 1. Set (or change) phy-mode in DT to:
> phy-mode = "rgmii-idrx";
> This actives internal delay for RX only.
> 3. Use following DT properties:
> phy-mode = "rgmii";
> txen-skew-psec = <0>;
> rxdv-skew-psec = <0>;
> rxd0-skew-psec = <0>;
> rxd1-skew-psec = <0>;
> rxd2-skew-psec = <0>;
> rxd3-skew-psec = <0>;
> rxc-skew-psec = <1860>;
> txc-skew-psec = <1860>;
> This activates the internal delays for RX and TX, with the value as
> the fixup that is removed in this patch.
>
> Signed-off-by: Oleksij Rempel <[email protected]>
For Toradex Boards:
Acked-by: Philippe Schenker <[email protected]>
> ---
> arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 2 +-
> arch/arm/mach-imx/mach-imx6q.c | 23 -----------------------
> 2 files changed, 1 insertion(+), 24 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
> b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
> index fa2307d8ce86..c713ac03b3b9 100644
> --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
> +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
> @@ -112,7 +112,7 @@ flash: m25p80@0 {
> &fec {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_enet>;
> - phy-mode = "rgmii";
> + phy-mode = "rgmii-id";
> phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
> phy-supply = <&vgen2_1v2_eth>;
> status = "okay";
> diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-
> imx6q.c
> index 703998ebb52e..78205f90da27 100644
> --- a/arch/arm/mach-imx/mach-imx6q.c
> +++ b/arch/arm/mach-imx/mach-imx6q.c
> @@ -40,27 +40,6 @@ static int ksz9021rn_phy_fixup(struct phy_device
> *phydev)
> return 0;
> }
>
> -static void mmd_write_reg(struct phy_device *dev, int device, int
> reg, int val)
> -{
> - phy_write(dev, 0x0d, device);
> - phy_write(dev, 0x0e, reg);
> - phy_write(dev, 0x0d, (1 << 14) | device);
> - phy_write(dev, 0x0e, val);
> -}
> -
> -static int ksz9031rn_phy_fixup(struct phy_device *dev)
> -{
> - /*
> - * min rx data delay, max rx/tx clock delay,
> - * min rx/tx control delay
> - */
> - mmd_write_reg(dev, 2, 4, 0);
> - mmd_write_reg(dev, 2, 5, 0);
> - mmd_write_reg(dev, 2, 8, 0x003ff);
> -
> - return 0;
> -}
> -
> /*
> * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
> * as they are used for slots1-7 PERST#
> @@ -152,8 +131,6 @@ static void __init imx6q_enet_phy_init(void)
> if (IS_BUILTIN(CONFIG_PHYLIB)) {
> phy_register_fixup_for_uid(PHY_ID_KSZ9021,
> MICREL_PHY_ID_MASK,
> ksz9021rn_phy_fixup);
> - phy_register_fixup_for_uid(PHY_ID_KSZ9031,
> MICREL_PHY_ID_MASK,
> - ksz9031rn_phy_fixup);
> phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef,
> ar8031_phy_fixup);
> phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
On Wed, Feb 03, 2021 at 09:56:28AM +0000, Russell King - ARM Linux admin wrote:
> On Wed, Feb 03, 2021 at 10:18:55AM +0100, Oleksij Rempel wrote:
> > This fixup removes the Lpi_en bit.
> >
> > If this patch breaks functionality of your board, use following device
> > tree properties:
> >
> > ethernet-phy@X {
> > reg = <0xX>;
> > eee-broken-1000t;
> > eee-broken-100tx;
> > ....
> > };
>
> That is the historical fix for this problem, but there is a better
> solution now in net-next - configuring the Tw parameter for gigabit
> connections. That solves the random link drop issue when EEE is
> enabled.
Do you mean this properties?
qca,smarteee-tw-us-1g
qca,smarteee-tw-us-100m
Do you have some recommendations, which values can be here used? Are
they same for all MACs? Or, can we calculate this values automatically?
Beside, I have seen this patch: "ARM: dts: imx6qdl-sr-som: fix some
cubox-i platforms"
I had similar issue and it was triggered by the boot loader, which
enabled 60 Ohm on-die termination. The fix was to remove this lines in
the boot loader: wm 32 0x020e07ac 0x00000200 /* 60 Ohm ODT */
> Support for this configuration has only recently been merged into
> net-next and other trees for this merge window, so I ask that you
> hold off at least this patch until the next cycle.
ok.
Regards,
Oleksij
--
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31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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On Mon, Feb 08, 2021 at 10:20:38AM +0100, Oleksij Rempel wrote:
> On Wed, Feb 03, 2021 at 09:56:28AM +0000, Russell King - ARM Linux admin wrote:
> > That is the historical fix for this problem, but there is a better
> > solution now in net-next - configuring the Tw parameter for gigabit
> > connections. That solves the random link drop issue when EEE is
> > enabled.
>
> Do you mean this properties?
> qca,smarteee-tw-us-1g
> qca,smarteee-tw-us-100m
>
> Do you have some recommendations, which values can be here used? Are
> they same for all MACs? Or, can we calculate this values automatically?
I don't think there's a way to "calculate" them.
The AR8035 default is 17us for 1G and 23us for 100M. Increasing the
1G Tw to 26us or 27us fixes it on several different Solidrun platforms
(iMX6 Hummingboards and Cubox-i, and LX2160A based). The boards all
have differing layouts, so I don't think it's layout or SoC specific
(which is good news.)
These figures have been arrived at by repetitive long-term testing and
observing whether there are sporadic link drops over these platforms.
> Beside, I have seen this patch: "ARM: dts: imx6qdl-sr-som: fix some
> cubox-i platforms"
That's for a different problem: moving these settings to DT broke
some Cubox-i platforms because of the weird ways that the AR8035
configures the address bits, using the LED pin. Tying a LED to the
LED pin is not sufficient to guarantee that a board always configures
the PHY to a particular address, so it can appear on address 0 or 4
depending on noise, temperature, supply voltage, and PHY chip
thresholds.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!