From: Hou Zhiqiang <[email protected]>
This patch set is to add greater than 4GiB range support, patch 4/4.
Patch 3/4 is to initialize the number of viewport.
BTW, fix 2 bugs, see patch 1/4 and 2/4.
Hou Zhiqiang (4):
PCI/dwc: fix potential memory leak
PCI/dwc: Fix the 4GiB outbound window size truncated to zero issue
PCI/layerscape: initialize the number of viewport
PCI/dwc: Add more than 4GiB range support
drivers/pci/controller/dwc/pci-layerscape.c | 3 +
.../pci/controller/dwc/pcie-designware-host.c | 83 +++++++++++++++----
drivers/pci/controller/dwc/pcie-designware.c | 4 +-
drivers/pci/controller/dwc/pcie-designware.h | 7 +-
4 files changed, 79 insertions(+), 18 deletions(-)
--
2.17.1
From: Hou Zhiqiang <[email protected]>
Free the allocated pci_host_bridge struct when failed to get
host bridge resources, and free the resource windows before
free the bridge.
Signed-off-by: Hou Zhiqiang <[email protected]>
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 29a05759a294..ecacce016489 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -353,7 +353,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
&bridge->windows, &pp->io_base);
if (ret)
- return ret;
+ goto error;
ret = devm_request_pci_bus_resources(dev, &bridge->windows);
if (ret)
@@ -502,6 +502,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
return 0;
error:
+ pci_free_resource_list(&bridge->windows);
pci_free_host_bridge(bridge);
return ret;
}
--
2.17.1
From: Hou Zhiqiang <[email protected]>
FSL implements 6 viewports on Layerscape series SoCs.
Signed-off-by: Hou Zhiqiang <[email protected]>
---
drivers/pci/controller/dwc/pci-layerscape.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c
index 3724d3ef7008..69f3f1a5a782 100644
--- a/drivers/pci/controller/dwc/pci-layerscape.c
+++ b/drivers/pci/controller/dwc/pci-layerscape.c
@@ -280,6 +280,9 @@ static int __init ls_add_pcie_port(struct ls_pcie *pcie)
pp->ops = pcie->drvdata->ops;
+ /* FSL implements 6 windows */
+ pci->num_viewport = 6;
+
ret = dw_pcie_host_init(pp);
if (ret) {
dev_err(dev, "failed to initialize host\n");
--
2.17.1
From: Hou Zhiqiang <[email protected]>
The current type of mem_size is 'u32', so when resource_size()
return 4G it will be truncated to zero. This patch fix it by
changing its type to 'u64'.
Signed-off-by: Hou Zhiqiang <[email protected]>
---
drivers/pci/controller/dwc/pcie-designware.c | 4 ++--
drivers/pci/controller/dwc/pcie-designware.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 2153956a0b20..7ac5989c23ef 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -106,7 +106,7 @@ static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
int type, u64 cpu_addr,
- u64 pci_addr, u32 size)
+ u64 pci_addr, u64 size)
{
u32 retries, val;
@@ -141,7 +141,7 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
}
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
- u64 cpu_addr, u64 pci_addr, u32 size)
+ u64 cpu_addr, u64 pci_addr, u64 size)
{
u32 retries, val;
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 9f1a5e399b70..a438c3879aa9 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -153,7 +153,7 @@ struct pcie_port {
u32 io_size;
u64 mem_base;
phys_addr_t mem_bus_addr;
- u32 mem_size;
+ u64 mem_size;
struct resource *cfg;
struct resource *io;
struct resource *mem;
@@ -238,7 +238,7 @@ int dw_pcie_link_up(struct dw_pcie *pci);
int dw_pcie_wait_for_link(struct dw_pcie *pci);
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
int type, u64 cpu_addr, u64 pci_addr,
- u32 size);
+ u64 size);
int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
u64 cpu_addr, enum dw_pcie_as_type as_type);
void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
--
2.17.1
From: Hou Zhiqiang <[email protected]>
As each viewport support upto 4GiB, to support greater than 4GiB range
we need multiple viewport for MEM windows. And this patch explicitly
assigned the last (if there are only 2 viewports) or last 2 viewports
for CFG and IO windows and the rests for MEM windows.
Signed-off-by: Hou Zhiqiang <[email protected]>
---
.../pci/controller/dwc/pcie-designware-host.c | 80 ++++++++++++++++---
drivers/pci/controller/dwc/pcie-designware.h | 3 +
2 files changed, 70 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index ecacce016489..1b083873835e 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -346,6 +346,35 @@ int dw_pcie_host_init(struct pcie_port *pp)
dev_err(dev, "Missing *config* reg space\n");
}
+ /*
+ * If vendor's platform driver has set the num_viewport and it is
+ * not less than 2, skip getting the num_viewport from DT here.
+ */
+ if (pci->num_viewport < 2) {
+ ret = of_property_read_u32(np, "num-viewport",
+ &pci->num_viewport);
+ if (ret || pci->num_viewport < 2)
+ pci->num_viewport = 2;
+ }
+
+ /*
+ * if there are only 2 viewports, assign the last viewport for
+ * both CFG and IO window, otherwise assign the last 2 viewport
+ * for CFG and IO window specific. And the rest viewports are
+ * assigned to MEM windows.
+ */
+ if (pci->num_viewport == 2) {
+ pp->cfg_idx = pp->io_idx = PCIE_ATU_REGION_INDEX1;
+ pp->mem_wins = 1;
+ } else {
+ pp->cfg_idx = pci->num_viewport - 1;
+ pp->io_idx = pci->num_viewport - 2;
+ pp->mem_wins = pci->num_viewport - 2;
+ }
+
+ dev_dbg(dev, "CFG window index: %d, IO window index: %d, Total MEM window number: %d\n",
+ pp->cfg_idx, pp->io_idx, pp->mem_wins);
+
bridge = pci_alloc_host_bridge(0);
if (!bridge)
return -ENOMEM;
@@ -534,12 +563,12 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
va_cfg_base = pp->va_cfg1_base;
}
- dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
+ dw_pcie_prog_outbound_atu(pci, pp->cfg_idx,
type, cpu_addr,
busdev, cfg_size);
ret = dw_pcie_read(va_cfg_base + where, size, val);
- if (pci->num_viewport <= 2)
- dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
+ if (pp->cfg_idx == pp->io_idx)
+ dw_pcie_prog_outbound_atu(pci, pp->io_idx,
PCIE_ATU_TYPE_IO, pp->io_base,
pp->io_bus_addr, pp->io_size);
@@ -573,12 +602,12 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
va_cfg_base = pp->va_cfg1_base;
}
- dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
+ dw_pcie_prog_outbound_atu(pci, pp->cfg_idx,
type, cpu_addr,
busdev, cfg_size);
ret = dw_pcie_write(va_cfg_base + where, size, val);
- if (pci->num_viewport <= 2)
- dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
+ if (pp->cfg_idx == pp->io_idx)
+ dw_pcie_prog_outbound_atu(pci, pp->io_idx,
PCIE_ATU_TYPE_IO, pp->io_base,
pp->io_bus_addr, pp->io_size);
@@ -652,6 +681,9 @@ static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
void dw_pcie_setup_rc(struct pcie_port *pp)
{
u32 val, ctrl, num_ctrls;
+ u64 remain_size, base, win_size;
+ phys_addr_t bus_addr;
+ int i;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
dw_pcie_setup(pci);
@@ -700,13 +732,35 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dev_dbg(pci->dev, "iATU unroll: %s\n",
pci->iatu_unroll_enabled ? "enabled" : "disabled");
- dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_MEM, pp->mem_base,
- pp->mem_bus_addr, pp->mem_size);
- if (pci->num_viewport > 2)
- dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,
- PCIE_ATU_TYPE_IO, pp->io_base,
- pp->io_bus_addr, pp->io_size);
+ remain_size = pp->mem_size;
+ base = pp->mem_base;
+ bus_addr = pp->mem_bus_addr;
+
+ for (i = 0; remain_size > 0 && i < pp->mem_wins; i++) {
+ /*
+ * The maximum region size is 4 GB, and a region
+ * must not cross a 4 GB boundary.
+ */
+ win_size = SZ_4G - (base & (SZ_4G - 1));
+ win_size = min(win_size, remain_size);
+ dev_dbg(pci->dev, "iATU: MEM window %d: base = %llx, bus_addr = %llx, size = %llx\n",
+ i, base, bus_addr, win_size);
+
+ dw_pcie_prog_outbound_atu(pci, i,
+ PCIE_ATU_TYPE_MEM, base,
+ bus_addr, win_size);
+
+ base += win_size;
+ bus_addr += win_size;
+ remain_size -= win_size;
+ }
+
+ if (remain_size > 0)
+ dev_info(pci->dev, "iATU: MEM window isn't enough\n");
+
+ dw_pcie_prog_outbound_atu(pci, pp->io_idx,
+ PCIE_ATU_TYPE_IO, pp->io_base,
+ pp->io_bus_addr, pp->io_size);
}
dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index a438c3879aa9..20146b8729b3 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -148,12 +148,15 @@ struct pcie_port {
u64 cfg1_base;
void __iomem *va_cfg1_base;
u32 cfg1_size;
+ u32 cfg_idx;
resource_size_t io_base;
phys_addr_t io_bus_addr;
u32 io_size;
+ u32 io_idx;
u64 mem_base;
phys_addr_t mem_bus_addr;
u64 mem_size;
+ u32 mem_wins;
struct resource *cfg;
struct resource *io;
struct resource *mem;
--
2.17.1
Hi Hou,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on pci/next]
[also build test WARNING on v4.19 next-20181019]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Z-q-Hou/PCI-dwc-Add-more-than-4GiB-range-support/20181025-173802
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: i386-randconfig-s1-201842 (attached as .config)
compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new ones prefixed by >>):
In file included from include/linux/printk.h:336:0,
from include/linux/kernel.h:14,
from include/linux/list.h:9,
from include/linux/preempt.h:11,
from include/linux/spinlock.h:51,
from include/linux/irq.h:14,
from include/linux/irqchip/chained_irq.h:21,
from drivers/pci/controller/dwc/pcie-designware-host.c:11:
drivers/pci/controller/dwc/pcie-designware-host.c: In function 'dw_pcie_setup_rc':
>> drivers/pci/controller/dwc/pcie-designware-host.c:746:22: warning: format '%llx' expects argument of type 'long long unsigned int', but argument 6 has type 'phys_addr_t {aka unsigned int}' [-Wformat=]
dev_dbg(pci->dev, "iATU: MEM window %d: base = %llx, bus_addr = %llx, size = %llx\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
>> include/linux/device.h:1428:23: note: in expansion of macro 'dev_fmt'
dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
^~~~~~~
>> drivers/pci/controller/dwc/pcie-designware-host.c:746:4: note: in expansion of macro 'dev_dbg'
dev_dbg(pci->dev, "iATU: MEM window %d: base = %llx, bus_addr = %llx, size = %llx\n",
^~~~~~~
--
In file included from include/linux/printk.h:336:0,
from include/linux/kernel.h:14,
from include/linux/list.h:9,
from include/linux/preempt.h:11,
from include/linux/spinlock.h:51,
from include/linux/irq.h:14,
from include/linux/irqchip/chained_irq.h:21,
from drivers/pci//controller/dwc/pcie-designware-host.c:11:
drivers/pci//controller/dwc/pcie-designware-host.c: In function 'dw_pcie_setup_rc':
drivers/pci//controller/dwc/pcie-designware-host.c:746:22: warning: format '%llx' expects argument of type 'long long unsigned int', but argument 6 has type 'phys_addr_t {aka unsigned int}' [-Wformat=]
dev_dbg(pci->dev, "iATU: MEM window %d: base = %llx, bus_addr = %llx, size = %llx\n",
^
include/linux/dynamic_debug.h:135:39: note: in definition of macro 'dynamic_dev_dbg'
__dynamic_dev_dbg(&descriptor, dev, fmt, \
^~~
>> include/linux/device.h:1428:23: note: in expansion of macro 'dev_fmt'
dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
^~~~~~~
drivers/pci//controller/dwc/pcie-designware-host.c:746:4: note: in expansion of macro 'dev_dbg'
dev_dbg(pci->dev, "iATU: MEM window %d: base = %llx, bus_addr = %llx, size = %llx\n",
^~~~~~~
vim +746 drivers/pci/controller/dwc/pcie-designware-host.c
680
681 void dw_pcie_setup_rc(struct pcie_port *pp)
682 {
683 u32 val, ctrl, num_ctrls;
684 u64 remain_size, base, win_size;
685 phys_addr_t bus_addr;
686 int i;
687 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
688
689 dw_pcie_setup(pci);
690
691 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
692
693 /* Initialize IRQ Status array */
694 for (ctrl = 0; ctrl < num_ctrls; ctrl++)
695 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE +
696 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
697 4, &pp->irq_status[ctrl]);
698
699 /* Setup RC BARs */
700 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
701 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
702
703 /* Setup interrupt pins */
704 dw_pcie_dbi_ro_wr_en(pci);
705 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
706 val &= 0xffff00ff;
707 val |= 0x00000100;
708 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
709 dw_pcie_dbi_ro_wr_dis(pci);
710
711 /* Setup bus numbers */
712 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
713 val &= 0xff000000;
714 val |= 0x00ff0100;
715 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
716
717 /* Setup command register */
718 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
719 val &= 0xffff0000;
720 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
721 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
722 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
723
724 /*
725 * If the platform provides ->rd_other_conf, it means the platform
726 * uses its own address translation component rather than ATU, so
727 * we should not program the ATU here.
728 */
729 if (!pp->ops->rd_other_conf) {
730 /* Get iATU unroll support */
731 pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
732 dev_dbg(pci->dev, "iATU unroll: %s\n",
733 pci->iatu_unroll_enabled ? "enabled" : "disabled");
734
735 remain_size = pp->mem_size;
736 base = pp->mem_base;
737 bus_addr = pp->mem_bus_addr;
738
739 for (i = 0; remain_size > 0 && i < pp->mem_wins; i++) {
740 /*
741 * The maximum region size is 4 GB, and a region
742 * must not cross a 4 GB boundary.
743 */
744 win_size = SZ_4G - (base & (SZ_4G - 1));
745 win_size = min(win_size, remain_size);
> 746 dev_dbg(pci->dev, "iATU: MEM window %d: base = %llx, bus_addr = %llx, size = %llx\n",
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
On 25/10/2018 10:22, Z.q. Hou wrote:
> From: Hou Zhiqiang <[email protected]>
>
> Free the allocated pci_host_bridge struct when failed to get
> host bridge resources, and free the resource windows before
> free the bridge.
>
> Signed-off-by: Hou Zhiqiang <[email protected]>
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 29a05759a294..ecacce016489 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -353,7 +353,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
> ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
> &bridge->windows, &pp->io_base);
> if (ret)
> - return ret;
> + goto error;
>
> ret = devm_request_pci_bus_resources(dev, &bridge->windows);
> if (ret)
> @@ -502,6 +502,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
> return 0;
>
> error:
> + pci_free_resource_list(&bridge->windows);
> pci_free_host_bridge(bridge);
> return ret;
> }
>
Thanks for the memory leak fix. :)
Acked-by: Gustavo Pimentel <[email protected]>
On 25/10/2018 10:22, Z.q. Hou wrote:
> From: Hou Zhiqiang <[email protected]>
>
> The current type of mem_size is 'u32', so when resource_size()
> return 4G it will be truncated to zero. This patch fix it by
> changing its type to 'u64'.
>
> Signed-off-by: Hou Zhiqiang <[email protected]>
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 4 ++--
> drivers/pci/controller/dwc/pcie-designware.h | 4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 2153956a0b20..7ac5989c23ef 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -106,7 +106,7 @@ static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
>
> static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
> int type, u64 cpu_addr,
> - u64 pci_addr, u32 size)
> + u64 pci_addr, u64 size)
> {
> u32 retries, val;
>
> @@ -141,7 +141,7 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index,
> }
>
> void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> - u64 cpu_addr, u64 pci_addr, u32 size)
> + u64 cpu_addr, u64 pci_addr, u64 size)
> {
> u32 retries, val;
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 9f1a5e399b70..a438c3879aa9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -153,7 +153,7 @@ struct pcie_port {
> u32 io_size;
> u64 mem_base;
> phys_addr_t mem_bus_addr;
> - u32 mem_size;
> + u64 mem_size;
> struct resource *cfg;
> struct resource *io;
> struct resource *mem;
> @@ -238,7 +238,7 @@ int dw_pcie_link_up(struct dw_pcie *pci);
> int dw_pcie_wait_for_link(struct dw_pcie *pci);
> void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
> int type, u64 cpu_addr, u64 pci_addr,
> - u32 size);
> + u64 size);
> int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int bar,
> u64 cpu_addr, enum dw_pcie_as_type as_type);
> void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
>
Nice catch! :)
Acked-by: Gustavo Pimentel <[email protected]>