This series re-organizes the platsmp.c and adds SMP support for
MSM8660, MSM8960 and MSM8974.
We convert to using the cpus property in device tree and
add a "enable-method" property for arm32.
This helps select the appropriate release sequence for the
secondary cores based on the cpu.
Rohit Vaswani (4):
ARM: msm: Remove pen_release usage
ARM: msm: Re-organize platsmp to make it extensible
ARM: msm: Add SMP support for 8960
ARM: msm: Add support for 8974 SMP
Documentation/devicetree/bindings/arm/cpus.txt | 9 +
Documentation/devicetree/bindings/arm/msm/kpss.txt | 16 ++
Documentation/devicetree/bindings/arm/msm/scss.txt | 15 ++
arch/arm/boot/dts/msm8660-surf.dts | 23 +-
arch/arm/boot/dts/msm8960-cdp.dts | 22 ++
arch/arm/boot/dts/msm8974.dts | 23 ++
arch/arm/mach-msm/board-dt-8974.c | 3 +
arch/arm/mach-msm/headsmp.S | 41 ----
arch/arm/mach-msm/hotplug.c | 31 +--
arch/arm/mach-msm/platsmp.c | 265 ++++++++++++++++-----
arch/arm/mach-msm/scm-boot.h | 8 +-
11 files changed, 330 insertions(+), 126 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/msm/kpss.txt
create mode 100644 Documentation/devicetree/bindings/arm/msm/scss.txt
delete mode 100644 arch/arm/mach-msm/headsmp.S
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
pen_release is no longer required as the synchronization
is now managed by generic arm code.
This is done as suggested in https://lkml.org/lkml/2013/6/4/184
Signed-off-by: Rohit Vaswani <[email protected]>
---
arch/arm/mach-msm/headsmp.S | 41 -----------------------------------------
arch/arm/mach-msm/hotplug.c | 31 ++++---------------------------
arch/arm/mach-msm/platsmp.c | 35 +++--------------------------------
3 files changed, 7 insertions(+), 100 deletions(-)
delete mode 100644 arch/arm/mach-msm/headsmp.S
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S
deleted file mode 100644
index bcd5af2..0000000
--- a/arch/arm/mach-msm/headsmp.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * linux/arch/arm/mach-realview/headsmp.S
- *
- * Copyright (c) 2003 ARM Limited
- * All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
- __CPUINIT
-
-/*
- * MSM specific entry point for secondary CPUs. This provides
- * a "holding pen" into which all secondary cores are held until we're
- * ready for them to initialise.
- */
-ENTRY(msm_secondary_startup)
- mrc p15, 0, r0, c0, c0, 5
- and r0, r0, #15
- adr r4, 1f
- ldmia r4, {r5, r6}
- sub r4, r4, r5
- add r6, r6, r4
-pen: ldr r7, [r6]
- cmp r7, r0
- bne pen
-
- /*
- * we've been released from the holding pen: secondary_stack
- * should now contain the SVC stack for this core
- */
- b secondary_startup
-ENDPROC(msm_secondary_startup)
-
- .align
-1: .long .
- .long pen_release
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
index 326a872..cea80fc 100644
--- a/arch/arm/mach-msm/hotplug.c
+++ b/arch/arm/mach-msm/hotplug.c
@@ -24,33 +24,10 @@ static inline void cpu_leave_lowpower(void)
static inline void platform_do_lowpower(unsigned int cpu)
{
- /* Just enter wfi for now. TODO: Properly shut off the cpu. */
- for (;;) {
- /*
- * here's the WFI
- */
- asm("wfi"
- :
- :
- : "memory", "cc");
-
- if (pen_release == cpu_logical_map(cpu)) {
- /*
- * OK, proper wakeup, we're done
- */
- break;
- }
-
- /*
- * getting here, means that we have come out of WFI without
- * having been woken up - this shouldn't happen
- *
- * The trouble is, letting people know about this is not really
- * possible, since we are currently running incoherently, and
- * therefore cannot safely call printk() or anything else
- */
- pr_debug("CPU%u: spurious wakeup call\n", cpu);
- }
+ asm("wfi"
+ :
+ :
+ : "memory", "cc");
}
/*
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 00cdb0a..7d48759 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -28,7 +28,7 @@
#define SCSS_CPU1CORE_RESET 0xD80
#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
-extern void msm_secondary_startup(void);
+extern void secondary_startup(void);
static DEFINE_SPINLOCK(boot_lock);
@@ -41,13 +41,6 @@ static inline int get_core_count(void)
static void __cpuinit msm_secondary_init(unsigned int cpu)
{
/*
- * let the primary processor know we're out of the
- * pen, then head off into the C entry point
- */
- pen_release = -1;
- smp_wmb();
-
- /*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
@@ -57,7 +50,7 @@ static void __cpuinit msm_secondary_init(unsigned int cpu)
static __cpuinit void prepare_cold_cpu(unsigned int cpu)
{
int ret;
- ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
+ ret = scm_set_boot_addr(virt_to_phys(secondary_startup),
SCM_FLAG_COLDBOOT_CPU1);
if (ret == 0) {
void __iomem *sc1_base_ptr;
@@ -75,7 +68,6 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu)
static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
- unsigned long timeout;
static int cold_boot_done;
/* Only need to bring cpu out of reset this way once */
@@ -91,40 +83,19 @@ static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *id
spin_lock(&boot_lock);
/*
- * The secondary processor is waiting to be released from
- * the holding pen - release it, then wait for it to flag
- * that it has been released by resetting pen_release.
- *
- * Note that "pen_release" is the hardware CPU ID, whereas
- * "cpu" is Linux's internal ID.
- */
- pen_release = cpu_logical_map(cpu);
- __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
- outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
-
- /*
* Send the secondary CPU a soft interrupt, thereby causing
* the boot monitor to read the system wide flags register,
* and branch to the address found there.
*/
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
- timeout = jiffies + (1 * HZ);
- while (time_before(jiffies, timeout)) {
- smp_rmb();
- if (pen_release == -1)
- break;
-
- udelay(10);
- }
-
/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
spin_unlock(&boot_lock);
- return pen_release != -1 ? -ENOSYS : 0;
+ return 0;
}
/*
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
This makes it easy to add SMP support for new targets
by adding cpus property and the release sequence.
We add the enable-method property for the cpus property to
specify which release sequence to use.
While at it, add the 8660 cpus bindings to make SMP work.
Signed-off-by: Rohit Vaswani <[email protected]>
---
Documentation/devicetree/bindings/arm/cpus.txt | 6 ++
Documentation/devicetree/bindings/arm/msm/scss.txt | 15 ++++
arch/arm/boot/dts/msm8660-surf.dts | 23 +++++-
arch/arm/mach-msm/platsmp.c | 96 ++++++++++++++++------
4 files changed, 116 insertions(+), 24 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/msm/scss.txt
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index f32494d..327aad2 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -44,6 +44,12 @@ For the ARM architecture every CPU node must contain the following properties:
"marvell,mohawk"
"marvell,xsc3"
"marvell,xscale"
+ "qcom,scorpion"
+- enable-method: Specifies the method used to enable or take the secondary cores
+ out of reset. This allows different reset sequence for
+ different types of cpus.
+ This should be one of:
+ "qcom,scss"
Example:
diff --git a/Documentation/devicetree/bindings/arm/msm/scss.txt b/Documentation/devicetree/bindings/arm/msm/scss.txt
new file mode 100644
index 0000000..21c3e26
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/scss.txt
@@ -0,0 +1,15 @@
+* SCSS - Scorpion Sub-system
+
+Properties
+
+- compatible : Should contain "qcom,scss".
+
+- reg: Specifies the base address for the SCSS registers used for
+ booting up secondary cores.
+
+Example:
+
+ scss@902000 {
+ compatible = "qcom,scss";
+ reg = <0x00902000 0x2000>;
+ };
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index cdc010e..203e51a 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -7,6 +7,22 @@
compatible = "qcom,msm8660-surf", "qcom,msm8660";
interrupt-parent = <&intc>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,scorpion";
+ device_type = "cpu";
+ enable-method = "qcom,scss";
+
+ cpu@0 {
+ reg = <0>;
+ };
+
+ cpu@1 {
+ reg = <1>;
+ };
+ };
+
intc: interrupt-controller@2080000 {
compatible = "qcom,msm-8660-qgic";
interrupt-controller;
@@ -37,7 +53,12 @@
#interrupt-cells = <2>;
};
- serial@19c40000 {
+ scss@902000 {
+ compatible = "qcom,scss";
+ reg = <0x00902000 0x2000>;
+ };
+
+ serial@19c400000 {
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
reg = <0x19c40000 0x1000>,
<0x19c00000 0x1000>;
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 7d48759..17022e0 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -13,6 +13,8 @@
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/jiffies.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/smp.h>
#include <linux/io.h>
@@ -38,7 +40,7 @@ static inline int get_core_count(void)
return ((read_cpuid_id() >> 4) & 3) + 1;
}
-static void __cpuinit msm_secondary_init(unsigned int cpu)
+static void msm_secondary_init(unsigned int cpu)
{
/*
* Synchronise with the boot thread.
@@ -47,35 +49,63 @@ static void __cpuinit msm_secondary_init(unsigned int cpu)
spin_unlock(&boot_lock);
}
-static __cpuinit void prepare_cold_cpu(unsigned int cpu)
+static int scorpion_release_secondary(void)
{
- int ret;
- ret = scm_set_boot_addr(virt_to_phys(secondary_startup),
- SCM_FLAG_COLDBOOT_CPU1);
- if (ret == 0) {
- void __iomem *sc1_base_ptr;
- sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
- if (sc1_base_ptr) {
- writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
- writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
- writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
- iounmap(sc1_base_ptr);
- }
- } else
- printk(KERN_DEBUG "Failed to set secondary core boot "
- "address\n");
+ void __iomem *sc1_base_ptr;
+ struct device_node *dn = NULL;
+
+ dn = of_find_compatible_node(dn, NULL, "qcom,scss");
+ if (!dn) {
+ pr_err("%s: Missing scss node in device tree\n", __func__);
+ return -ENXIO;
+ }
+
+ sc1_base_ptr = of_iomap(dn, 0);
+ if (sc1_base_ptr) {
+ writel_relaxed(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
+ writel_relaxed(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
+ writel_relaxed(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
+ mb();
+ iounmap(sc1_base_ptr);
+ } else {
+ return -ENOMEM;
+ }
+
+ return 0;
}
-static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static DEFINE_PER_CPU(int, cold_boot_done);
+
+static void boot_cold_cpu(unsigned int cpu)
{
- static int cold_boot_done;
+ const char *enable_method;
+ struct device_node *dn = NULL;
- /* Only need to bring cpu out of reset this way once */
- if (cold_boot_done == false) {
- prepare_cold_cpu(cpu);
- cold_boot_done = true;
+ dn = of_find_node_by_name(dn, "cpus");
+ if (!dn) {
+ pr_err("%s: Missing node cpus in device tree\n", __func__);
+ return;
}
+ enable_method = of_get_property(dn, "enable-method", NULL);
+ if (!enable_method) {
+ pr_err("%s: cpus node is missing enable-method property\n",
+ __func__);
+ } else if (!strcmp(enable_method, "qcom,scss")) {
+ if (per_cpu(cold_boot_done, cpu) == false) {
+ scorpion_release_secondary();
+ per_cpu(cold_boot_done, cpu) = true;
+ }
+ } else {
+ pr_err("%s: Invalid enable-method property: %s\n",
+ __func__, enable_method);
+ }
+}
+
+static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ boot_cold_cpu(cpu);
+
/*
* set synchronisation state between this boot processor
* and the secondary one
@@ -118,8 +148,28 @@ static void __init msm_smp_init_cpus(void)
set_cpu_possible(i, true);
}
+static const int cold_boot_flags[] __initconst = {
+ 0,
+ SCM_FLAG_COLDBOOT_CPU1,
+};
+
static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
{
+ int cpu, map;
+ unsigned int flags = 0;
+
+ for_each_present_cpu(cpu) {
+ map = cpu_logical_map(cpu);
+ if (map > ARRAY_SIZE(cold_boot_flags)) {
+ set_cpu_present(cpu, false);
+ __WARN();
+ continue;
+ }
+ flags |= cold_boot_flags[map];
+ }
+
+ if (scm_set_boot_addr(virt_to_phys(secondary_startup), flags))
+ pr_warn("Failed to set CPU boot address\n");
}
struct smp_operations msm_smp_ops __initdata = {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
Add the cpus bindings and the Krait release sequence
to make SMP work for MSM8960
Signed-off-by: Rohit Vaswani <[email protected]>
---
Documentation/devicetree/bindings/arm/cpus.txt | 2 +
Documentation/devicetree/bindings/arm/msm/kpss.txt | 16 ++++++
arch/arm/boot/dts/msm8960-cdp.dts | 22 +++++++++
arch/arm/mach-msm/platsmp.c | 57 ++++++++++++++++++++++
arch/arm/mach-msm/scm-boot.h | 8 +--
5 files changed, 102 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/msm/kpss.txt
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 327aad2..1132eac 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -45,11 +45,13 @@ For the ARM architecture every CPU node must contain the following properties:
"marvell,xsc3"
"marvell,xscale"
"qcom,scorpion"
+ "qcom,krait"
- enable-method: Specifies the method used to enable or take the secondary cores
out of reset. This allows different reset sequence for
different types of cpus.
This should be one of:
"qcom,scss"
+ "qcom,kpssv1"
Example:
diff --git a/Documentation/devicetree/bindings/arm/msm/kpss.txt b/Documentation/devicetree/bindings/arm/msm/kpss.txt
new file mode 100644
index 0000000..7272340
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/kpss.txt
@@ -0,0 +1,16 @@
+* KPSS - Krait Processor Sub-system
+
+Properties
+
+- compatible : Should contain "qcom,kpss".
+
+- reg: Specifies the base address for the KPSS registers used for
+ booting up secondary cores.
+
+Example:
+
+ kpss@2088000 {
+ compatible = "qcom,kpss";
+ reg = <0x02088000 0x1000
+ 0x02098000 0x2000>;
+ };
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts
index db2060c..8c82d5e 100644
--- a/arch/arm/boot/dts/msm8960-cdp.dts
+++ b/arch/arm/boot/dts/msm8960-cdp.dts
@@ -7,6 +7,22 @@
compatible = "qcom,msm8960-cdp", "qcom,msm8960";
interrupt-parent = <&intc>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,krait";
+ device_type = "cpu";
+ enable-method = "qcom,kpssv1";
+
+ cpu@0 {
+ reg = <0>;
+ };
+
+ cpu@1 {
+ reg = <1>;
+ };
+ };
+
intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
@@ -37,6 +53,12 @@
reg = <0xfd510000 0x4000>;
};
+ kpss@2088000 {
+ compatible = "qcom,kpss";
+ reg = <0x02088000 0x1000
+ 0x02098000 0x2000>;
+ };
+
serial@16440000 {
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
reg = <0x16440000 0x1000>,
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 17022e0..82eb079 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -74,6 +74,56 @@ static int scorpion_release_secondary(void)
return 0;
}
+static int msm8960_release_secondary(unsigned int cpu)
+{
+ void __iomem *reg;
+ struct device_node *dn = NULL;
+
+ if (cpu == 0 || cpu >= num_possible_cpus())
+ return -EINVAL;
+
+ dn = of_find_compatible_node(dn, NULL, "qcom,kpss");
+ if (!dn) {
+ pr_err("%s : Missing kpss node from device tree\n", __func__);
+ return -ENXIO;
+ }
+
+ reg = of_iomap(dn, cpu);
+ if (!reg)
+ return -ENOMEM;
+
+ pr_debug("Starting secondary CPU %d\n", cpu);
+
+ /* Turn on CPU Rail */
+ writel_relaxed(0xA4, reg+0x1014);
+ mb();
+ udelay(512);
+
+ /* Krait bring-up sequence */
+ writel_relaxed(0x109, reg+0x04);
+ writel_relaxed(0x101, reg+0x04);
+ mb();
+ ndelay(300);
+
+ writel_relaxed(0x121, reg+0x04);
+ mb();
+ udelay(2);
+
+ writel_relaxed(0x120, reg+0x04);
+ mb();
+ udelay(2);
+
+ writel_relaxed(0x100, reg+0x04);
+ mb();
+ udelay(100);
+
+ writel_relaxed(0x180, reg+0x04);
+ mb();
+
+ iounmap(reg);
+ return 0;
+}
+
static DEFINE_PER_CPU(int, cold_boot_done);
static void boot_cold_cpu(unsigned int cpu)
@@ -96,6 +146,11 @@ static void boot_cold_cpu(unsigned int cpu)
scorpion_release_secondary();
per_cpu(cold_boot_done, cpu) = true;
}
+ } else if (!strcmp(enable_method, "qcom,kpssv1")) {
+ if (per_cpu(cold_boot_done, cpu) == false) {
+ msm8960_release_secondary(cpu);
+ per_cpu(cold_boot_done, cpu) = true;
+ }
} else {
pr_err("%s: Invalid enable-method property: %s\n",
__func__, enable_method);
@@ -151,6 +206,8 @@ static void __init msm_smp_init_cpus(void)
static const int cold_boot_flags[] __initconst = {
0,
SCM_FLAG_COLDBOOT_CPU1,
+ SCM_FLAG_COLDBOOT_CPU2,
+ SCM_FLAG_COLDBOOT_CPU3,
};
static void __init msm_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-msm/scm-boot.h
index 7be32ff..6aabb24 100644
--- a/arch/arm/mach-msm/scm-boot.h
+++ b/arch/arm/mach-msm/scm-boot.h
@@ -13,9 +13,11 @@
#define __MACH_SCM_BOOT_H
#define SCM_BOOT_ADDR 0x1
-#define SCM_FLAG_COLDBOOT_CPU1 0x1
-#define SCM_FLAG_WARMBOOT_CPU1 0x2
-#define SCM_FLAG_WARMBOOT_CPU0 0x4
+#define SCM_FLAG_COLDBOOT_CPU1 0x01
+#define SCM_FLAG_COLDBOOT_CPU2 0x08
+#define SCM_FLAG_COLDBOOT_CPU3 0x20
+#define SCM_FLAG_WARMBOOT_CPU0 0x04
+#define SCM_FLAG_WARMBOOT_CPU1 0x02
int scm_set_boot_addr(phys_addr_t addr, int flags);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
Add the cpus bindings and the Kraitv2 release sequence
to make SMP work for 2 cores on MSM8974.
Signed-off-by: Rohit Vaswani <[email protected]>
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
arch/arm/boot/dts/msm8974.dts | 23 ++++++++
arch/arm/mach-msm/board-dt-8974.c | 3 +
arch/arm/mach-msm/platsmp.c | 79 ++++++++++++++++++++++++++
4 files changed, 106 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 1132eac..7c3c677 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -52,6 +52,7 @@ For the ARM architecture every CPU node must contain the following properties:
This should be one of:
"qcom,scss"
"qcom,kpssv1"
+ "qcom,kpssv2"
Example:
diff --git a/arch/arm/boot/dts/msm8974.dts b/arch/arm/boot/dts/msm8974.dts
index c31c097..ef35a9b 100644
--- a/arch/arm/boot/dts/msm8974.dts
+++ b/arch/arm/boot/dts/msm8974.dts
@@ -7,6 +7,22 @@
compatible = "qcom,msm8974";
interrupt-parent = <&intc>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,krait";
+ device_type = "cpu";
+ enable-method = "qcom,kpssv2";
+
+ cpu@0 {
+ reg = <0>;
+ };
+
+ cpu@1 {
+ reg = <1>;
+ };
+ };
+
intc: interrupt-controller@f9000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
@@ -23,4 +39,11 @@
<1 1 0xf08>;
clock-frequency = <19200000>;
};
+
+ kpss@f9012000 {
+ compatible = "qcom,kpss";
+ reg = <0xf9012000 0x1000>,
+ <0xf9088000 0x1000>,
+ <0xf9098000 0x1000>;
+ };
};
diff --git a/arch/arm/mach-msm/board-dt-8974.c b/arch/arm/mach-msm/board-dt-8974.c
index d7f84f2..06119f9 100644
--- a/arch/arm/mach-msm/board-dt-8974.c
+++ b/arch/arm/mach-msm/board-dt-8974.c
@@ -13,11 +13,14 @@
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
+#include "common.h"
+
static const char * const msm8974_dt_match[] __initconst = {
"qcom,msm8974",
NULL
};
DT_MACHINE_START(MSM8974_DT, "Qualcomm MSM (Flattened Device Tree)")
+ .smp = smp_ops(msm_smp_ops),
.dt_compat = msm8974_dt_match,
MACHINE_END
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 82eb079..0fdae69 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -124,6 +124,80 @@ static int msm8960_release_secondary(unsigned int cpu)
return 0;
}
+static int msm8974_release_secondary(unsigned int cpu)
+{
+ void __iomem *reg;
+ void __iomem *l2_saw_base;
+ struct device_node *dn = NULL;
+ unsigned apc_pwr_gate_ctl = 0x14;
+ unsigned reg_val;
+
+ if (cpu == 0 || cpu >= num_possible_cpus())
+ return -EINVAL;
+
+ dn = of_find_compatible_node(dn, NULL, "qcom,kpss");
+ if (!dn) {
+ pr_err("%s : Missing kpss node from device tree\n", __func__);
+ return -ENXIO;
+ }
+
+ reg = of_iomap(dn, cpu+1);
+ if (!reg)
+ return -ENOMEM;
+
+ pr_debug("Starting secondary CPU %d\n", cpu);
+
+ /* Turn on the BHS, turn off LDO Bypass and power down LDO */
+ reg_val = 0x403f0001;
+ writel_relaxed(reg_val, reg + apc_pwr_gate_ctl);
+
+ /* complete the above write before the delay */
+ mb();
+ /* wait for the bhs to settle */
+ udelay(1);
+
+ /* Turn on BHS segments */
+ reg_val |= 0x3f << 1;
+ writel_relaxed(reg_val, reg + apc_pwr_gate_ctl);
+
+ /* complete the above write before the delay */
+ mb();
+ /* wait for the bhs to settle */
+ udelay(1);
+
+ /* Finally turn on the bypass so that BHS supplies power */
+ reg_val |= 0x3f << 8;
+ writel_relaxed(reg_val, reg + apc_pwr_gate_ctl);
+
+ /* enable max phases */
+ l2_saw_base = of_iomap(dn, 0);
+ if (!l2_saw_base) {
+ return -ENOMEM;
+ }
+ writel_relaxed(0x10003, l2_saw_base + 0x1c);
+ mb();
+ udelay(50);
+
+ iounmap(l2_saw_base);
+
+ writel_relaxed(0x021, reg+0x04);
+ mb();
+ udelay(2);
+
+ writel_relaxed(0x020, reg+0x04);
+ mb();
+ udelay(2);
+
+ writel_relaxed(0x000, reg+0x04);
+ mb();
+
+ writel_relaxed(0x080, reg+0x04);
+ mb();
+
+ iounmap(reg);
+ return 0;
+}
+
static DEFINE_PER_CPU(int, cold_boot_done);
static void boot_cold_cpu(unsigned int cpu)
@@ -151,6 +225,11 @@ static void boot_cold_cpu(unsigned int cpu)
msm8960_release_secondary(cpu);
per_cpu(cold_boot_done, cpu) = true;
}
+ } else if (!strcmp(enable_method, "qcom,kpssv2")) {
+ if (per_cpu(cold_boot_done, cpu) == false) {
+ msm8974_release_secondary(cpu);
+ per_cpu(cold_boot_done, cpu) = true;
+ }
} else {
pr_err("%s: Invalid enable-method property: %s\n",
__func__, enable_method);
--
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hosted by The Linux Foundation
ping ?
On 6/28/2013 4:25 PM, Rohit Vaswani wrote:
> This series re-organizes the platsmp.c and adds SMP support for
> MSM8660, MSM8960 and MSM8974.
> We convert to using the cpus property in device tree and
> add a "enable-method" property for arm32.
> This helps select the appropriate release sequence for the
> secondary cores based on the cpu.
>
> Rohit Vaswani (4):
> ARM: msm: Remove pen_release usage
> ARM: msm: Re-organize platsmp to make it extensible
> ARM: msm: Add SMP support for 8960
> ARM: msm: Add support for 8974 SMP
>
> Documentation/devicetree/bindings/arm/cpus.txt | 9 +
> Documentation/devicetree/bindings/arm/msm/kpss.txt | 16 ++
> Documentation/devicetree/bindings/arm/msm/scss.txt | 15 ++
> arch/arm/boot/dts/msm8660-surf.dts | 23 +-
> arch/arm/boot/dts/msm8960-cdp.dts | 22 ++
> arch/arm/boot/dts/msm8974.dts | 23 ++
> arch/arm/mach-msm/board-dt-8974.c | 3 +
> arch/arm/mach-msm/headsmp.S | 41 ----
> arch/arm/mach-msm/hotplug.c | 31 +--
> arch/arm/mach-msm/platsmp.c | 265 ++++++++++++++++-----
> arch/arm/mach-msm/scm-boot.h | 8 +-
> 11 files changed, 330 insertions(+), 126 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/msm/kpss.txt
> create mode 100644 Documentation/devicetree/bindings/arm/msm/scss.txt
> delete mode 100644 arch/arm/mach-msm/headsmp.S
>
Thanks,
Rohit Vaswani
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
On Jun 28, 2013, at 6:25 PM, Rohit Vaswani wrote:
> pen_release is no longer required as the synchronization
> is now managed by generic arm code.
> This is done as suggested in https://lkml.org/lkml/2013/6/4/184
>
> Signed-off-by: Rohit Vaswani <[email protected]>
> ---
> arch/arm/mach-msm/headsmp.S | 41 -----------------------------------------
> arch/arm/mach-msm/hotplug.c | 31 ++++---------------------------
> arch/arm/mach-msm/platsmp.c | 35 +++--------------------------------
> 3 files changed, 7 insertions(+), 100 deletions(-)
> delete mode 100644 arch/arm/mach-msm/headsmp.S
Don't you need to update arch/arm/mach-msm/Makefile to remove headsmp.o from:
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
- k
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
On 7/26/2013 10:48 AM, Kumar Gala wrote:
> On Jun 28, 2013, at 6:25 PM, Rohit Vaswani wrote:
>
>> pen_release is no longer required as the synchronization
>> is now managed by generic arm code.
>> This is done as suggested in https://lkml.org/lkml/2013/6/4/184
>>
>> Signed-off-by: Rohit Vaswani <[email protected]>
>> ---
>> arch/arm/mach-msm/headsmp.S | 41 -----------------------------------------
>> arch/arm/mach-msm/hotplug.c | 31 ++++---------------------------
>> arch/arm/mach-msm/platsmp.c | 35 +++--------------------------------
>> 3 files changed, 7 insertions(+), 100 deletions(-)
>> delete mode 100644 arch/arm/mach-msm/headsmp.S
> Don't you need to update arch/arm/mach-msm/Makefile to remove headsmp.o from:
>
> obj-$(CONFIG_SMP) += headsmp.o platsmp.o
Will do
> - k
>
> --
> Employee of Qualcomm Innovation Center, Inc.
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to [email protected]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
Thanks,
Rohit Vaswani
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation