Hello,
This series adds support for CPSW3G MAC port 2 with the SK-Ethernet-DC01
Add-On daughtercard. Also, the missing alias for CPSW3G MAC Port 1 is
added to the am62a7-sk board file in order to allow kernel to fetch MAC
address populated by U-Boot for CPSW3G MAC Port 1.
This series is based on linux-next tagged next-20240424.
Link to v1:
https://lore.kernel.org/r/[email protected]/
Changes from v1 to v2:
- Since support for device tree overlays for am62a7-sk is already enabled
by commit "635ed9715194", it is removed from this series.
Siddharth Vadapalli (2):
arm64: dts: ti: k3-am62a7-sk: Add alias for CPSW3G MAC port 1
arm64: dts: ti: k3-am62a7: Add overlay for second CPSW3G Port
arch/arm64/boot/dts/ti/Makefile | 3 +
.../dts/ti/k3-am62a7-sk-ethernet-dc01.dtso | 61 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 1 +
3 files changed, 65 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso
--
2.34.1
From: Siddharth Vadapalli <[email protected]>
The SK-Ethernet-DC01 Add-On Ethernet Card for AM62A7-SK board supports
RGMII mode.
Add overlay to enable the second CPSW3G port in RGMII-RXID mode with the
Add-On Ethernet Card.
Signed-off-by: Siddharth Vadapalli <[email protected]>
Signed-off-by: Chintan Vankar <[email protected]>
---
Link to v1:
https://lore.kernel.org/r/[email protected]/
Changes from v1 to v2:
- Since support for device tree overlays for am62a7-sk is already enabled
by commit "635ed9715194", it is removed from this series.
arch/arm64/boot/dts/ti/Makefile | 3 +
.../dts/ti/k3-am62a7-sk-ethernet-dc01.dtso | 61 +++++++++++++++++++
2 files changed, 64 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index c76b41f86527..8c55e46d9f98 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -27,6 +27,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
# Boards with AM62Ax SoC
dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-ethernet-dc01.dtbo
# Boards with AM62Px SoC
dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
@@ -123,6 +124,8 @@ k3-am62a7-sk-csi2-ov5640-dtbs := k3-am62a7-sk.dtb \
k3-am62x-sk-csi2-ov5640.dtbo
k3-am62a7-sk-csi2-tevi-ov5640-dtbs := k3-am62a7-sk.dtb \
k3-am62x-sk-csi2-tevi-ov5640.dtbo
+k3-am62a7-sk-ethernet-dc01-dtbs := k3-am62a7-sk.dtb \
+ k3-am62a7-sk-ethernet-dc01.dtbo
k3-am62a7-sk-hdmi-audio-dtbs := k3-am62a7-sk.dtb k3-am62x-sk-hdmi-audio.dtbo
k3-am62p5-sk-csi2-imx219-dtbs := k3-am62p5-sk.dtb \
k3-am62x-sk-csi2-imx219.dtbo
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso b/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso
new file mode 100644
index 000000000000..f6d5a089a717
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for second CPSW3G port in RGMII mode using SK-ETHERNET-DC01
+ * Add-On Daughtercard with AM62A7-SK.
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-pinctrl.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@2";
+ };
+};
+
+&cpsw3g {
+ pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
+};
+
+&cpsw_port2 {
+ status = "okay";
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy1>;
+};
+
+&cpsw3g_mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw3g_phy1: ethernet-phy@1 {
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&main_pmx0 {
+ main_rgmii2_pins_default: main-rgmii2-default-pins {
+ pinctrl-single,pins = <
+ AM62AX_IOPAD(0x0184, PIN_INPUT, 0) /* (AA21) RGMII2_RD0 */
+ AM62AX_IOPAD(0x0188, PIN_INPUT, 0) /* (Y20) RGMII2_RD1 */
+ AM62AX_IOPAD(0x018c, PIN_INPUT, 0) /* (AB21) RGMII2_RD2 */
+ AM62AX_IOPAD(0x0190, PIN_INPUT, 0) /* (AB20) RGMII2_RD3 */
+ AM62AX_IOPAD(0x0180, PIN_INPUT, 0) /* (AA20) RGMII2_RXC */
+ AM62AX_IOPAD(0x017c, PIN_INPUT, 0) /* (W18) RGMII2_RX_CTL */
+ AM62AX_IOPAD(0x016c, PIN_INPUT, 0) /* (AA19) RGMII2_TD0 */
+ AM62AX_IOPAD(0x0170, PIN_INPUT, 0) /* (Y18) RGMII2_TD1 */
+ AM62AX_IOPAD(0x0174, PIN_INPUT, 0) /* (AA18) RGMII2_TD2 */
+ AM62AX_IOPAD(0x0178, PIN_INPUT, 0) /* (W17) RGMII2_TD3 */
+ AM62AX_IOPAD(0x0168, PIN_INPUT, 0) /* (AB19) RGMII2_TXC */
+ AM62AX_IOPAD(0x0164, PIN_INPUT, 0) /* (Y19) RGMII2_TX_CTL */
+ >;
+ };
+};
--
2.34.1
From: Siddharth Vadapalli <[email protected]>
Add alias for CPSW3G MAC port 1 to enable kernel to fetch MAC Address
directly from U-Boot.
Signed-off-by: Siddharth Vadapalli <[email protected]>
Signed-off-by: Chintan Vankar <[email protected]>
---
Link to v1:
https://lore.kernel.org/r/[email protected]/
Changes from v1 to v2:
- No changes.
arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
index f241637a5642..7ac3049302ae 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
@@ -22,6 +22,7 @@ aliases {
serial3 = &main_uart1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
+ ethernet0 = &cpsw_port1;
};
chosen {
--
2.34.1
On 4/25/24 3:50 PM, Chintan Vankar wrote:
> From: Siddharth Vadapalli <[email protected]>
>
> Add alias for CPSW3G MAC port 1 to enable kernel to fetch MAC Address
> directly from U-Boot.
>
> Signed-off-by: Siddharth Vadapalli <[email protected]>
> Signed-off-by: Chintan Vankar <[email protected]>
> ---
>
> Link to v1:
> https://lore.kernel.org/r/[email protected]/
>
> Changes from v1 to v2:
> - No changes.
>
> arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
> index f241637a5642..7ac3049302ae 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
> @@ -22,6 +22,7 @@ aliases {
> serial3 = &main_uart1;
> mmc0 = &sdhci0;
> mmc1 = &sdhci1;
> + ethernet0 = &cpsw_port1;
> };
>
> chosen {
Reviewed-by: Ravi Gunasekaran <[email protected]>
--
Regards,
Ravi
On 4/25/24 3:50 PM, Chintan Vankar wrote:
> From: Siddharth Vadapalli <[email protected]>
>
> The SK-Ethernet-DC01 Add-On Ethernet Card for AM62A7-SK board supports
> RGMII mode.
>
> Add overlay to enable the second CPSW3G port in RGMII-RXID mode with the
> Add-On Ethernet Card.
>
> Signed-off-by: Siddharth Vadapalli <[email protected]>
> Signed-off-by: Chintan Vankar <[email protected]>
> ---
>
> Link to v1:
> https://lore.kernel.org/r/[email protected]/
>
> Changes from v1 to v2:
> - Since support for device tree overlays for am62a7-sk is already enabled
> by commit "635ed9715194", it is removed from this series.
>
> arch/arm64/boot/dts/ti/Makefile | 3 +
> .../dts/ti/k3-am62a7-sk-ethernet-dc01.dtso | 61 +++++++++++++++++++
> 2 files changed, 64 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index c76b41f86527..8c55e46d9f98 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -27,6 +27,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
>
> # Boards with AM62Ax SoC
> dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-ethernet-dc01.dtbo
>
> # Boards with AM62Px SoC
> dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
> @@ -123,6 +124,8 @@ k3-am62a7-sk-csi2-ov5640-dtbs := k3-am62a7-sk.dtb \
> k3-am62x-sk-csi2-ov5640.dtbo
> k3-am62a7-sk-csi2-tevi-ov5640-dtbs := k3-am62a7-sk.dtb \
> k3-am62x-sk-csi2-tevi-ov5640.dtbo
> +k3-am62a7-sk-ethernet-dc01-dtbs := k3-am62a7-sk.dtb \
> + k3-am62a7-sk-ethernet-dc01.dtbo
> k3-am62a7-sk-hdmi-audio-dtbs := k3-am62a7-sk.dtb k3-am62x-sk-hdmi-audio.dtbo
> k3-am62p5-sk-csi2-imx219-dtbs := k3-am62p5-sk.dtb \
> k3-am62x-sk-csi2-imx219.dtbo
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso b/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso
> new file mode 100644
> index 000000000000..f6d5a089a717
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso
> @@ -0,0 +1,61 @@
> +// SPDX-License-Identifier: GPL-2.0
Please update the license to "GPL-2.0-only OR MIT"
> +/**
> + * DT Overlay for second CPSW3G port in RGMII mode using SK-ETHERNET-DC01
> + * Add-On Daughtercard with AM62A7-SK.
> + *
> + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/net/ti-dp83867.h>
> +#include "k3-pinctrl.h"
> +
> +&{/} {
> + aliases {
> + ethernet1 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@2";
> + };
> +};
> +
> +&cpsw3g {
> + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
One entry per line like below
pinctrl-0 = <&main_rgmii1_pins_default>,
<&main_rgmii2_pins_default>;
> +};
> +
> +&cpsw_port2 {
> + status = "okay";
> + phy-mode = "rgmii-rxid";
> + phy-handle = <&cpsw3g_phy1>;
> +};
> +
> +&cpsw3g_mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpsw3g_phy1: ethernet-phy@1 {
> + reg = <1>;
> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + ti,min-output-impedance;
> + };
> +};
> +
> +&main_pmx0 {
> + main_rgmii2_pins_default: main-rgmii2-default-pins {
> + pinctrl-single,pins = <
> + AM62AX_IOPAD(0x0184, PIN_INPUT, 0) /* (AA21) RGMII2_RD0 */
> + AM62AX_IOPAD(0x0188, PIN_INPUT, 0) /* (Y20) RGMII2_RD1 */
> + AM62AX_IOPAD(0x018c, PIN_INPUT, 0) /* (AB21) RGMII2_RD2 */
> + AM62AX_IOPAD(0x0190, PIN_INPUT, 0) /* (AB20) RGMII2_RD3 */
> + AM62AX_IOPAD(0x0180, PIN_INPUT, 0) /* (AA20) RGMII2_RXC */
> + AM62AX_IOPAD(0x017c, PIN_INPUT, 0) /* (W18) RGMII2_RX_CTL */
> + AM62AX_IOPAD(0x016c, PIN_INPUT, 0) /* (AA19) RGMII2_TD0 */
> + AM62AX_IOPAD(0x0170, PIN_INPUT, 0) /* (Y18) RGMII2_TD1 */
> + AM62AX_IOPAD(0x0174, PIN_INPUT, 0) /* (AA18) RGMII2_TD2 */
> + AM62AX_IOPAD(0x0178, PIN_INPUT, 0) /* (W17) RGMII2_TD3 */
> + AM62AX_IOPAD(0x0168, PIN_INPUT, 0) /* (AB19) RGMII2_TXC */
> + AM62AX_IOPAD(0x0164, PIN_INPUT, 0) /* (Y19) RGMII2_TX_CTL */
> + >;
> + };
> +};
--
Regards,
Ravi
On 29/04/24 10:54, Ravi Gunasekaran wrote:
>
>
> On 4/25/24 3:50 PM, Chintan Vankar wrote:
>> From: Siddharth Vadapalli <[email protected]>
>>
>> The SK-Ethernet-DC01 Add-On Ethernet Card for AM62A7-SK board supports
>> RGMII mode.
>>
>> Add overlay to enable the second CPSW3G port in RGMII-RXID mode with the
>> Add-On Ethernet Card.
>>
>> Signed-off-by: Siddharth Vadapalli <[email protected]>
>> Signed-off-by: Chintan Vankar <[email protected]>
>> ---
>>
>> Link to v1:
>> https://lore.kernel.org/r/[email protected]/
>>
>> Changes from v1 to v2:
>> - Since support for device tree overlays for am62a7-sk is already enabled
>> by commit "635ed9715194", it is removed from this series.
>>
>> arch/arm64/boot/dts/ti/Makefile | 3 +
>> .../dts/ti/k3-am62a7-sk-ethernet-dc01.dtso | 61 +++++++++++++++++++
>> 2 files changed, 64 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso
>>
>> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
>> index c76b41f86527..8c55e46d9f98 100644
>> --- a/arch/arm64/boot/dts/ti/Makefile
>> +++ b/arch/arm64/boot/dts/ti/Makefile
>> @@ -27,6 +27,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
>>
>> # Boards with AM62Ax SoC
>> dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
>> +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-ethernet-dc01.dtbo
>>
>> # Boards with AM62Px SoC
>> dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
>> @@ -123,6 +124,8 @@ k3-am62a7-sk-csi2-ov5640-dtbs := k3-am62a7-sk.dtb \
>> k3-am62x-sk-csi2-ov5640.dtbo
>> k3-am62a7-sk-csi2-tevi-ov5640-dtbs := k3-am62a7-sk.dtb \
>> k3-am62x-sk-csi2-tevi-ov5640.dtbo
>> +k3-am62a7-sk-ethernet-dc01-dtbs := k3-am62a7-sk.dtb \
>> + k3-am62a7-sk-ethernet-dc01.dtbo
>> k3-am62a7-sk-hdmi-audio-dtbs := k3-am62a7-sk.dtb k3-am62x-sk-hdmi-audio.dtbo
>> k3-am62p5-sk-csi2-imx219-dtbs := k3-am62p5-sk.dtb \
>> k3-am62x-sk-csi2-imx219.dtbo
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso b/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso
>> new file mode 100644
>> index 000000000000..f6d5a089a717
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk-ethernet-dc01.dtso
>> @@ -0,0 +1,61 @@
>> +// SPDX-License-Identifier: GPL-2.0
>
> Please update the license to "GPL-2.0-only OR MIT"
>
I will update it in next version.
>> +/**
>> + * DT Overlay for second CPSW3G port in RGMII mode using SK-ETHERNET-DC01
>> + * Add-On Daughtercard with AM62A7-SK.
>> + *
>> + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
>> + */
>> +
>> +/dts-v1/;
>> +/plugin/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/net/ti-dp83867.h>
>> +#include "k3-pinctrl.h"
>> +
>> +&{/} {
>> + aliases {
>> + ethernet1 = "/bus@f0000/ethernet@8000000/ethernet-ports/port@2";
>> + };
>> +};
>> +
>> +&cpsw3g {
>> + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>;
>
>
> One entry per line like below
>
> pinctrl-0 = <&main_rgmii1_pins_default>,
> <&main_rgmii2_pins_default>;
>
Thanks Ravi for pointing out this, I will update this in next
version.
>> +};
>> +
>> +&cpsw_port2 {
>> + status = "okay";
>> + phy-mode = "rgmii-rxid";
>> + phy-handle = <&cpsw3g_phy1>;
>> +};
>> +
>> +&cpsw3g_mdio {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpsw3g_phy1: ethernet-phy@1 {
>> + reg = <1>;
>> + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> + ti,min-output-impedance;
>> + };
>> +};
>> +
>> +&main_pmx0 {
>> + main_rgmii2_pins_default: main-rgmii2-default-pins {
>> + pinctrl-single,pins = <
>> + AM62AX_IOPAD(0x0184, PIN_INPUT, 0) /* (AA21) RGMII2_RD0 */
>> + AM62AX_IOPAD(0x0188, PIN_INPUT, 0) /* (Y20) RGMII2_RD1 */
>> + AM62AX_IOPAD(0x018c, PIN_INPUT, 0) /* (AB21) RGMII2_RD2 */
>> + AM62AX_IOPAD(0x0190, PIN_INPUT, 0) /* (AB20) RGMII2_RD3 */
>> + AM62AX_IOPAD(0x0180, PIN_INPUT, 0) /* (AA20) RGMII2_RXC */
>> + AM62AX_IOPAD(0x017c, PIN_INPUT, 0) /* (W18) RGMII2_RX_CTL */
>> + AM62AX_IOPAD(0x016c, PIN_INPUT, 0) /* (AA19) RGMII2_TD0 */
>> + AM62AX_IOPAD(0x0170, PIN_INPUT, 0) /* (Y18) RGMII2_TD1 */
>> + AM62AX_IOPAD(0x0174, PIN_INPUT, 0) /* (AA18) RGMII2_TD2 */
>> + AM62AX_IOPAD(0x0178, PIN_INPUT, 0) /* (W17) RGMII2_TD3 */
>> + AM62AX_IOPAD(0x0168, PIN_INPUT, 0) /* (AB19) RGMII2_TXC */
>> + AM62AX_IOPAD(0x0164, PIN_INPUT, 0) /* (Y19) RGMII2_TX_CTL */
>> + >;
>> + };
>> +};
>