V9:
- Fixes name of tsens
s4 is not present
s4->s5
s5->s6
s6->s7
s7->s8
s8->s9
I erroneously thought the last sensor needed to be brought in but,
as has been pointed out to me, the last sensor isn't used, so
no need to support the reading and reassembly of the non-contiguous
calibration data - Stephan/Dmitry
- pronto/s//wcnss - Stephan
- tulip dr_mode = "otg" not dr_mode = "device"
I set the value to device for debug purposes but the role-switch
works just fine and should be upstream - Stephan
- fixed alphabetisation in pm8939-8916.dtsi - bod
Bootable: https://git.codelinaro.org/bryan.odonoghue/kernel/-/commits/linux-next-23-04-07-msm8939-nocpr
Previous: https://lore.kernel.org/linux-arm-msm/[email protected]/
git diff linux-next-23-03-27-msm8939-nocpr -- arch/arm64/boot/dts/qcom/*39*
V8:
- Addresses all of Stephan's comments from v7
- Moves M4 Aqua display to a separate series
- Retains s4_p1/p2 done on purpose I believe
- Adds Konrad's RB as indicated
Bootable: https://git.codelinaro.org/bryan.odonoghue/kernel/-/commits/linux-next-23-03-27-msm8939-nocpr
Previous: https://lore.kernel.org/lkml/[email protected]/
V7:
- Addresses all of Konrad's asks on V6
- Adds Konrad's RB for patch #3
Bootable: https://git.codelinaro.org/bryan.odonoghue/kernel/-/commits/linux-next-23-02-23-msm8939-nocpr
Previous: https://lore.kernel.org/lkml/[email protected]/T/
V6:
- Adds Krzysztof's Ack for Square vendor addition - Krzysztof
- Incorporates all of Stephan's comments from V5, including
dropping CPR dummy given the dependent patch [1] has been merged, now.
Bootable: https://git.codelinaro.org/bryan.odonoghue/kernel/-/commits/linux-next-23-02-21-msm8939-nocpr
Previous: https://lore.kernel.org/lkml/[email protected]/T/
[1]: https://lore.kernel.org/linux-arm-msm/[email protected]/
V5:
- Adds Square as a vendor - Krzysztof
- typec_pd: usb-pd@38 - Krzysztof
- Drops gcc clock controller extension. It looks like phy0 actually
provides a PLL to phy1 for its byte clock. - Bryan, Krzysztof, Stephan
- Adds RB Konrad as indicated - Konrad
- wcnss VDDMX_AO -> VDDMX - Bjorn
- Adds dsi_phy0 as clock-parent to dsi1
- mdss interconnect drops Androidism "register-mem" - Stephan
- cpu power-domain. I've retained the "dummy" cpr reference to
satiate dtbs_check [1] but renamed &vreg_cpr_stub to remove any confusion
between now and when we finish off CPR on 8939.
Bootable: https://git.codelinaro.org/bryan.odonoghue/kernel/-/commits/linux-next-23-02-02-msm8939-nocpr
Previous: https://lore.kernel.org/linux-arm-msm/[email protected]/
[1] https://lore.kernel.org/linux-arm-msm/[email protected]/
V4:
- Adds Krzysztof's RB to snoc-mm
- Re-orders alphabetically missed nodes in previous iteration - Bjorn
- Adds LK address/size cells comment - Bjorn
- Left _AO for wcnss as downstream reference uses this - Bjorn/Bryan
- Uses qcom,ids.h and QCOM_ID_SOCNAME for qcom,msm-id - Bjorn
- Revises comment from "Regulator" to "Power supply" - Bjorn
- Leaves dummy power-domain reference in cpu defintion as this
- Relabels "cpu" to "CPU" to be more consistent with other dtsi - Bryan
- Moves msm8939 gcc to its own yaml file to capture 8939 specific form - Bryan
is a required property and the dt checker complains - Stephan/Bryan
- Removes CPR entries from qfprom - Stephan
- Left MDSS interconnects. I don't see a bug to fix here - Stephan/Bryan
- power-domain in MDSS - dropped its not longer required after
commit a6f033938beb ("dt-bindings: msm: dsi-controller-main: Fix power-domain constraint") - Stephan
- Adds gcc dsi1pll and dsi1pllbyte to gcc clock list.
Reviewing the silicon documentation we see dsi0_phy_pll is used to clock
GCC_BYTE1_CFG_RCGR : SRC_SEL
Root Source Select
000 : cxo
001 : dsi0_phy_pll_out_byteclk
010 : GPLL0_OUT_AUX
011 : gnd
100 : gnd
101 : gnd
110 : gnd
111 : reserved - Stephan/Bryan
- pm8916_l16 -> pm8916_l6 in dsi definition, typo - Konrad
- Moved regulator_set_load location - Konrad
Previous: https://lore.kernel.org/lkml/[email protected]/T/
Bootable: https://git.linaro.org/people/bryan.odonoghue/kernel.git/log/?h=linux-next-23-01-23-msm8939-nocpr
V3:
- Happily I don't currently depend on any other series to be merged.
Bjorn and Chanwoo picked up everything I need to unblock this series. ＼(^o^)／
- Moves xo_board to RPM/PMIC clock gated CXO, not including rpmcc: obvs - Konrad/Bjorn
- qcom,msm-id = <239 0> - left as in V2 valid according to Sony references - bod
- cpu-release-addr - as stated below we rely on lk2nd to take the second cluster
out of reset - bod
- smem child node update - Konrad
- Whitespace updates - Konrad
- gpu no interconnect - Konrad - No bod
- 19.2 MHz dropped from timer@b020000 - Konrad
- Added vreg_dummy comment - Konrad
- sdc_pins grouped - Konrad
- startup-delay-us = <0> - left as is
- bias - added no-bias - Konrad
- :g/msmgpio/s//tlmm/g - Konrad
- mdss/s//display-controller - Konrad
- l11 set-load - Korad
- l12 upper voltage raised to 3.3v since this is what the
downstream kernel says when I boot and interrogate it - bod
- sdhc@address - Discussed with Krzysztof and implemented as discussed
- snoc-mm fix - Discussed with Krzysztof implemented if:then:else:not
- dtc -I dtb -fs apq8039-t2.dtb prodcues
/soc@0/i2c@78b5000: duplicate unit-address
as does every other component that uses this polymorphic dts node
- Renamed type-c i2c port manager IC to "typec" - Krzysztof
/smsm/hexagon@1: Missing #address-cells in interrupt provider
Same output as other upstream and recently upstreamed SoCs
I left these alone for now
link: https://lore.kernel.org/lkml/[email protected]/T/
bootable: https://git.linaro.org/people/bryan.odonoghue/kernel.git/log/?h=linux-next-23-01-16-msm8939-nocpr
V2:
- Sorts core dtsi node list by address followed by alpahbetical sorting
within address sorted nodes - Bjorn
- Drops use of 8916-pins - Bjorn
- Adds msm8939-pm8916.dtsi - Stephan
- Fixes every dts splat from previous submission minus non-converted
.txt compat strings [1] and one yaml error in Bjorn's tree not in -next yet
- I haven't applied Dmitry's change for tsens since that's not been
picked up yet
- Picks up a number of suggestions and fixes from Stephan Gerhold and Vincent Knecht
- Depends on
Applied:
[PATCH v4 0/7] remoteproc: qcom_q6v5_mss: Add MSM8909 and MSM8953
https://lore.kernel.org/linux-arm-msm/[email protected]/
[PATCH v6 0/5] remoteproc: qcom: Add support for pronto-v3
https://lore.kernel.org/linux-arm-msm/[email protected]/
[PATCH v6 00/18] mdss-dsi-ctrl binding and dts fixes
https://lore.kernel.org/linux-arm-msm/[email protected]/
Awaiting application:
https://lore.kernel.org/linux-arm-msm/[email protected]/
- Previous
https://lore.kernel.org/linux-arm-msm/[email protected]/
- Bootable tree
https://git.linaro.org/people/bryan.odonoghue/kernel.git/log/?h=linux-next-23-01-03-msm8939-no-cpr
- [1] DTC_CHK arch/arm64/boot/dts/qcom/apq8039-t2.dtb
Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
qcom/apq8039-t2.dtb: idle-states: cpu-sleep-0:compatible:0: 'qcom,idle-state-spc' is not one of ['arm,idle-state', 'riscv,idle-state']
From schema: Documentation/devicetree/bindings/cpu/idle-states.yaml
qcom/apq8039-t2.dtb: idle-states: cpu-sleep-0:compatible: ['qcom,idle-state-spc', 'arm,idle-state'] is too long
From schema: Documentation/devicetree/bindings/cpu/idle-states.yaml
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /cpus/idle-states/cpu-sleep-0: failed to match any schema with compatible: ['qcom,idle-state-spc', 'arm,idle-state']
Documentation/devicetree/bindings/iommu/qcom,iommu.txt
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/iommu@1ef0000: failed to match any schema with compatible: ['qcom,msm8916-iommu', 'qcom,msm-iommu-v1']
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/iommu@1ef0000/iommu-ctx@4000: failed to match any schema with compatible: ['qcom,msm-iommu-v1-ns']
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/iommu@1ef0000/iommu-ctx@5000: failed to match any schema with compatible: ['qcom,msm-iommu-v1-sec']
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/iommu@1f08000: failed to match any schema with compatible: ['qcom,msm8916-iommu', 'qcom,msm-iommu-v1']
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/iommu@1f08000/iommu-ctx@1000: failed to match any schema with compatible: ['qcom,msm-iommu-v1-ns']
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/iommu@1f08000/iommu-ctx@2000: failed to match any schema with compatible: ['qcom,msm-iommu-v1-ns']
arch/arm64/boot/dts/qcom/pm8916.dtsi f5d7bca55425c8
qcom/apq8039-t2.dtb: pmic@0: 'extcon@1300' does not match any of the regexes: '(.*)?(wled|leds)@[0-9a-f]+$', '^adc-tm@[0-9a-f]+$', '^adc@[0-9a-f]+$', '^audio-codec@[0-9a-f]+$', '^charger@[0-9a-f]+$', '^mpps@[0-9a-f]+$', '^rtc@[0-9a-f]+$', '^temp-alarm@[0-9a-f]+$', '^usb-detect@[0-9a-f]+$', '^usb-vbus-regulator@[0-9a-f]+$', '^vibrator@[0-9a-f]+$', 'gpio@[0-9a-f]+$', 'pinctrl-[0-9]+', 'pon@[0-9a-f]+$'
From schema: Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/spmi@200f000/pmic@1/audio-codec@f000: failed to match any schema with compatible: ['qcom,pm8916-wcd-analog-codec']
yaml documentation error not yet in -next
arm64/boot/dts/qcom/apq8039-t2.dtb: remoteproc@4080000: qcom,halt-regs:0: [33] is too short
From schema: Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml
Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/usb@78d9000: failed to match any schema with compatible: ['qcom,ci-hdrc']
Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt: compatible = "qcom,kpss-acc-v2";
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b088000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b098000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b0a8000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b0b8000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b188000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b198000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b1a8000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b1b8000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
V1:
This series adds in MSM8939 SoC support with two supported devices.
- CPU
MSM8939 is a non-PSCI compliant device. As such in the downstreaming
shipped image custom code is used to bring non-boot cores out of reset.
This drop specifies the boot-method as spin-table instead and is
completely standard. To accomplish this, we rely on lk2nd.
https://github.com/msm8916-mainline/lk2nd/pull/142
- Serial
- i2c
- USB
- eMMC
- MDP/DSI
- WiFi
- Bluetooth
What's not included
- CPR
We have CPR working in a 4.19 kernel quite well but for now it feels like
putting the cart before the horse to gate the SoC and boards on CPR.
- Venus
I've been told this works but I haven't tried it myself and right now
consider it maybe working but probably not 100%.
- Sound
We have a copy-exactly from the 4.19 kernel here in the DTS.
I haven't run the sound through any sort of reasonable test.
Vincent Knecht has some PostmarketOS kernels which use a 5.17 version of
this DTS to get sound up so, I think sound is in good shape.
- CAMSS
There are slight differences between msm8916 and msm8939 for CAMSS. It
doesn't feel like tons of work but, right now it is work we haven't even
started.
- Devices
I've booted on the Square device obviously and this is my regular
hardware for upstream development. I've also booted on the Sony Xperia M4
Aqua including mutli-core bring-up, WiFi and ADB.
Dependencies for this drop:
qcom-cpufreq-nvmem: Add msm8939 with some fixups
link: https://lore.kernel.org/linux-arm-msm/[email protected]/T/#t
Fix apq8016 compat string
link: https://lore.kernel.org/linux-arm-msm/[email protected]/T/#t
dt-bindings: soc: qcom: smd-rpm: Fix missing MSM8936 compatible
link: https://lore.kernel.org/linux-arm-msm/[email protected]/T/#u
Bootable tree here:
https://git.linaro.org/people/bryan.odonoghue/kernel.git/log/?h=v5.18-rc2%2bapq8039-without-cpr
Bryan O'Donoghue (3):
arm64: dts: qcom: Add msm8939 SoC
arm64: dts: qcom: Add Square apq8039-t2 board
arm64: dts: qcom: Add msm8939 Sony Xperia M4 Aqua
Stephan Gerhold (1):
arm64: dts: qcom: Add msm8939-pm8916.dtsi include
arch/arm64/boot/dts/qcom/Makefile | 2 +
arch/arm64/boot/dts/qcom/apq8039-t2.dts | 492 ++++
arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi | 82 +
.../qcom/msm8939-sony-xperia-kanuti-tulip.dts | 184 ++
arch/arm64/boot/dts/qcom/msm8939.dtsi | 2452 +++++++++++++++++
5 files changed, 3212 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/apq8039-t2.dts
create mode 100644 arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts
create mode 100644 arch/arm64/boot/dts/qcom/msm8939.dtsi
--
2.39.2
From: Stephan Gerhold <[email protected]>
The msm8939-pm8916.dtsi include configures the regulator supplies of
MSM8939 used together with PM8916, as recommended by Qualcomm. In rare
cases where boards deviate from the recommended design they can just
avoid using this include.
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Bryan O'Donoghue <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi | 82 ++++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi
diff --git a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi
new file mode 100644
index 0000000000000..24393a1590580
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "msm8939.dtsi"
+#include "pm8916.dtsi"
+
+&dsi0 {
+ vdda-supply = <&pm8916_l2>;
+ vddio-supply = <&pm8916_l6>;
+};
+
+&dsi1 {
+ vdda-supply = <&pm8916_l2>;
+ vddio-supply = <&pm8916_l6>;
+};
+
+&dsi_phy0 {
+ vddio-supply = <&pm8916_l6>;
+};
+
+&dsi_phy1 {
+ vddio-supply = <&pm8916_l6>;
+};
+
+&mpss {
+ pll-supply = <&pm8916_l7>;
+};
+
+&rpm_requests {
+ smd_rpm_regulators: regulators {
+ compatible = "qcom,rpm-pm8916-regulators";
+
+ /* pm8916_s1 is managed by rpmpd (MSM8939_VDDMDCX) */
+ /* pm8916_s2 is managed by rpmpd (MSM8939_VDDCX) */
+ pm8916_s3: s3 {};
+ pm8916_s4: s4 {};
+
+ pm8916_l1: l1 {};
+ pm8916_l2: l2 {};
+ /* pm8916_l3 is managed by rpmpd (MSM8939_VDDMX) */
+ pm8916_l4: l4 {};
+ pm8916_l5: l5 {};
+ pm8916_l6: l6 {};
+ pm8916_l7: l7 {};
+ pm8916_l8: l8 {};
+ pm8916_l9: l9 {};
+ pm8916_l10: l10 {};
+ pm8916_l11: l11 {};
+ pm8916_l12: l12 {};
+ pm8916_l13: l13 {};
+ pm8916_l14: l14 {};
+ pm8916_l15: l15 {};
+ pm8916_l16: l16 {};
+ pm8916_l17: l17 {};
+ pm8916_l18: l18 {};
+ };
+};
+
+&sdhc_1 {
+ vmmc-supply = <&pm8916_l8>;
+ vqmmc-supply = <&pm8916_l5>;
+};
+
+&sdhc_2 {
+ vmmc-supply = <&pm8916_l11>;
+ vqmmc-supply = <&pm8916_l12>;
+};
+
+&usb_hs_phy {
+ v1p8-supply = <&pm8916_l7>;
+ v3p3-supply = <&pm8916_l13>;
+};
+
+&wcnss {
+ vddpx-supply = <&pm8916_l7>;
+};
+
+&wcnss_iris {
+ vddxo-supply = <&pm8916_l7>;
+ vddrfa-supply = <&pm8916_s3>;
+ vddpa-supply = <&pm8916_l9>;
+ vdddig-supply = <&pm8916_l5>;
+};
--
2.39.2
Add msm8939 a derivative SoC of msm8916. This SoC contains a number of key
differences to msm8916.
- big.LITTLE Octa Core - quad 1.5GHz + quad 1.0GHz
- DRAM 1x800 LPDDR3
- Camera 4+4 lane CSI
- Venus @ 1080p60 HEVC
- DSI x 2
- Adreno A405
- WiFi wcn3660/wcn3680b 802.11ac
Co-developed-by: Shawn Guo <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Co-developed-by: Jun Nie <[email protected]>
Signed-off-by: Jun Nie <[email protected]>
Co-developed-by: Benjamin Li <[email protected]>
Signed-off-by: Benjamin Li <[email protected]>
Co-developed-by: James Willcox <[email protected]>
Signed-off-by: James Willcox <[email protected]>
Co-developed-by: Leo Yan <[email protected]>
Signed-off-by: Leo Yan <[email protected]>
Co-developed-by: Joseph Gates <[email protected]>
Signed-off-by: Joseph Gates <[email protected]>
Co-developed-by: Max Chen <[email protected]>
Signed-off-by: Max Chen <[email protected]>
Co-developed-by: Zac Crosby <[email protected]>
Signed-off-by: Zac Crosby <[email protected]>
Co-developed-by: Vincent Knecht <[email protected]>
Signed-off-by: Vincent Knecht <[email protected]>
Co-developed-by: Stephan Gerhold <[email protected]>
Signed-off-by: Stephan Gerhold <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Bryan O'Donoghue <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8939.dtsi | 2452 +++++++++++++++++++++++++
1 file changed, 2452 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/msm8939.dtsi
diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi
new file mode 100644
index 0000000000000..778d24c8aee52
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi
@@ -0,0 +1,2452 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2023, Linaro Limited
+ */
+
+#include <dt-bindings/clock/qcom,gcc-msm8939.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/interconnect/qcom,msm8939.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/reset/qcom,gcc-msm8939.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ /*
+ * Stock LK wants address-cells/size-cells = 2
+ * A number of our drivers want address/size cells = 1
+ * hence the disparity between top-level and /soc below.
+ */
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@100 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "spin-table";
+ reg = <0x100>;
+ next-level-cache = <&L2_1>;
+ qcom,acc = <&acc0>;
+ qcom,saw = <&saw0>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&apcs1_mbox>;
+ #cooling-cells = <2>;
+ L2_1: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU1: cpu@101 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "spin-table";
+ reg = <0x101>;
+ next-level-cache = <&L2_1>;
+ qcom,acc = <&acc1>;
+ qcom,saw = <&saw1>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&apcs1_mbox>;
+ #cooling-cells = <2>;
+ };
+
+ CPU2: cpu@102 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "spin-table";
+ reg = <0x102>;
+ next-level-cache = <&L2_1>;
+ qcom,acc = <&acc2>;
+ qcom,saw = <&saw2>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&apcs1_mbox>;
+ #cooling-cells = <2>;
+ };
+
+ CPU3: cpu@103 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "spin-table";
+ reg = <0x103>;
+ next-level-cache = <&L2_1>;
+ qcom,acc = <&acc3>;
+ qcom,saw = <&saw3>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&apcs1_mbox>;
+ #cooling-cells = <2>;
+ };
+
+ CPU4: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "spin-table";
+ reg = <0x0>;
+ qcom,acc = <&acc4>;
+ qcom,saw = <&saw4>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&apcs0_mbox>;
+ #cooling-cells = <2>;
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ CPU5: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "spin-table";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ qcom,acc = <&acc5>;
+ qcom,saw = <&saw5>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&apcs0_mbox>;
+ #cooling-cells = <2>;
+ };
+
+ CPU6: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "spin-table";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ qcom,acc = <&acc6>;
+ qcom,saw = <&saw6>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&apcs0_mbox>;
+ #cooling-cells = <2>;
+ };
+
+ CPU7: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "spin-table";
+ reg = <0x3>;
+ next-level-cache = <&L2_0>;
+ qcom,acc = <&acc7>;
+ qcom,saw = <&saw7>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&apcs0_mbox>;
+ #cooling-cells = <2>;
+ };
+
+ idle-states {
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible ="qcom,idle-state-spc", "arm,idle-state";
+ entry-latency-us = <130>;
+ exit-latency-us = <150>;
+ min-residency-us = <2000>;
+ local-timer-stop;
+ };
+ };
+ };
+
+ /*
+ * MSM8939 has a big.LITTLE heterogeneous computing architecture,
+ * consisting of two clusters of four ARM Cortex-A53s each. The
+ * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs
+ * at 1.5-1.7GHz.
+ *
+ * The enable method used here is spin-table which presupposes use
+ * of a 2nd stage boot shim such as lk2nd to have installed a
+ * spin-table, the downstream non-psci/non-spin-table method that
+ * default msm8916/msm8936/msm8939 will not be supported upstream.
+ */
+ cpu-map {
+ /* LITTLE (efficiency) cluster */
+ cluster0 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+
+ /* big (performance) cluster */
+ /* Boot CPU is cluster 1 core 0 */
+ cluster1 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-msm8916", "qcom,scm";
+ clocks = <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>;
+ clock-names = "core", "bus", "iface";
+ #reset-cells = <1>;
+
+ qcom,dload-mode = <&tcsr 0x6100>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0x0 0x80000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ tz-apps@86000000 {
+ reg = <0x0 0x86000000 0x0 0x300000>;
+ no-map;
+ };
+
+ smem@86300000 {
+ compatible = "qcom,smem";
+ reg = <0x0 0x86300000 0x0 0x100000>;
+ no-map;
+
+ hwlocks = <&tcsr_mutex 3>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ };
+
+ hypervisor@86400000 {
+ reg = <0x0 0x86400000 0x0 0x100000>;
+ no-map;
+ };
+
+ tz@86500000 {
+ reg = <0x0 0x86500000 0x0 0x180000>;
+ no-map;
+ };
+
+ reserved@86680000 {
+ reg = <0x0 0x86680000 0x0 0x80000>;
+ no-map;
+ };
+
+ rmtfs@86700000 {
+ compatible = "qcom,rmtfs-mem";
+ reg = <0x0 0x86700000 0x0 0xe0000>;
+ no-map;
+
+ qcom,client-id = <1>;
+ };
+
+ rfsa@867e0000 {
+ reg = <0x0 0x867e0000 0x0 0x20000>;
+ no-map;
+ };
+
+ mpss_mem: mpss@86800000 {
+ reg = <0x0 0x86800000 0x0 0x5500000>;
+ no-map;
+ };
+
+ wcnss_mem: wcnss@8bd00000 {
+ reg = <0x0 0x8bd00000 0x0 0x600000>;
+ no-map;
+ };
+
+ venus_mem: venus@8c300000 {
+ reg = <0x0 0x8c300000 0x0 0x800000>;
+ no-map;
+ };
+
+ mba_mem: mba@8cb00000 {
+ reg = <0x0 0x8cb00000 0x0 0x100000>;
+ no-map;
+ };
+ };
+
+ smd {
+ compatible = "qcom,smd";
+
+ rpm {
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs1_mbox 8 0>;
+ qcom,smd-edge = <15>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-msm8936";
+ qcom,smd-channels = "rpm_requests";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board>;
+ };
+
+ rpmpd: power-controller {
+ compatible = "qcom,msm8939-rpmpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmpd_opp_table>;
+
+ rpmpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmpd_opp_ret: opp1 {
+ opp-level = <1>;
+ };
+
+ rpmpd_opp_svs_krait: opp2 {
+ opp-level = <2>;
+ };
+
+ rpmpd_opp_svs_soc: opp3 {
+ opp-level = <3>;
+ };
+
+ rpmpd_opp_nom: opp4 {
+ opp-level = <4>;
+ };
+
+ rpmpd_opp_turbo: opp5 {
+ opp-level = <5>;
+ };
+
+ rpmpd_opp_super_turbo: opp6 {
+ opp-level = <6>;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ smp2p-hexagon {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+
+ interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&apcs1_mbox 14>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ hexagon_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+
+ #qcom,smem-state-cells = <1>;
+ };
+
+ hexagon_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ };
+ };
+
+ smp2p-wcnss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <451>, <431>;
+
+ interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&apcs1_mbox 18>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <4>;
+
+ wcnss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ wcnss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+
+ #qcom,smem-state-cells = <1>;
+ };
+ };
+
+ smsm {
+ compatible = "qcom,smsm";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ipc-1 = <&apcs1_mbox 8 13>;
+ qcom,ipc-3 = <&apcs1_mbox 8 19>;
+
+ apps_smsm: apps@0 {
+ reg = <0>;
+
+ #qcom,smem-state-cells = <1>;
+ };
+
+ hexagon_smsm: hexagon@1 {
+ reg = <1>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ wcnss_smsm: wcnss@6 {
+ reg = <6>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+
+ rng@22000 {
+ compatible = "qcom,prng";
+ reg = <0x00022000 0x200>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "core";
+ };
+
+ qfprom: qfprom@5c000 {
+ compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
+ reg = <0x0005c000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ tsens_base1: base1@a0 {
+ reg = <0xa0 0x1>;
+ bits = <0 8>;
+ };
+
+ tsens_s6_p1: s6-p1@a1 {
+ reg = <0xa1 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s6_p2: s6-p2@a1 {
+ reg = <0xa1 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s7_p1: s7-p1@a2 {
+ reg = <0xa2 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s7_p2: s7-p2@a3 {
+ reg = <0xa3 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_s8_p1: s8-p1@a4 {
+ reg = <0xa4 0x1>;
+ bits = <0 6>;
+ };
+
+ tsens_s8_p2: s8-p2@a4 {
+ reg = <0xa4 0x2>;
+ bits = <6 6>;
+ };
+
+ tsens_s9_p1: s9-p1@a5 {
+ reg = <0xa5 0x2>;
+ bits = <4 6>;
+ };
+
+ tsens_s9_p2: s9-p2@a6 {
+ reg = <0xa6 0x1>;
+ bits = <2 6>;
+ };
+
+ tsens_base2: base2@a7 {
+ reg = <0xa7 0x1>;
+ bits = <0 8>;
+ };
+
+ tsens_mode: mode@d0 {
+ reg = <0xd0 0x1>;
+ bits = <0 3>;
+ };
+
+ tsens_s0_p1: s0-p1@d0 {
+ reg = <0xd0 0x2>;
+ bits = <3 6>;
+ };
+
+ tsens_s0_p2: s0-p1@d1 {
+ reg = <0xd1 0x1>;
+ bits = <1 6>;
+ };
+
+ tsens_s1_p1: s1-p1@d1 {
+ reg = <0xd1 0x2>;
+ bits = <7 6>;
+ };
+
+ tsens_s1_p2: s1-p2@d2 {
+ reg = <0xd2 0x2>;
+ bits = <5 6>;
+ };
+
+ tsens_s2_p1: s2-p1@d3 {
+ reg = <0xd3 0x2>;
+ bits = <3 6>;
+ };
+
+ tsens_s2_p2: s2-p2@d4 {
+ reg = <0xd4 0x1>;
+ bits = <1 6>;
+ };
+
+ tsens_s3_p1: s3-p1@d4 {
+ reg = <0xd4 0x2>;
+ bits = <7 6>;
+ };
+
+ tsens_s3_p2: s3-p2@d5 {
+ reg = <0xd5 0x2>;
+ bits = <5 6>;
+ };
+
+ tsens_s5_p1: s5-p1@d6 {
+ reg = <0xd6 0x2>;
+ bits = <3 6>;
+ };
+
+ tsens_s5_p2: s5-p2@d7 {
+ reg = <0xd7 0x1>;
+ bits = <1 6>;
+ };
+ };
+
+ rpm_msg_ram: sram@60000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x00060000 0x8000>;
+ };
+
+ bimc: interconnect@400000 {
+ compatible = "qcom,msm8939-bimc";
+ reg = <0x00400000 0x62000>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+ <&rpmcc RPM_SMD_BIMC_A_CLK>;
+ #interconnect-cells = <1>;
+ };
+
+ tsens: thermal-sensor@4a9000 {
+ compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1";
+ reg = <0x004a9000 0x1000>, /* TM */
+ <0x004a8000 0x1000>; /* SROT */
+ nvmem-cells = <&tsens_mode>,
+ <&tsens_base1>, <&tsens_base2>,
+ <&tsens_s0_p1>, <&tsens_s0_p2>,
+ <&tsens_s1_p1>, <&tsens_s1_p2>,
+ <&tsens_s2_p1>, <&tsens_s2_p2>,
+ <&tsens_s3_p1>, <&tsens_s3_p2>,
+ <&tsens_s5_p1>, <&tsens_s5_p2>,
+ <&tsens_s6_p1>, <&tsens_s6_p2>,
+ <&tsens_s7_p1>, <&tsens_s7_p2>,
+ <&tsens_s8_p1>, <&tsens_s8_p2>,
+ <&tsens_s9_p1>, <&tsens_s9_p2>;
+ nvmem-cell-names = "mode",
+ "base1", "base2",
+ "s0_p1", "s0_p2",
+ "s1_p1", "s1_p2",
+ "s2_p1", "s2_p2",
+ "s3_p1", "s3_p2",
+ "s5_p1", "s5_p2",
+ "s6_p1", "s6_p2",
+ "s7_p1", "s7_p2",
+ "s8_p1", "s8_p2",
+ "s9_p1", "s9_p2";
+ #qcom,sensors = <9>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+ #thermal-sensor-cells = <1>;
+ };
+
+ restart@4ab000 {
+ compatible = "qcom,pshold";
+ reg = <0x004ab000 0x4>;
+ };
+
+ pcnoc: interconnect@500000 {
+ compatible = "qcom,msm8939-pcnoc";
+ reg = <0x00500000 0x11000>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
+ <&rpmcc RPM_SMD_PCNOC_A_CLK>;
+ #interconnect-cells = <1>;
+ };
+
+ snoc: interconnect@580000 {
+ compatible = "qcom,msm8939-snoc";
+ reg = <0x00580000 0x14080>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+ <&rpmcc RPM_SMD_SNOC_A_CLK>;
+ #interconnect-cells = <1>;
+
+ snoc_mm: interconnect-snoc {
+ compatible = "qcom,msm8939-snoc-mm";
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_SYSMMNOC_CLK>,
+ <&rpmcc RPM_SMD_SYSMMNOC_A_CLK>;
+ #interconnect-cells = <1>;
+ };
+ };
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,msm8916-pinctrl";
+ reg = <0x01000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ gpio-ranges = <&tlmm 0 0 122>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ blsp1_uart1_default: blsp1-uart1-default-state {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "blsp_uart1";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp1_uart1_sleep: blsp1-uart1-sleep-state {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp1_uart2_default: blsp1-uart2-default-state {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp1_uart2_sleep: blsp1-uart2-sleep-state {
+ pins = "gpio4", "gpio5";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ camera_front_default: camera-front-default-state {
+ pwdn-pins {
+ pins = "gpio33";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ rst-pins {
+ pins = "gpio28";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mclk1-pins {
+ pins = "gpio27";
+ function = "cam_mclk1";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ camera_rear_default: camera-rear-default-state {
+ pwdn-pins {
+ pins = "gpio34";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ rst-pins {
+ pins = "gpio35";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ mclk0-pins {
+ pins = "gpio26";
+ function = "cam_mclk0";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ cci0_default: cci0-default-state {
+ pins = "gpio29", "gpio30";
+ function = "cci_i2c";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cdc_pdm_lines_default: pdm-lines-default-state {
+ pins = "gpio63", "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68";
+ function = "cdc_pdm0";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ cdc_pdm_lines_sleep: pdm-lines-suspend-state {
+ pins = "gpio63", "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68";
+ function = "cdc_pdm0";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cdc_dmic_lines_act: cdc-dmic-lines-on-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "dmic0_clk";
+ drive-strength = <8>;
+ };
+
+ data-pins {
+ pins = "gpio1";
+ function = "dmic0_data";
+ drive-strength = <8>;
+ };
+ };
+
+ cdc_dmic_lines_sus: cdc-dmic-lines-off-state {
+ clk-pins {
+ pins = "gpio0";
+ function = "dmic0_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio1";
+ function = "dmic0_data";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ ext-mclk-tlmm-lines-state {
+ ext_mclk_tlmm_lines_act: mclk-lines-on-pins {
+ pins = "gpio116";
+ function = "pri_mi2s";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ ext_mclk_tlmm_lines_sus: mclk-lines-off-pins {
+ pins = "gpio116";
+ function = "pri_mi2s";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ ext-pri-tlmm-lines-state {
+ ext_pri_tlmm_lines_act: ext-pa-on-pins {
+ pins = "gpio113", "gpio114", "gpio115", "gpio116";
+ function = "pri_mi2s";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ ext_pri_tlmm_lines_sus: ext-pa-off-pins {
+ pins = "gpio113", "gpio114", "gpio115", "gpio116";
+ function = "pri_mi2s";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ ext-pri-ws-line-state {
+ ext_pri_ws_act: ext-pa-on-pins {
+ pins = "gpio110";
+ function = "pri_mi2s_ws";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ ext_pri_ws_sus: ext-pa-off-pins {
+ pins = "gpio110";
+ function = "pri_mi2s_ws";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ /* secondary Mi2S */
+ ext-sec-tlmm-lines-state {
+ ext_sec_tlmm_lines_act: tlmm-lines-on-pins {
+ pins = "gpio112", "gpio117", "gpio118", "gpio119";
+ function = "sec_mi2s";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ ext_sec_tlmm_lines_sus: tlmm-lines-off-pins {
+ pins = "gpio112", "gpio117", "gpio118", "gpio119";
+ function = "sec_mi2s";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c1_default: i2c1-default-state {
+ pins = "gpio2", "gpio3";
+ function = "blsp_i2c1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c1_sleep: i2c1-sleep-state {
+ pins = "gpio2", "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c2_default: i2c2-default-state {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c2_sleep: i2c2-sleep-state {
+ pins = "gpio6", "gpio7";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c3_default: i2c3-default-state {
+ pins = "gpio10", "gpio11";
+ function = "blsp_i2c3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c3_sleep: i2c3-sleep-state {
+ pins = "gpio10", "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c4_default: i2c4-default-state {
+ pins = "gpio14", "gpio15";
+ function = "blsp_i2c4";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c4_sleep: i2c4-sleep-state {
+ pins = "gpio14", "gpio15";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c5_default: i2c5-default-state {
+ pins = "gpio18", "gpio19";
+ function = "blsp_i2c5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c5_sleep: i2c5-sleep-state {
+ pins = "gpio18", "gpio19";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c6_default: i2c6-default-state {
+ pins = "gpio22", "gpio23";
+ function = "blsp_i2c6";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ i2c6_sleep: i2c6-sleep-state {
+ pins = "gpio22", "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdc1_default_state: sdc1-default-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ };
+
+ sdc1_sleep_state: sdc1-sleep-state {
+ clk-pins {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+
+ sdc2_default_state: sdc2-default-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ cd-pins {
+ pins = "gpio38";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_sleep_state: sdc2-sleep-state {
+ clk-pins {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd-pins {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data-pins {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ cd-pins {
+ pins = "gpio38";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ spi1_default: spi1-default-state {
+ spi-pins {
+ pins = "gpio0", "gpio1", "gpio3";
+ function = "blsp_spi1";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ cs-pins {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ spi1_sleep: spi1-sleep-state {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ spi2_default: spi2-default-state {
+ spi-pins {
+ pins = "gpio4", "gpio5", "gpio7";
+ function = "blsp_spi2";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ cs-pins {
+ pins = "gpio6";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ spi2_sleep: spi2-sleep-state {
+ pins = "gpio4", "gpio5", "gpio6", "gpio7";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ spi3_default: spi3-default-state {
+ spi-pins {
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "blsp_spi3";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ cs-pins {
+ pins = "gpio10";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ spi3_sleep: spi3-sleep-state {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ spi4_default: spi4-default-state {
+ spi-pins {
+ pins = "gpio12", "gpio13", "gpio15";
+ function = "blsp_spi4";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ cs-pins {
+ pins = "gpio14";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ spi4_sleep: spi4-sleep-state {
+ pins = "gpio12", "gpio13", "gpio14", "gpio15";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ spi5_default: spi5-default-state {
+ spi-pins {
+ pins = "gpio16", "gpio17", "gpio19";
+ function = "blsp_spi5";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ cs-pins {
+ pins = "gpio18";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ spi5_sleep: spi5-sleep-state {
+ pins = "gpio16", "gpio17", "gpio18", "gpio19";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ spi6_default: spi6-default-state {
+ spi-pins {
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "blsp_spi6";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ cs-pins {
+ pins = "gpio22";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ spi6_sleep: spi6-sleep-state {
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wcnss_pin_a: wcnss-active-state {
+ pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
+ function = "wcss_wlan";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+ };
+
+ gcc: clock-controller@1800000 {
+ compatible = "qcom,gcc-msm8939";
+ reg = <0x01800000 0x80000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&sleep_clk>,
+ <&dsi_phy0 1>,
+ <&dsi_phy0 0>,
+ <0>,
+ <0>,
+ <0>;
+ clock-names = "xo",
+ "sleep_clk",
+ "dsi0pll",
+ "dsi0pllbyte",
+ "ext_mclk",
+ "ext_pri_i2s",
+ "ext_sec_i2s";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ tcsr_mutex: hwlock@1905000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x01905000 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ tcsr: syscon@1937000 {
+ compatible = "qcom,tcsr-msm8916", "syscon";
+ reg = <0x01937000 0x30000>;
+ };
+
+ mdss: display-subsystem@1a00000 {
+ compatible = "qcom,mdss";
+ reg = <0x01a00000 0x1000>,
+ <0x01ac8000 0x3000>;
+ reg-names = "mdss_phys", "vbif_phys";
+
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_VSYNC_CLK>;
+ clock-names = "iface",
+ "bus",
+ "vsync";
+
+ power-domains = <&gcc MDSS_GDSC>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+ ranges;
+
+ status = "disabled";
+
+ mdp: display-controller@1a01000 {
+ compatible = "qcom,mdp5";
+ reg = <0x01a01000 0x89000>;
+ reg-names = "mdp_phys";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_VSYNC_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "vsync";
+
+ iommus = <&apps_iommu 4>;
+
+ interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
+ <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>;
+ interconnect-names = "mdp0-mem", "mdp1-mem";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdp5_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdp5_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@1a98000 {
+ compatible = "qcom,msm8916-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0x01a98000 0x25c>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_BYTE0_CLK>,
+ <&gcc GCC_MDSS_PCLK0_CLK>,
+ <&gcc GCC_MDSS_ESC0_CLK>;
+ clock-names = "mdp_core",
+ "iface",
+ "bus",
+ "byte",
+ "pixel",
+ "core";
+ assigned-clocks = <&gcc BYTE0_CLK_SRC>,
+ <&gcc PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&dsi_phy0 0>,
+ <&dsi_phy0 1>;
+
+ phys = <&dsi_phy0>;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&mdp5_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi_phy0: phy@1a98300 {
+ compatible = "qcom,dsi-phy-28nm-lp";
+ reg = <0x01a98300 0xd4>,
+ <0x01a98500 0x280>,
+ <0x01a98780 0x30>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ dsi1: dsi@1aa0000 {
+ compatible = "qcom,msm8916-dsi-ctrl",
+ "qcom,mdss-dsi-ctrl";
+ reg = <0x01aa0000 0x25c>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <5>;
+
+ clocks = <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_BYTE1_CLK>,
+ <&gcc GCC_MDSS_PCLK1_CLK>,
+ <&gcc GCC_MDSS_ESC1_CLK>;
+ clock-names = "mdp_core",
+ "iface",
+ "bus",
+ "byte",
+ "pixel",
+ "core";
+ assigned-clocks = <&gcc BYTE1_CLK_SRC>,
+ <&gcc PCLK1_CLK_SRC>;
+ assigned-clock-parents = <&dsi_phy0 0>,
+ <&dsi_phy0 1>;
+ phys = <&dsi_phy1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi1_in: endpoint {
+ remote-endpoint = <&mdp5_intf2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi1_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi_phy1: phy@1aa0300 {
+ compatible = "qcom,dsi-phy-28nm-lp";
+ reg = <0x01aa0300 0xd4>,
+ <0x01aa0500 0x280>,
+ <0x01aa0780 0x30>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ gpu@1c00000 {
+ compatible = "qcom,adreno-405.0", "qcom,adreno";
+ reg = <0x01c00000 0x10000>;
+ reg-names = "kgsl_3d0_reg_memory";
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+ clock-names = "core",
+ "iface",
+ "mem",
+ "mem_iface",
+ "alt_mem_iface",
+ "gfx3d",
+ "rbbmtimer";
+ clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
+ <&gcc GCC_OXILI_AHB_CLK>,
+ <&gcc GCC_OXILI_GMEM_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>,
+ <&gcc GCC_BIMC_GPU_CLK>,
+ <&gcc GFX3D_CLK_SRC>,
+ <&gcc GCC_OXILI_TIMER_CLK>;
+ power-domains = <&gcc OXILI_GDSC>;
+ operating-points-v2 = <&opp_table>;
+ iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
+
+ opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ };
+
+ opp-465000000 {
+ opp-hz = /bits/ 64 <465000000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ };
+
+ opp-220000000 {
+ opp-hz = /bits/ 64 <220000000>;
+ };
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ };
+ };
+ };
+
+ apps_iommu: iommu@1ef0000 {
+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+ reg = <0x01ef0000 0x3000>;
+ ranges = <0 0x01e20000 0x40000>;
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_APSS_TCU_CLK>;
+ clock-names = "iface", "bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #iommu-cells = <1>;
+ qcom,iommu-secure-id = <17>;
+
+ /* mdp_0: */
+ iommu-ctx@4000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x4000 0x1000>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ /* venus_ns: */
+ iommu-ctx@5000 {
+ compatible = "qcom,msm-iommu-v1-sec";
+ reg = <0x5000 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpu_iommu: iommu@1f08000 {
+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+ ranges = <0 0x1f08000 0x10000>;
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_GFX_TCU_CLK>,
+ <&gcc GCC_GFX_TBU_CLK>;
+ clock-names = "iface", "bus", "tbu";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #iommu-cells = <1>;
+ qcom,iommu-secure-id = <18>;
+
+ /* gfx3d_user: */
+ iommu-ctx@1000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ /* gfx3d_priv: */
+ iommu-ctx@2000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ spmi_bus: spmi@200f000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0200f000 0x001000>,
+ <0x02400000 0x400000>,
+ <0x02c00000 0x400000>,
+ <0x03800000 0x200000>,
+ <0x0200a000 0x002100>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
+ mpss: remoteproc@4080000 {
+ compatible = "qcom,msm8916-mss-pil";
+ reg = <0x04080000 0x100>, <0x04020000 0x040>;
+ reg-names = "qdsp6", "rmb";
+ interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
+ <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+ clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
+ <&gcc GCC_BOOT_ROM_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface",
+ "bus",
+ "mem",
+ "xo";
+ power-domains = <&rpmpd MSM8939_VDDMDCX>,
+ <&rpmpd MSM8939_VDDMX>;
+ power-domain-names = "cx", "mx";
+ qcom,smem-states = <&hexagon_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+ resets = <&scm 0>;
+ reset-names = "mss_restart";
+ qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
+ status = "disabled";
+
+ mba {
+ memory-region = <&mba_mem>;
+ };
+
+ mpss {
+ memory-region = <&mpss_mem>;
+ };
+
+ smd-edge {
+ interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,smd-edge = <0>;
+ mboxes = <&apcs1_mbox 12>;
+ qcom,remote-pid = <1>;
+
+ label = "hexagon";
+ };
+ };
+
+ sound: sound@7702000 {
+ compatible = "qcom,apq8016-sbc-sndcard";
+ reg = <0x07702000 0x4>,
+ <0x07702004 0x4>;
+ reg-names = "mic-iomux", "spkr-iomux";
+ status = "disabled";
+ };
+
+ lpass: audio-controller@7708000 {
+ compatible = "qcom,apq8016-lpass-cpu";
+ reg = <0x07708000 0x10000>;
+ reg-names = "lpass-lpaif";
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpass-irq-lpaif";
+ clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
+ <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
+ <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
+ <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
+ <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
+ <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
+ <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
+ clock-names = "ahbix-clk",
+ "mi2s-bit-clk0",
+ "mi2s-bit-clk1",
+ "mi2s-bit-clk2",
+ "mi2s-bit-clk3",
+ "pcnoc-mport-clk",
+ "pcnoc-sway-clk";
+ #sound-dai-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ lpass_codec: audio-codec@771c000 {
+ compatible = "qcom,msm8916-wcd-digital-codec";
+ reg = <0x0771c000 0x400>;
+ clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
+ <&gcc GCC_CODEC_DIGCODEC_CLK>;
+ clock-names = "ahbix-clk", "mclk";
+ #sound-dai-cells = <1>;
+ };
+
+ sdhc_1: mmc@7824900 {
+ compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
+ reg = <0x07824900 0x11c>, <0x07824000 0x800>;
+ reg-names = "hc", "core";
+
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "core", "xo";
+ resets = <&gcc GCC_SDCC1_BCR>;
+ mmc-ddr-1_8v;
+ bus-width = <8>;
+ non-removable;
+ status = "disabled";
+ };
+
+ sdhc_2: mmc@7864900 {
+ compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
+ reg = <0x07864900 0x11c>, <0x07864000 0x800>;
+ reg-names = "hc", "core";
+
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "core", "xo";
+ resets = <&gcc GCC_SDCC2_BCR>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ blsp_dma: dma-controller@7884000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07884000 0x23000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ blsp1_uart1: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078af000 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 0>, <&blsp_dma 1>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&blsp1_uart1_default>;
+ pinctrl-1 = <&blsp1_uart1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ };
+
+ blsp1_uart2: serial@78b0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078b0000 0x200>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 2>, <&blsp_dma 3>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&blsp1_uart2_default>;
+ pinctrl-1 = <&blsp1_uart2_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ };
+
+ blsp_i2c1: i2c@78b5000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b5000 0x500>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&i2c1_default>;
+ pinctrl-1 = <&i2c1_sleep>;
+ pinctrl-names = "default", "sleep";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_spi1: spi@78b5000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x078b5000 0x500>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&spi1_default>;
+ pinctrl-1 = <&spi1_sleep>;
+ pinctrl-names = "default", "sleep";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_i2c2: i2c@78b6000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b6000 0x500>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 6>, <&blsp_dma 7>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&i2c2_default>;
+ pinctrl-1 = <&i2c2_sleep>;
+ pinctrl-names = "default", "sleep";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_spi2: spi@78b6000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x078b6000 0x500>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 6>, <&blsp_dma 7>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&spi2_default>;
+ pinctrl-1 = <&spi2_sleep>;
+ pinctrl-names = "default", "sleep";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_i2c3: i2c@78b7000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b7000 0x500>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 8>, <&blsp_dma 9>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&i2c3_default>;
+ pinctrl-1 = <&i2c3_sleep>;
+ pinctrl-names = "default", "sleep";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_spi3: spi@78b7000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x078b7000 0x500>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 8>, <&blsp_dma 9>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&spi3_default>;
+ pinctrl-1 = <&spi3_sleep>;
+ pinctrl-names = "default", "sleep";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_i2c4: i2c@78b8000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b8000 0x500>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 10>, <&blsp_dma 11>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&i2c4_default>;
+ pinctrl-1 = <&i2c4_sleep>;
+ pinctrl-names = "default", "sleep";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_spi4: spi@78b8000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x078b8000 0x500>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 10>, <&blsp_dma 11>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&spi4_default>;
+ pinctrl-1 = <&spi4_sleep>;
+ pinctrl-names = "default", "sleep";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_i2c5: i2c@78b9000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b9000 0x500>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&i2c5_default>;
+ pinctrl-1 = <&i2c5_sleep>;
+ pinctrl-names = "default", "sleep";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_spi5: spi@78b9000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x078b9000 0x500>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&spi5_default>;
+ pinctrl-1 = <&spi5_sleep>;
+ pinctrl-names = "default", "sleep";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_i2c6: i2c@78ba000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078ba000 0x500>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&i2c6_default>;
+ pinctrl-1 = <&i2c6_sleep>;
+ pinctrl-names = "default", "sleep";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp_spi6: spi@78ba000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x078ba000 0x500>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
+ dma-names = "tx", "rx";
+ pinctrl-0 = <&spi6_default>;
+ pinctrl-1 = <&spi6_sleep>;
+ pinctrl-names = "default", "sleep";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ usb: usb@78d9000 {
+ compatible = "qcom,ci-hdrc";
+ reg = <0x078d9000 0x200>,
+ <0x078d9200 0x200>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_USB_HS_AHB_CLK>,
+ <&gcc GCC_USB_HS_SYSTEM_CLK>;
+ clock-names = "iface", "core";
+ assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
+ assigned-clock-rates = <80000000>;
+ resets = <&gcc GCC_USB_HS_BCR>;
+ reset-names = "core";
+ #reset-cells = <1>;
+ phy_type = "ulpi";
+ dr_mode = "otg";
+ adp-disable;
+ hnp-disable;
+ srp-disable;
+ ahb-burst-config = <0>;
+ phy-names = "usb-phy";
+ phys = <&usb_hs_phy>;
+ status = "disabled";
+
+ ulpi {
+ usb_hs_phy: phy {
+ compatible = "qcom,usb-hs-phy-msm8916",
+ "qcom,usb-hs-phy";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+ clock-names = "ref", "sleep";
+ resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
+ reset-names = "phy", "por";
+ #phy-cells = <0>;
+ qcom,init-seq = /bits/ 8 <0x0 0x44>,
+ <0x1 0x6b>,
+ <0x2 0x24>,
+ <0x3 0x13>;
+ };
+ };
+ };
+
+ wcnss: remoteproc@a204000 {
+ compatible = "qcom,pronto-v2-pil", "qcom,pronto";
+ interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+ reg = <0x0a204000 0x2000>,
+ <0x0a202000 0x1000>,
+ <0x0a21b000 0x3000>;
+ reg-names = "ccu", "dxe", "pmu";
+
+ memory-region = <&wcnss_mem>;
+
+ power-domains = <&rpmpd MSM8939_VDDCX>,
+ <&rpmpd MSM8939_VDDMX>;
+ power-domain-names = "cx", "mx";
+
+ qcom,smem-states = <&wcnss_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wcnss_pin_a>;
+
+ status = "disabled";
+
+ wcnss_iris: iris {
+ /* Separate chip, compatible is board-specific */
+ clocks = <&rpmcc RPM_SMD_RF_CLK2>;
+ clock-names = "xo";
+ };
+
+ smd-edge {
+ interrupts = <GIC_SPI 142 1>;
+ qcom,ipc = <&apcs1_mbox 8 17>;
+ qcom,smd-edge = <6>;
+ qcom,remote-pid = <4>;
+
+ label = "pronto";
+
+ wcnss {
+ compatible = "qcom,wcnss";
+ qcom,smd-channels = "WCNSS_CTRL";
+
+ qcom,mmio = <&wcnss>;
+
+ wcnss_bt: bluetooth {
+ compatible = "qcom,wcnss-bt";
+ };
+
+ wcnss_wifi: wifi {
+ compatible = "qcom,wcnss-wlan";
+
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ qcom,smem-states = <&apps_smsm 10>,
+ <&apps_smsm 9>;
+ qcom,smem-state-names = "tx-enable",
+ "tx-rings-empty";
+ };
+ };
+ };
+ };
+
+ intc: interrupt-controller@b000000 {
+ compatible = "qcom,msm-qgic2";
+ reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
+ <0x0b001000 0x1000>, <0x0b004000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ apcs1_mbox: mailbox@b011000 {
+ compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
+ reg = <0x0b011000 0x1000>;
+ clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "pll", "aux", "ref";
+ #clock-cells = <0>;
+ assigned-clocks = <&apcs2>;
+ assigned-clock-rates = <297600000>;
+ #mbox-cells = <1>;
+ };
+
+ a53pll_c1: clock@b016000 {
+ compatible = "qcom,msm8939-a53pll";
+ reg = <0x0b016000 0x40>;
+ #clock-cells = <0>;
+ };
+
+ acc0: clock-controller@b088000 {
+ compatible = "qcom,kpss-acc-v2";
+ reg = <0x0b088000 0x1000>;
+ };
+
+ saw0: power-manager@b089000 {
+ compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
+ reg = <0x0b089000 0x1000>;
+ };
+
+ acc1: clock-controller@b098000 {
+ compatible = "qcom,kpss-acc-v2";
+ reg = <0x0b098000 0x1000>;
+ };
+
+ saw1: power-manager@b099000 {
+ compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
+ reg = <0x0b099000 0x1000>;
+ };
+
+ acc2: clock-controller@b0a8000 {
+ compatible = "qcom,kpss-acc-v2";
+ reg = <0x0b0a8000 0x1000>;
+ };
+
+ saw2: power-manager@b0a9000 {
+ compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
+ reg = <0x0b0a9000 0x1000>;
+ };
+
+ acc3: clock-controller@b0b8000 {
+ compatible = "qcom,kpss-acc-v2";
+ reg = <0x0b0b8000 0x1000>;
+ };
+
+ saw3: power-manager@b0b9000 {
+ compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
+ reg = <0x0b0b9000 0x1000>;
+ };
+
+ apcs0_mbox: mailbox@b111000 {
+ compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
+ reg = <0x0b111000 0x1000>;
+ clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "pll", "aux", "ref";
+ #clock-cells = <0>;
+ #mbox-cells = <1>;
+ };
+
+ a53pll_c0: clock@b116000 {
+ compatible = "qcom,msm8939-a53pll";
+ reg = <0x0b116000 0x40>;
+ #clock-cells = <0>;
+ };
+
+ timer@b120000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0b120000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ frame@b121000 {
+ reg = <0x0b121000 0x1000>,
+ <0x0b122000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <0>;
+ };
+
+ frame@b123000 {
+ reg = <0x0b123000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <1>;
+ status = "disabled";
+ };
+
+ frame@b124000 {
+ reg = <0x0b124000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <2>;
+ status = "disabled";
+ };
+
+ frame@b125000 {
+ reg = <0x0b125000 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <3>;
+ status = "disabled";
+ };
+
+ frame@b126000 {
+ reg = <0x0b126000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <4>;
+ status = "disabled";
+ };
+
+ frame@b127000 {
+ reg = <0x0b127000 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <5>;
+ status = "disabled";
+ };
+
+ frame@b128000 {
+ reg = <0x0b128000 0x1000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <6>;
+ status = "disabled";
+ };
+ };
+
+ acc4: clock-controller@b188000 {
+ compatible = "qcom,kpss-acc-v2";
+ reg = <0x0b188000 0x1000>;
+ };
+
+ saw4: power-manager@b189000 {
+ compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
+ reg = <0x0b189000 0x1000>;
+ };
+
+ acc5: clock-controller@b198000 {
+ compatible = "qcom,kpss-acc-v2";
+ reg = <0x0b198000 0x1000>;
+ };
+
+ saw5: power-manager@b199000 {
+ compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
+ reg = <0x0b199000 0x1000>;
+ };
+
+ acc6: clock-controller@b1a8000 {
+ compatible = "qcom,kpss-acc-v2";
+ reg = <0x0b1a8000 0x1000>;
+ };
+
+ saw6: power-manager@b1a9000 {
+ compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
+ reg = <0x0b1a9000 0x1000>;
+ };
+
+ acc7: clock-controller@b1b8000 {
+ compatible = "qcom,kpss-acc-v2";
+ reg = <0x0b1b8000 0x1000>;
+ };
+
+ saw7: power-manager@b1b9000 {
+ compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2";
+ reg = <0x0b1b9000 0x1000>;
+ };
+
+ a53pll_cci: clock@b1d0000 {
+ compatible = "qcom,msm8939-a53pll";
+ reg = <0x0b1d0000 0x40>;
+ #clock-cells = <0>;
+ };
+
+ apcs2: mailbox@b1d1000 {
+ compatible = "qcom,msm8939-apcs-kpss-global", "syscon";
+ reg = <0x0b1d1000 0x1000>;
+ clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "pll", "aux", "ref";
+ #clock-cells = <0>;
+ #mbox-cells = <1>;
+ };
+ };
+
+ thermal_zones: thermal-zones {
+ cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 5>;
+
+ trips {
+ cpu0_alert: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_crit: trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 6>;
+
+ trips {
+ cpu1_alert: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_crit: trip1 {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 7>;
+
+ trips {
+ cpu2_alert: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2_crit: trip1 {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu3-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 8>;
+
+ trips {
+ cpu3_alert: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_crit: trip1 {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu4567-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 9>;
+
+ trips {
+ cpu4567_alert: trip0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4567_crit: trip1 {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu4567_alert>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 3>;
+
+ trips {
+ gpu_alert0: trip-point0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu_crit: gpu_crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ modem1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 0>;
+
+ trips {
+ modem1_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ modem2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 2>;
+
+ trips {
+ modem2_alert0: trip-point0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ camera-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&tsens 1>;
+
+ trips {
+ cam_alert0: trip-point0 {
+ temperature = <75000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.39.2
The apq8039-t2 is an apq8039 based board paired with a wcn3680b WiFi
chipset.
Co-developed-by: Shawn Guo <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Co-developed-by: Jun Nie <[email protected]>
Signed-off-by: Jun Nie <[email protected]>
Co-developed-by: Benjamin Li <[email protected]>
Signed-off-by: Benjamin Li <[email protected]>
Co-developed-by: James Willcox <[email protected]>
Signed-off-by: James Willcox <[email protected]>
Co-developed-by: Leo Yan <[email protected]>
Signed-off-by: Leo Yan <[email protected]>
Co-developed-by: Joseph Gates <[email protected]>
Signed-off-by: Joseph Gates <[email protected]>
Co-developed-by: Max Chen <[email protected]>
Signed-off-by: Max Chen <[email protected]>
Co-developed-by: Zac Crosby <[email protected]>
Signed-off-by: Zac Crosby <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Bryan O'Donoghue <[email protected]>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/apq8039-t2.dts | 492 ++++++++++++++++++++++++
2 files changed, 493 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/apq8039-t2.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index f6ff4024a60eb..a7feb1609e0c2 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
+dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts
new file mode 100644
index 0000000000000..e75ee34cb014b
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts
@@ -0,0 +1,492 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2023, Linaro Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "msm8939.dtsi"
+#include "msm8939-pm8916.dtsi"
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/sound/apq8016-lpass.h>
+
+/ {
+ model = "Square, Inc. T2 Devkit";
+ compatible = "square,apq8039-t2", "qcom,msm8939";
+
+ qcom,board-id = <0x53 0x54>;
+ qcom,msm-id = <QCOM_ID_APQ8039 0x30000>;
+
+ aliases {
+ mmc0 = &sdhc_1;
+ mmc1 = &sdhc_2;
+ serial0 = &blsp1_uart1;
+ serial1 = &blsp1_uart2;
+ };
+
+ bl: backlight {
+ compatible = "gpio-backlight";
+ pinctrl-0 = <&pinctrl_backlight>;
+ pinctrl-names = "default";
+ gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ vreg_lcd_avdd_reg: lcd-avdd-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd_avdd";
+ regulator-min-microvolt = <5600000>;
+ regulator-max-microvolt = <5600000>;
+ pinctrl-0 = <&pinctrl_lcd_avdd_reg>;
+ pinctrl-names = "default";
+ gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <300>;
+ enable-active-high;
+ };
+
+ vreg_lcd_avee_reg: lcd-avee-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd_avee";
+ regulator-min-microvolt = <5600000>;
+ regulator-max-microvolt = <5600000>;
+ pinctrl-0 = <&pinctrl_lcd_avee_reg>;
+ pinctrl-names = "default";
+ gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <300>;
+ enable-active-high;
+ };
+
+ vreg_lcd_iovcc_reg: lcd-iovcc-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd_iovcc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ pinctrl-0 = <&pinctrl_lcd_iovcc_reg>;
+ pinctrl-names = "default";
+ gpio = <&tlmm 9 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <300>;
+ enable-active-high;
+ };
+};
+
+&blsp_i2c1 {
+ status = "okay";
+};
+
+&blsp_i2c2 {
+ status = "okay";
+};
+
+&blsp_i2c3 {
+ status = "okay";
+
+ typec_pd: usb-pd@38 {
+ compatible = "ti,tps6598x";
+ reg = <0x38>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <107 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "irq";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&typec_irq>;
+
+ typec_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+
+ port {
+ typec_ep: endpoint {
+ remote-endpoint = <&otg_ep>;
+ };
+ };
+ };
+ };
+};
+
+&blsp_i2c5 {
+ status = "okay";
+};
+
+&blsp1_uart1 {
+ status = "okay";
+};
+
+&blsp1_uart1_default {
+ pins = "gpio0", "gpio1";
+};
+
+&blsp1_uart1_sleep {
+ pins = "gpio0", "gpio1";
+};
+
+&blsp1_uart2 {
+ status = "okay";
+};
+
+&lpass {
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&pm8916_gpios {
+ gpio-line-names =
+ "PM_GPIO1", /* WIFI_GPIO1_PRE */
+ "PM_GPIO2", /* WIFI_GPIO2_PRE */
+ "PM_GPIO3",
+ "PM_GPIO4";
+};
+
+&smd_rpm_regulators {
+ vdd_l1_l2_l3-supply = <&pm8916_s3>;
+ vdd_l4_l5_l6-supply = <&pm8916_s4>;
+ vdd_l7-supply = <&pm8916_s4>;
+
+ pm8916_s3: s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8916_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2100000>;
+ };
+
+ /* l1 is fixed to 1225000, but not connected in schematic */
+
+ pm8916_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8916_l4: l4 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8916_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8916_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8916_l7: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8916_l8: l8 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ pm8916_l9: l9 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8916_l10: l10 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8916_l11: l11 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8916_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ pm8916_l13: l13 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pm8916_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8916_l15: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8916_l16: l16 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8916_l17: l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8916_l18: l18 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+};
+
+&sdhc_1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_default_state>;
+ pinctrl-1 = <&sdc1_sleep_state>;
+ status = "okay";
+};
+
+&sound {
+ model = "apq8039-square-sndcard";
+ audio-routing = "AMIC2", "MIC BIAS Internal2";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cdc_pdm_lines_default>;
+ pinctrl-1 = <&cdc_pdm_lines_sleep>;
+
+ internal-codec-playback-dai-link {
+ link-name = "WCD";
+ cpu {
+ sound-dai = <&lpass MI2S_PRIMARY>;
+ };
+ codec {
+ sound-dai = <&lpass_codec 0>, <&wcd_codec 0>;
+ };
+ };
+
+ internal-codec-capture-dai-link {
+ link-name = "WCD-Capture";
+ cpu {
+ sound-dai = <&lpass MI2S_TERTIARY>;
+ };
+ codec {
+ sound-dai = <&lpass_codec 1>, <&wcd_codec 1>;
+ };
+ };
+};
+
+/*
+ * Line names are taken from the schematic of T2, Ver X03.
+ * July 14, 2018. Page 4 in particular.
+ */
+&tlmm {
+ gpio-line-names =
+ "APQ_UART1_TX", /* GPIO_0 */
+ "APQ_UART1_RX",
+ "APQ_I2C1_SDA",
+ "APQ_I2C1_SCL",
+ "APQ_UART2_TX_1V8",
+ "APQ_UART2_RX_1V8",
+ "APQ_I2C2_SDA",
+ "APQ_I2C2_SCL",
+ "NC",
+ "APQ_LCD_IOVCC_EN",
+ "APQ_I2C3_SDA", /* GPIO_10 */
+ "APQ_I2C3_SCL",
+ "TOUCH_RST_1V8_L",
+ "NC",
+ "APQ_I2C4_SDA",
+ "APQ_I2C4_SCL",
+ "APQ_ID5",
+ "USB_DISCONNECT",
+ "APQ_I2C5_SDA",
+ "APQ_I2C5_SCL",
+ "APQ_USBC_SPI_MOSI", /* GPIO_20 */
+ "APQ_USBC_SPI_MISO",
+ "APQ_USBC_SPI_SS_L",
+ "APQ_USBC_SPI_CLK",
+ "APQ_LCD_TE0",
+ "APQ_LCD_RST_L",
+ "NC",
+ "NC",
+ "ACCELEROMETER_INT1",
+ "APQ_CAM_I2C0_SDA",
+ "APQ_CAM_I2C0_SCL", /* GPIO_30 */
+ "ACCELEROMETER_INT2",
+ "NC",
+ "NC",
+ "NC",
+ "APQ_K21_RST_1V8_L",
+ "NC",
+ "APQ_EDL_1V8",
+ "TP145",
+ "BT_SSBI",
+ "NC", /* GPIO_40 */
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "BT_CTRL",
+ "BT_DAT",
+ "PWR_GPIO_IN",
+ "PWR_GPIO_OUT", /* GPIO_50 */
+ "CARD_DET_MLB_L",
+ "HALL_SENSOR",
+ "TP63",
+ "TP64",
+ "TP65",
+ "NC",
+ "NC",
+ "NC",
+ "NC",
+ "NC", /* GPIO_60 */
+ "NC",
+ "APQ_K21_GPIO0_1V8",
+ "CDC_PDM_CLK",
+ "CDC_PDM_SYNC",
+ "CDC_PDM_TX",
+ "CDC_PDM_RX0",
+ "CDC_PDM_RX1",
+ "CDC_PDM_RX2",
+ "APQ_K21_GPIO1_1V8",
+ "NC", /* GPIO_70 */
+ "APQ_HUB_SEL_1V8",
+ "APQ_K21_GPIO2_1V8",
+ "APQ_K21_GPIO3_1V8",
+ "APQ_ID0",
+ "APQ_ID1",
+ "APQ_ID2",
+ "APQ_ID3",
+ "APQ_ID4",
+ "APQ_HUB_SUSP_IND",
+ "BOOT_CONFIG_0", /* GPIO_80 */
+ "BOOT_CONFIG_1",
+ "BOOT_CONFIG_2",
+ "BOOT_CONFIG_3",
+ "NC",
+ "NC",
+ "APQ_LCD_AVDD_EN",
+ "APQ_LCD_AVEE_EN",
+ "TP70",
+ "NC",
+ "APQ_DEBUG0", /* GPIO_90 */
+ "APQ_DEBUG1",
+ "APQ_DEBUG2",
+ "APQ_DEBUG3",
+ "TP165",
+ "NC",
+ "APQ_LNA_PWR_EN",
+ "NC",
+ "APQ_LCD_BL_EN",
+ "NC",
+ "APQ_LCD_ID0", /* GPIO_100 */
+ "APQ_LCD_ID1",
+ "USBC_GPIO5_1V8",
+ "NC",
+ "NC",
+ "NC",
+ "APQ_HUB_RST_1V8_L",
+ "USBC_I2C_IRQ_1V8_L",
+ "SPE_PWR_EN",
+ "NC",
+ "APQ_USB_ID", /* GPIO_110 */
+ "APQ_EXT_BUCK_VSEL",
+ "APQ_USB_ID_OUT",
+ "NC",
+ "PRNT_RST_L",
+ "APQ_CRQ_I2C_RDY_1V8",
+ "TYPEC_RST_1V8_H",
+ "CHG_BACKPWR_EN",
+ "CHG_PROCHOT_L",
+ "NC",
+ "USBC_GPIO7_1V8", /* GPIO_120 */
+ "NC";
+
+ pinctrl_backlight: backlight-state {
+ pins = "gpio98";
+ function = "gpio";
+ };
+
+ pinctrl_lcd_avdd_reg: lcd-avdd-reg-state {
+ pins = "gpio86";
+ function = "gpio";
+ };
+
+ pinctrl_lcd_avee_reg: lcd-avee-reg-state {
+ pins = "gpio87";
+ function = "gpio";
+ };
+
+ pinctrl_lcd_iovcc_reg: lcd-iovcc-reg-state {
+ pins = "gpio9";
+ function = "gpio";
+ };
+
+ pinctrl_lcd_rst: lcd-rst-state {
+ pins = "gpio25";
+ function = "gpio";
+ };
+
+ pinctrl_otg_default: otg-default-state {
+ function = "gpio";
+ pins = "gpio17";
+ output-high;
+ };
+
+ pinctrl_otg_device: otg-device-state {
+ function = "gpio";
+ pins = "gpio17";
+ output-low;
+ };
+
+ pinctrl_otg_host: otg-host-state {
+ function = "gpio";
+ pins = "gpio17";
+ output-low;
+ };
+
+ typec_irq: typec-irq-state {
+ function = "gpio";
+ pins = "gpio107";
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&usb {
+ pinctrl-names = "default", "host", "device";
+ pinctrl-0 = <&pinctrl_otg_default>;
+ pinctrl-1 = <&pinctrl_otg_host>;
+ pinctrl-2 = <&pinctrl_otg_device>;
+ pin-switch-delay-us = <100000>;
+ usb-role-switch;
+ status = "okay";
+
+ port {
+ otg_ep: endpoint {
+ remote-endpoint = <&typec_ep>;
+ };
+ };
+};
+
+&wcd_codec {
+ qcom,hphl-jack-type-normally-open;
+ qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
+ qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
+ status = "okay";
+};
+
+&wcnss {
+ status = "okay";
+};
+
+&wcnss_iris {
+ compatible = "qcom,wcn3680";
+};
--
2.39.2
Add a basic booting DTS for the Sony Xperia M4 Aqua aka "tulip".
Tulip is paired with:
- wcn3660
- smb1360 battery charger
- 720p Truly NT35521 Panel
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Bryan O'Donoghue <[email protected]>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../qcom/msm8939-sony-xperia-kanuti-tulip.dts | 183 ++++++++++++++++++
2 files changed, 184 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index a7feb1609e0c2..f02d5ace0122d 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb
+dtb-$(CONFIG_ARCH_QCOM) += msm8939-sony-xperia-kanuti-tulip.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb
diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts
new file mode 100644
index 0000000000000..951d01674b784
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023, Bryan O'Donoghue.
+ *
+ */
+
+/dts-v1/;
+
+#include "msm8939.dtsi"
+#include "msm8939-pm8916.dtsi"
+#include <dt-bindings/arm/qcom,ids.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+/ {
+ model = "Sony Xperia M4 Aqua";
+ compatible = "sony,kanuti-tulip", "qcom,msm8939";
+
+ qcom,board-id = <QCOM_BOARD_ID_MTP 0>;
+ qcom,msm-id = <QCOM_ID_MSM8939 0>, <QCOM_ID_MSM8939 0x30000>;
+
+ aliases {
+ mmc0 = &sdhc_1; /* SDC1 eMMC slot */
+ mmc1 = &sdhc_2; /* SDC2 SD card slot */
+ serial0 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_id: usb-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&usb_id_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&mdss {
+ status = "okay";
+};
+
+&tlmm {
+ usb_id_default: usb-id-default-state {
+ pins = "gpio110";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+};
+
+&smd_rpm_regulators {
+ vdd_l1_l2_l3-supply = <&pm8916_s3>;
+ vdd_l4_l5_l6-supply = <&pm8916_s4>;
+ vdd_l7-supply = <&pm8916_s4>;
+
+ pm8916_s3: s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ pm8916_s4: s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2100000>;
+ };
+
+ pm8916_l2: l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ pm8916_l4: l4 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ pm8916_l5: l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8916_l6: l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ pm8916_l7: l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8916_l8: l8 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ pm8916_l9: l9 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8916_l10: l10 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8916_l11: l11 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-system-load = <200000>;
+ regulator-allow-set-load;
+ };
+
+ pm8916_l12: l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8916_l13: l13 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ pm8916_l14: l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8916_l15: l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8916_l16: l16 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ pm8916_l17: l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ pm8916_l18: l18 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+};
+
+&sdhc_1 {
+ pinctrl-0 = <&sdc1_default_state>;
+ pinctrl-1 = <&sdc1_sleep_state>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+};
+
+&sdhc_2 {
+ pinctrl-0 = <&sdc2_default_state>;
+ pinctrl-1 = <&sdc2_sleep_state>;
+ pinctrl-names = "default", "sleep";
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usb {
+ extcon = <&usb_id>, <&usb_id>;
+ status = "okay";
+};
+
+&usb_hs_phy {
+ extcon = <&usb_id>;
+};
+
+&wcnss {
+ status = "okay";
+};
+
+&wcnss_iris {
+ compatible = "qcom,wcn3660";
+};
--
2.39.2
On 07/04/2023 20:49, Bryan O'Donoghue wrote:
> V9:
> - Fixes name of tsens
> s4 is not present
> s4->s5
> s5->s6
> s6->s7
> s7->s8
> s8->s9
> I erroneously thought the last sensor needed to be brought in but,
> as has been pointed out to me, the last sensor isn't used, so
> no need to support the reading and reassembly of the non-contiguous
> calibration data - Stephan/Dmitry
>
> - pronto/s//wcnss - Stephan
>
> - tulip dr_mode = "otg" not dr_mode = "device"
> I set the value to device for debug purposes but the role-switch
> works just fine and should be upstream - Stephan
>
> - fixed alphabetisation in pm8939-8916.dtsi - bod
>
> Bootable: https://git.codelinaro.org/bryan.odonoghue/kernel/-/commits/linux-next-23-04-07-msm8939-nocpr
> Previous: https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> git diff linux-next-23-03-27-msm8939-nocpr -- arch/arm64/boot/dts/qcom/*39*
>
> V8:
> - Addresses all of Stephan's comments from v7
> - Moves M4 Aqua display to a separate series
> - Retains s4_p1/p2 done on purpose I believe
> - Adds Konrad's RB as indicated
>
> Bootable: https://git.codelinaro.org/bryan.odonoghue/kernel/-/commits/linux-next-23-03-27-msm8939-nocpr
> Previous: https://lore.kernel.org/lkml/[email protected]/
>
> V7:
> - Addresses all of Konrad's asks on V6
> - Adds Konrad's RB for patch #3
> Bootable: https://git.codelinaro.org/bryan.odonoghue/kernel/-/commits/linux-next-23-02-23-msm8939-nocpr
> Previous: https://lore.kernel.org/lkml/[email protected]/T/
>
> V6:
> - Adds Krzysztof's Ack for Square vendor addition - Krzysztof
> - Incorporates all of Stephan's comments from V5, including
> dropping CPR dummy given the dependent patch [1] has been merged, now.
>
> Bootable: https://git.codelinaro.org/bryan.odonoghue/kernel/-/commits/linux-next-23-02-21-msm8939-nocpr
> Previous: https://lore.kernel.org/lkml/[email protected]/T/
> [1]: https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> V5:
> - Adds Square as a vendor - Krzysztof
>
> - typec_pd: usb-pd@38 - Krzysztof
>
> - Drops gcc clock controller extension. It looks like phy0 actually
> provides a PLL to phy1 for its byte clock. - Bryan, Krzysztof, Stephan
>
> - Adds RB Konrad as indicated - Konrad
>
> - wcnss VDDMX_AO -> VDDMX - Bjorn
>
> - Adds dsi_phy0 as clock-parent to dsi1
>
> - mdss interconnect drops Androidism "register-mem" - Stephan
>
> - cpu power-domain. I've retained the "dummy" cpr reference to
> satiate dtbs_check [1] but renamed &vreg_cpr_stub to remove any confusion
> between now and when we finish off CPR on 8939.
>
> Bootable: https://git.codelinaro.org/bryan.odonoghue/kernel/-/commits/linux-next-23-02-02-msm8939-nocpr
> Previous: https://lore.kernel.org/linux-arm-msm/[email protected]/
> [1] https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> V4:
> - Adds Krzysztof's RB to snoc-mm
> - Re-orders alphabetically missed nodes in previous iteration - Bjorn
> - Adds LK address/size cells comment - Bjorn
>
> - Left _AO for wcnss as downstream reference uses this - Bjorn/Bryan
> - Uses qcom,ids.h and QCOM_ID_SOCNAME for qcom,msm-id - Bjorn
> - Revises comment from "Regulator" to "Power supply" - Bjorn
> - Leaves dummy power-domain reference in cpu defintion as this
>
> - Relabels "cpu" to "CPU" to be more consistent with other dtsi - Bryan
> - Moves msm8939 gcc to its own yaml file to capture 8939 specific form - Bryan
>
> is a required property and the dt checker complains - Stephan/Bryan
> - Removes CPR entries from qfprom - Stephan
> - Left MDSS interconnects. I don't see a bug to fix here - Stephan/Bryan
> - power-domain in MDSS - dropped its not longer required after
> commit a6f033938beb ("dt-bindings: msm: dsi-controller-main: Fix power-domain constraint") - Stephan
> - Adds gcc dsi1pll and dsi1pllbyte to gcc clock list.
> Reviewing the silicon documentation we see dsi0_phy_pll is used to clock
> GCC_BYTE1_CFG_RCGR : SRC_SEL
> Root Source Select
> 000 : cxo
> 001 : dsi0_phy_pll_out_byteclk
> 010 : GPLL0_OUT_AUX
> 011 : gnd
> 100 : gnd
> 101 : gnd
> 110 : gnd
> 111 : reserved - Stephan/Bryan
>
> - pm8916_l16 -> pm8916_l6 in dsi definition, typo - Konrad
> - Moved regulator_set_load location - Konrad
>
> Previous: https://lore.kernel.org/lkml/[email protected]/T/
> Bootable: https://git.linaro.org/people/bryan.odonoghue/kernel.git/log/?h=linux-next-23-01-23-msm8939-nocpr
>
> V3:
> - Happily I don't currently depend on any other series to be merged.
> Bjorn and Chanwoo picked up everything I need to unblock this series. ＼(^o^)／
>
> - Moves xo_board to RPM/PMIC clock gated CXO, not including rpmcc: obvs - Konrad/Bjorn
> - qcom,msm-id = <239 0> - left as in V2 valid according to Sony references - bod
> - cpu-release-addr - as stated below we rely on lk2nd to take the second cluster
> out of reset - bod
> - smem child node update - Konrad
> - Whitespace updates - Konrad
> - gpu no interconnect - Konrad - No bod
> - 19.2 MHz dropped from timer@b020000 - Konrad
> - Added vreg_dummy comment - Konrad
> - sdc_pins grouped - Konrad
> - startup-delay-us = <0> - left as is
> - bias - added no-bias - Konrad
> - :g/msmgpio/s//tlmm/g - Konrad
> - mdss/s//display-controller - Konrad
> - l11 set-load - Korad
>
> - l12 upper voltage raised to 3.3v since this is what the
> downstream kernel says when I boot and interrogate it - bod
>
> - sdhc@address - Discussed with Krzysztof and implemented as discussed
> - snoc-mm fix - Discussed with Krzysztof implemented if:then:else:not
> - dtc -I dtb -fs apq8039-t2.dtb prodcues
> /soc@0/i2c@78b5000: duplicate unit-address
> as does every other component that uses this polymorphic dts node
> - Renamed type-c i2c port manager IC to "typec" - Krzysztof
>
> /smsm/hexagon@1: Missing #address-cells in interrupt provider
> Same output as other upstream and recently upstreamed SoCs
> I left these alone for now
>
> link: https://lore.kernel.org/lkml/[email protected]/T/
> bootable: https://git.linaro.org/people/bryan.odonoghue/kernel.git/log/?h=linux-next-23-01-16-msm8939-nocpr
>
> V2:
> - Sorts core dtsi node list by address followed by alpahbetical sorting
> within address sorted nodes - Bjorn
> - Drops use of 8916-pins - Bjorn
> - Adds msm8939-pm8916.dtsi - Stephan
> - Fixes every dts splat from previous submission minus non-converted
> .txt compat strings [1] and one yaml error in Bjorn's tree not in -next yet
> - I haven't applied Dmitry's change for tsens since that's not been
> picked up yet
> - Picks up a number of suggestions and fixes from Stephan Gerhold and Vincent Knecht
>
> - Depends on
>
> Applied:
> [PATCH v4 0/7] remoteproc: qcom_q6v5_mss: Add MSM8909 and MSM8953
> https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> [PATCH v6 0/5] remoteproc: qcom: Add support for pronto-v3
> https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> [PATCH v6 00/18] mdss-dsi-ctrl binding and dts fixes
> https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> Awaiting application:
> https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> - Previous
> https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> - Bootable tree
> https://git.linaro.org/people/bryan.odonoghue/kernel.git/log/?h=linux-next-23-01-03-msm8939-no-cpr
>
> - [1] DTC_CHK arch/arm64/boot/dts/qcom/apq8039-t2.dtb
>
> Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
> qcom/apq8039-t2.dtb: idle-states: cpu-sleep-0:compatible:0: 'qcom,idle-state-spc' is not one of ['arm,idle-state', 'riscv,idle-state']
> From schema: Documentation/devicetree/bindings/cpu/idle-states.yaml
> qcom/apq8039-t2.dtb: idle-states: cpu-sleep-0:compatible: ['qcom,idle-state-spc', 'arm,idle-state'] is too long
> From schema: Documentation/devicetree/bindings/cpu/idle-states.yaml
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /cpus/idle-states/cpu-sleep-0: failed to match any schema with compatible: ['qcom,idle-state-spc', 'arm,idle-state']
>
> Documentation/devicetree/bindings/iommu/qcom,iommu.txt
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/iommu@1ef0000: failed to match any schema with compatible: ['qcom,msm8916-iommu', 'qcom,msm-iommu-v1']
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/iommu@1ef0000/iommu-ctx@4000: failed to match any schema with compatible: ['qcom,msm-iommu-v1-ns']
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/iommu@1ef0000/iommu-ctx@5000: failed to match any schema with compatible: ['qcom,msm-iommu-v1-sec']
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/iommu@1f08000: failed to match any schema with compatible: ['qcom,msm8916-iommu', 'qcom,msm-iommu-v1']
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/iommu@1f08000/iommu-ctx@1000: failed to match any schema with compatible: ['qcom,msm-iommu-v1-ns']
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/iommu@1f08000/iommu-ctx@2000: failed to match any schema with compatible: ['qcom,msm-iommu-v1-ns']
>
> arch/arm64/boot/dts/qcom/pm8916.dtsi f5d7bca55425c8
> qcom/apq8039-t2.dtb: pmic@0: 'extcon@1300' does not match any of the regexes: '(.*)?(wled|leds)@[0-9a-f]+$', '^adc-tm@[0-9a-f]+$', '^adc@[0-9a-f]+$', '^audio-codec@[0-9a-f]+$', '^charger@[0-9a-f]+$', '^mpps@[0-9a-f]+$', '^rtc@[0-9a-f]+$', '^temp-alarm@[0-9a-f]+$', '^usb-detect@[0-9a-f]+$', '^usb-vbus-regulator@[0-9a-f]+$', '^vibrator@[0-9a-f]+$', 'gpio@[0-9a-f]+$', 'pinctrl-[0-9]+', 'pon@[0-9a-f]+$'
> From schema: Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
>
> Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-analog.txt
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/spmi@200f000/pmic@1/audio-codec@f000: failed to match any schema with compatible: ['qcom,pm8916-wcd-analog-codec']
>
> yaml documentation error not yet in -next
> arm64/boot/dts/qcom/apq8039-t2.dtb: remoteproc@4080000: qcom,halt-regs:0: [33] is too short
> From schema: Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml
>
> Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/usb@78d9000: failed to match any schema with compatible: ['qcom,ci-hdrc']
>
> Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt: compatible = "qcom,kpss-acc-v2";
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b088000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b098000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b0a8000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b0b8000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b188000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b198000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b1a8000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
> arch/arm64/boot/dts/qcom/apq8039-t2.dtb:0:0: /soc@0/clock-controller@b1b8000: failed to match any schema with compatible: ['qcom,kpss-acc-v2']
>
> V1:
> This series adds in MSM8939 SoC support with two supported devices.
>
> - CPU
> MSM8939 is a non-PSCI compliant device. As such in the downstreaming
> shipped image custom code is used to bring non-boot cores out of reset.
>
> This drop specifies the boot-method as spin-table instead and is
> completely standard. To accomplish this, we rely on lk2nd.
>
> https://github.com/msm8916-mainline/lk2nd/pull/142
>
> - Serial
> - i2c
> - USB
> - eMMC
> - MDP/DSI
> - WiFi
> - Bluetooth
>
> What's not included
>
> - CPR
> We have CPR working in a 4.19 kernel quite well but for now it feels like
> putting the cart before the horse to gate the SoC and boards on CPR.
>
> - Venus
> I've been told this works but I haven't tried it myself and right now
> consider it maybe working but probably not 100%.
>
> - Sound
> We have a copy-exactly from the 4.19 kernel here in the DTS.
> I haven't run the sound through any sort of reasonable test.
> Vincent Knecht has some PostmarketOS kernels which use a 5.17 version of
> this DTS to get sound up so, I think sound is in good shape.
>
> - CAMSS
> There are slight differences between msm8916 and msm8939 for CAMSS. It
> doesn't feel like tons of work but, right now it is work we haven't even
> started.
>
> - Devices
> I've booted on the Square device obviously and this is my regular
> hardware for upstream development. I've also booted on the Sony Xperia M4
> Aqua including mutli-core bring-up, WiFi and ADB.
>
> Dependencies for this drop:
>
> qcom-cpufreq-nvmem: Add msm8939 with some fixups
> link: https://lore.kernel.org/linux-arm-msm/[email protected]/T/#t
>
> Fix apq8016 compat string
> link: https://lore.kernel.org/linux-arm-msm/[email protected]/T/#t
>
> dt-bindings: soc: qcom: smd-rpm: Fix missing MSM8936 compatible
> link: https://lore.kernel.org/linux-arm-msm/[email protected]/T/#u
>
> Bootable tree here:
> https://git.linaro.org/people/bryan.odonoghue/kernel.git/log/?h=v5.18-rc2%2bapq8039-without-cpr
>
> Bryan O'Donoghue (3):
> arm64: dts: qcom: Add msm8939 SoC
> arm64: dts: qcom: Add Square apq8039-t2 board
> arm64: dts: qcom: Add msm8939 Sony Xperia M4 Aqua
>
> Stephan Gerhold (1):
> arm64: dts: qcom: Add msm8939-pm8916.dtsi include
>
> arch/arm64/boot/dts/qcom/Makefile | 2 +
> arch/arm64/boot/dts/qcom/apq8039-t2.dts | 492 ++++
> arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi | 82 +
> .../qcom/msm8939-sony-xperia-kanuti-tulip.dts | 184 ++
> arch/arm64/boot/dts/qcom/msm8939.dtsi | 2452 +++++++++++++++++
> 5 files changed, 3212 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/apq8039-t2.dts
> create mode 100644 arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts
> create mode 100644 arch/arm64/boot/dts/qcom/msm8939.dtsi
>
ping
On Fri, 7 Apr 2023 20:49:00 +0100, Bryan O'Donoghue wrote:
> V9:
> - Fixes name of tsens
> s4 is not present
> s4->s5
> s5->s6
> s6->s7
> s7->s8
> s8->s9
> I erroneously thought the last sensor needed to be brought in but,
> as has been pointed out to me, the last sensor isn't used, so
> no need to support the reading and reassembly of the non-contiguous
> calibration data - Stephan/Dmitry
>
> [...]
Applied, thanks!
[1/5] dt-bindings: vendor-prefixes: Add Square
commit: 8051c8b83ac076ab7f4fc80cff5e7f8cc3b1eefb
[2/5] arm64: dts: qcom: Add msm8939 SoC
commit: 61550c6c156c3715baf54ab2cdd678c8c35b3803
[3/5] arm64: dts: qcom: Add msm8939-pm8916.dtsi include
commit: 1e6dfe47ba020a192d743c7c820b469fd7253813
[4/5] arm64: dts: qcom: Add Square apq8039-t2 board
commit: 273a3dc13eb746c7b7abe7ea682811a8dacc89d6
[5/5] arm64: dts: qcom: Add msm8939 Sony Xperia M4 Aqua
commit: f1134f738fad68c51a44216ab0f68a0f086a1a5e
Best regards,
--
Bjorn Andersson <[email protected]>