Changes in v2:
- Squashed the addition of mediatek,mt6795-gce.h header with the
commit adding the MT6795 GCE compatible.
This series further enhances the support for the MT6795 Helio X10 SoC
and the Sony Xperia M5 smartphone.
In particular, for the SoC support, this adds:
- Frequency Hopping support
- I2C controllers
- Power domains
- IOMMU support and LARBs
- GCE/CMDQ Mailbox
- VDECSYS and VENCSYS clocks
- MMSYS support
...and, on the Xperia M5 smartphone, this adds:
- Frequency Hopping with Spread Spectrum for MAINPLL, MPLL, MSDCPLL
- Touchscreen support (Synaptics S2726, fw id: 1898977, RMI4 protocol)
- Accelerometer
- Magnetometer
- Proximity sensor
- NFC support
...all of which was successfully tested on the Xperia M5 smartphone.
This series depends on [1] for the MMSYS support.
Plan for step 3 is to push upstream full display support, which does
already work on my custom tree ;-)
[1]: https://lore.kernel.org/all/[email protected]/
Cheers!
AngeloGioacchino Del Regno (17):
arm64: dts: mediatek: mt6795: Add Frequency Hopping Controller node
arm64: dts: mediatek: mt6795: Add apmixedsys syscon node
arm64: dts: mediatek: mt6795: xperia-m5: Enable Frequency Hopping
dt-bindings: i2c: i2c-mt65xx: Add compatible for MT6795 Helio X10
arm64: dts: mediatek: mt6795: Add nodes for I2C controllers
arm64: dts: mediatek: mt6795: Add SoC power domains
dt-bindings: mailbox: mediatek,gce-mailbox: Add support for MT6795
arm64: dts: mediatek: mt6795: Add support for the CMDQ/GCE mailbox
arm64: dts: mediatek: mt6795: Add MMSYS node for multimedia clocks
arm64: dts: mediatek: mt6795: Add VDECSYS and VENCSYS clocks
arm64: dts: mediatek: mt6795: Add support for IOMMU and LARBs
arm64: dts: mediatek: mt6795-xperia-m5: Enable I2C 0-3 busses
arm64: dts: mediatek: mt6795-xperia-m5: Add Synaptics RMI4 Touchscreen
arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMA255 Accelerometer
arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMM050 Magnetometer
arm64: dts: mediatek: mt6795-xperia-m5: Add Sensortek STK3310
Proximity
arm64: dts: mediatek: mt6795-xperia-m5: Add NXP PN547 NFC on I2C3
.../devicetree/bindings/i2c/i2c-mt65xx.yaml | 4 +
.../mailbox/mediatek,gce-mailbox.yaml | 20 +-
.../dts/mediatek/mt6795-sony-xperia-m5.dts | 166 ++++++++++++
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 245 ++++++++++++++++++
include/dt-bindings/gce/mediatek,mt6795-gce.h | 123 +++++++++
5 files changed, 550 insertions(+), 8 deletions(-)
create mode 100644 include/dt-bindings/gce/mediatek,mt6795-gce.h
--
2.40.0
Add support for the NXP PN547 NFC chip found on this smartphone and
configure its pins.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
.../dts/mediatek/mt6795-sony-xperia-m5.dts | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
index bff0760cc1c8..8f00232e7348 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
@@ -5,6 +5,7 @@
*/
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "mt6795.dtsi"
/ {
@@ -112,6 +113,16 @@ magnetometer@0x12 {
reg = <0x12>;
};
+ pn547: nfc@28 {
+ compatible = "nxp,pn544-i2c";
+ reg = <0x28>;
+ interrupts-extended = <&pio 3 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&nfc_pins>;
+ enable-gpios = <&pio 149 GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&pio 94 GPIO_ACTIVE_HIGH>;
+ };
+
proximity@48 {
compatible = "sensortek,stk3310";
reg = <0x48>;
@@ -122,6 +133,19 @@ proximity@48 {
};
&pio {
+ nfc_pins: nfc-pins {
+ pins-irq {
+ pinmux = <PINMUX_GPIO3__FUNC_GPIO3>;
+ bias-pull-down;
+ input-enable;
+ };
+
+ pins-fw-ven {
+ pinmux = <PINMUX_GPIO94__FUNC_GPIO94>,
+ <PINMUX_GPIO149__FUNC_GPIO149>;
+ };
+ };
+
ts_pins: touchscreen-pins {
pins-irq {
pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
--
2.40.0
This smartphone features a Bosch BMM050 Magnetometer on I2C3: enable
it with the BMM150 binding, as that driver supports BMM050 as well.
For this sensor, there is no interrupt pin;
readings were validated in sysfs.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
index 54a1f7f306f7..bda14c74a8af 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
@@ -106,6 +106,11 @@ accelerometer@0x10 {
pinctrl-names = "default";
pinctrl-0 = <&accel_pins>;
};
+
+ magnetometer@0x12 {
+ compatible = "bosch,bmm150";
+ reg = <0x12>;
+ };
};
&pio {
--
2.40.0
Add the STK3310 Proximity sensor and its pins.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
.../boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
index bda14c74a8af..bff0760cc1c8 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
@@ -111,6 +111,14 @@ magnetometer@0x12 {
compatible = "bosch,bmm150";
reg = <0x12>;
};
+
+ proximity@48 {
+ compatible = "sensortek,stk3310";
+ reg = <0x48>;
+ interrupts-extended = <&pio 8 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&proximity_pins>;
+ };
};
&pio {
@@ -127,6 +135,14 @@ pins-rst {
};
};
+ proximity_pins: proximity-pins {
+ pins-irq {
+ pinmux = <PINMUX_GPIO8__FUNC_GPIO8>;
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
accel_pins: accelerometer-pins {
pins-irq {
pinmux = <PINMUX_GPIO12__FUNC_GPIO12>;
--
2.40.0
Add the BMA255 Accelerometer on I2C3 and its pin definitions.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
.../boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
index edab90f06a24..54a1f7f306f7 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
@@ -99,6 +99,13 @@ &i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
status = "okay";
+
+ accelerometer@0x10 {
+ compatible = "bosch,bma255";
+ reg = <0x10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&accel_pins>;
+ };
};
&pio {
@@ -115,6 +122,14 @@ pins-rst {
};
};
+ accel_pins: accelerometer-pins {
+ pins-irq {
+ pinmux = <PINMUX_GPIO12__FUNC_GPIO12>;
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
i2c0_pins: i2c0-pins {
pins-bus {
pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
--
2.40.0
Properly configure and enable the three i2c controllers that have
devices attached on the Sony Xperia M5 smartphone.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
.../dts/mediatek/mt6795-sony-xperia-m5.dts | 64 +++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
index 52ce3284a46f..6df1c848e2d5 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
@@ -55,7 +55,71 @@ &fhctl {
status = "okay";
};
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins>;
+ status = "okay";
+};
+
&pio {
+ i2c0_pins: i2c0-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
+ <PINMUX_GPIO46__FUNC_SCL0>;
+ input-enable;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO125__FUNC_SDA1>,
+ <PINMUX_GPIO126__FUNC_SCL1>;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO43__FUNC_SDA2>,
+ <PINMUX_GPIO44__FUNC_SCL2>;
+ bias-disable;
+ };
+ };
+
+ i2c3_pins: i2c3-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO136__FUNC_SDA3>,
+ <PINMUX_GPIO137__FUNC_SCL3>;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins: i2c4-pins {
+ pins-bus {
+ pinmux = <PINMUX_GPIO100__FUNC_SDA4>,
+ <PINMUX_GPIO101__FUNC_SCL4>;
+ bias-disable;
+ };
+ };
+
uart0_pins: uart0-pins {
pins-rx {
pinmux = <PINMUX_GPIO113__FUNC_URXD0>;
--
2.40.0
Add nodes for the multimedia IOMMU and its LARBs: this includes all but
the MJC LARB, which cannot currently be used and will be added later.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 59 ++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index a8b2c4517e79..a580ddb51a0e 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -390,6 +390,17 @@ systimer: timer@10200670 {
clock-names = "clk13m";
};
+ iommu: iommu@10205000 {
+ compatible = "mediatek,mt6795-m4u";
+ reg = <0 0x10205000 0 0x1000>;
+ clocks = <&infracfg CLK_INFRA_M4U>;
+ clock-names = "bclk";
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>;
+ mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>;
+ power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
+ #iommu-cells = <1>;
+ };
+
apmixedsys: syscon@10209000 {
compatible = "mediatek,mt6795-apmixedsys", "syscon";
reg = <0 0x10209000 0 0x1000>;
@@ -648,16 +659,64 @@ mmsys: syscon@14000000 {
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
+ larb0: larb@14021000 {
+ compatible = "mediatek,mt6795-smi-larb";
+ reg = <0 0x14021000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <0>;
+ power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
+ };
+
+ smi_common: smi@14022000 {
+ compatible = "mediatek,mt6795-smi-common";
+ reg = <0 0x14022000 0 0x1000>;
+ power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
+ clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>;
+ clock-names = "apb", "smi";
+ };
+
+ larb2: larb@15001000 {
+ compatible = "mediatek,mt6795-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>;
+ clock-names = "apb", "smi";
+ mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <2>;
+ power-domains = <&spm MT6795_POWER_DOMAIN_ISP>;
+ };
+
vdecsys: clock-controller@16000000 {
compatible = "mediatek,mt6795-vdecsys";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb1: larb@16010000 {
+ compatible = "mediatek,mt6795-smi-larb";
+ reg = <0 0x16010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <1>;
+ clocks = <&vdecsys CLK_VDEC_CKEN>, <&vdecsys CLK_VDEC_LARB_CKEN>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT6795_POWER_DOMAIN_VDEC>;
+ };
+
vencsys: clock-controller@18000000 {
compatible = "mediatek,mt6795-vencsys";
reg = <0 0x18000000 0 0x1000>;
#clock-cells = <1>;
};
+
+ larb3: larb@18001000 {
+ compatible = "mediatek,mt6795-smi-larb";
+ reg = <0 0x18001000 0 0x1000>;
+ clocks = <&vencsys CLK_VENC_VENC>, <&vencsys CLK_VENC_LARB>;
+ clock-names = "apb", "smi";
+ mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <3>;
+ power-domains = <&spm MT6795_POWER_DOMAIN_VENC>;
+ };
};
};
--
2.40.0
Add all four I2C controller nodes but keep them in disabled state as
usage is board-dependant.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 60 ++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 26d640e1bfb6..ceb6fc948d8a 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -445,6 +445,66 @@ uart3: serial@11005000 {
status = "disabled";
};
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
+ reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
+ reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
+ reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@11010000 {
+ compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
+ reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C3>, <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@11011000 {
+ compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
+ reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C4>, <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
mmc0: mmc@11230000 {
compatible = "mediatek,mt6795-mmc";
reg = <0 0x11230000 0 0x1000>;
--
2.40.0
Add the RMI4 Touchscreen on I2C2 and its pin definitions.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
.../dts/mediatek/mt6795-sony-xperia-m5.dts | 35 +++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
index 6df1c848e2d5..edab90f06a24 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
@@ -71,6 +71,28 @@ &i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
+
+ touchscreen@20 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts-extended = <&pio 6 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_pins>;
+ syna,startup-delay-ms = <160>;
+ syna,reset-delay-ms = <90>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>;
+ };
+
+ rmi4-f12@12 {
+ reg = <0x12>;
+ syna,sensor-type = <1>;
+ };
+ };
};
&i2c3 {
@@ -80,6 +102,19 @@ &i2c3 {
};
&pio {
+ ts_pins: touchscreen-pins {
+ pins-irq {
+ pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
+ bias-pull-up;
+ input-enable;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO102__FUNC_GPIO102>;
+ output-high;
+ };
+ };
+
i2c0_pins: i2c0-pins {
pins-bus {
pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
--
2.40.0
In prepration for adding the IOMMUs and LARBs of this SoC, add the
VDECSYS and VENCSYS clock controller nodes, providing clocks for the
vcodec stateful decoder and stateful decoder hardware.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index b721971d4e5e..a8b2c4517e79 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -647,5 +647,17 @@ mmsys: syscon@14000000 {
<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
+
+ vdecsys: clock-controller@16000000 {
+ compatible = "mediatek,mt6795-vdecsys";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: clock-controller@18000000 {
+ compatible = "mediatek,mt6795-vencsys";
+ reg = <0 0x18000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
};
--
2.40.0
Add the MultiMedia System node, providing clocks for the multimedia
hardware blocks and their IOMMU/SMIs.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 0f903e8fe70f..b721971d4e5e 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -634,5 +634,18 @@ mmc3: mmc@11260000 {
clock-names = "source", "hclk";
status = "disabled";
};
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt6795-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ power-domains = <&spm MT6795_POWER_DOMAIN_MM>;
+ assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
+ assigned-clock-rates = <400000000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
+ };
};
};
--
2.40.0
In preparation for adding multimedia blocks, add the CMDQ/GCE mailbox.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index d63efb32e6bb..0f903e8fe70f 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
+#include <dt-bindings/gce/mediatek,mt6795-gce.h>
#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
#include <dt-bindings/power/mt6795-power.h>
#include <dt-bindings/reset/mediatek,mt6795-resets.h>
@@ -401,6 +402,15 @@ fhctl: clock-controller@10209f00 {
status = "disabled";
};
+ gce: mailbox@10212000 {
+ compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_GCE>;
+ clock-names = "gce";
+ #mbox-cells = <2>;
+ };
+
gic: interrupt-controller@10221000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.40.0
Add a compatible string for the MT6795 Helio X10 SoC using MT8173
binding and add a header for the MT6795's GCE mailbox.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
P.S.: Krzysztof, should have I removed your Reviewed-by tag here, or
was retaining it the right choice?
.../mailbox/mediatek,gce-mailbox.yaml | 20 +--
include/dt-bindings/gce/mediatek,mt6795-gce.h | 123 ++++++++++++++++++
2 files changed, 135 insertions(+), 8 deletions(-)
create mode 100644 include/dt-bindings/gce/mediatek,mt6795-gce.h
diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
index d383b2ab3ce8..cef9d7601398 100644
--- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
@@ -16,14 +16,18 @@ description:
properties:
compatible:
- enum:
- - mediatek,mt6779-gce
- - mediatek,mt8173-gce
- - mediatek,mt8183-gce
- - mediatek,mt8186-gce
- - mediatek,mt8188-gce
- - mediatek,mt8192-gce
- - mediatek,mt8195-gce
+ oneOf:
+ - enum:
+ - mediatek,mt6779-gce
+ - mediatek,mt8173-gce
+ - mediatek,mt8183-gce
+ - mediatek,mt8186-gce
+ - mediatek,mt8188-gce
+ - mediatek,mt8192-gce
+ - mediatek,mt8195-gce
+ - items:
+ - const: mediatek,mt6795-gce
+ - const: mediatek,mt8173-gce
"#mbox-cells":
const: 2
diff --git a/include/dt-bindings/gce/mediatek,mt6795-gce.h b/include/dt-bindings/gce/mediatek,mt6795-gce.h
new file mode 100644
index 000000000000..97d5ba2d2b44
--- /dev/null
+++ b/include/dt-bindings/gce/mediatek,mt6795-gce.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023 Collabora Ltd.
+ * Author: AngeloGioacchino Del Regno <[email protected]>
+ */
+#ifndef _DT_BINDINGS_GCE_MT6795_H
+#define _DT_BINDINGS_GCE_MT6795_H
+
+/* GCE HW thread priority */
+#define CMDQ_THR_PRIO_LOWEST 0
+#define CMDQ_THR_PRIO_NORMAL 1
+#define CMDQ_THR_PRIO_NORMAL_2 2
+#define CMDQ_THR_PRIO_MEDIUM 3
+#define CMDQ_THR_PRIO_MEDIUM_2 4
+#define CMDQ_THR_PRIO_HIGH 5
+#define CMDQ_THR_PRIO_HIGHER 6
+#define CMDQ_THR_PRIO_HIGHEST 7
+
+/* GCE SUBSYS */
+#define SUBSYS_1300XXXX 0
+#define SUBSYS_1400XXXX 1
+#define SUBSYS_1401XXXX 2
+#define SUBSYS_1402XXXX 3
+#define SUBSYS_1500XXXX 4
+#define SUBSYS_1600XXXX 5
+#define SUBSYS_1700XXXX 6
+#define SUBSYS_1800XXXX 7
+#define SUBSYS_1000XXXX 8
+#define SUBSYS_1001XXXX 9
+#define SUBSYS_1002XXXX 10
+#define SUBSYS_1003XXXX 11
+#define SUBSYS_1004XXXX 12
+#define SUBSYS_1005XXXX 13
+#define SUBSYS_1020XXXX 14
+#define SUBSYS_1021XXXX 15
+#define SUBSYS_1120XXXX 16
+#define SUBSYS_1121XXXX 17
+#define SUBSYS_1122XXXX 18
+#define SUBSYS_1123XXXX 19
+#define SUBSYS_1124XXXX 20
+#define SUBSYS_1125XXXX 21
+#define SUBSYS_1126XXXX 22
+
+/* GCE HW EVENT */
+#define CMDQ_EVENT_MDP_RDMA0_SOF 0
+#define CMDQ_EVENT_MDP_RDMA1_SOF 1
+#define CMDQ_EVENT_MDP_DSI0_TE_SOF 2
+#define CMDQ_EVENT_MDP_DSI1_TE_SOF 3
+#define CMDQ_EVENT_MDP_MVW_SOF 4
+#define CMDQ_EVENT_MDP_TDSHP0_SOF 5
+#define CMDQ_EVENT_MDP_TDSHP1_SOF 6
+#define CMDQ_EVENT_MDP_WDMA_SOF 7
+#define CMDQ_EVENT_MDP_WROT0_SOF 8
+#define CMDQ_EVENT_MDP_WROT1_SOF 9
+#define CMDQ_EVENT_MDP_CROP_SOF 10
+#define CMDQ_EVENT_DISP_OVL0_SOF 11
+#define CMDQ_EVENT_DISP_OVL1_SOF 12
+#define CMDQ_EVENT_DISP_RDMA0_SOF 13
+#define CMDQ_EVENT_DISP_RDMA1_SOF 14
+#define CMDQ_EVENT_DISP_RDMA2_SOF 15
+#define CMDQ_EVENT_DISP_WDMA0_SOF 16
+#define CMDQ_EVENT_DISP_WDMA1_SOF 17
+#define CMDQ_EVENT_DISP_COLOR0_SOF 18
+#define CMDQ_EVENT_DISP_COLOR1_SOF 19
+#define CMDQ_EVENT_DISP_AAL_SOF 20
+#define CMDQ_EVENT_DISP_GAMMA_SOF 21
+#define CMDQ_EVENT_DISP_UFOE_SOF 22
+#define CMDQ_EVENT_DISP_PWM0_SOF 23
+#define CMDQ_EVENT_DISP_PWM1_SOF 24
+#define CMDQ_EVENT_DISP_OD_SOF 25
+#define CMDQ_EVENT_MDP_RDMA0_EOF 26
+#define CMDQ_EVENT_MDP_RDMA1_EOF 27
+#define CMDQ_EVENT_MDP_RSZ0_EOF 28
+#define CMDQ_EVENT_MDP_RSZ1_EOF 29
+#define CMDQ_EVENT_MDP_RSZ2_EOF 30
+#define CMDQ_EVENT_MDP_TDSHP0_EOF 31
+#define CMDQ_EVENT_MDP_TDSHP1_EOF 32
+#define CMDQ_EVENT_MDP_WDMA_EOF 33
+#define CMDQ_EVENT_MDP_WROT0_WRITE_EOF 34
+#define CMDQ_EVENT_MDP_WROT0_READ_EOF 35
+#define CMDQ_EVENT_MDP_WROT1_WRITE_EOF 36
+#define CMDQ_EVENT_MDP_WROT1_READ_EOF 37
+#define CMDQ_EVENT_MDP_CROP_EOF 38
+#define CMDQ_EVENT_DISP_OVL0_EOF 39
+#define CMDQ_EVENT_DISP_OVL1_EOF 40
+#define CMDQ_EVENT_DISP_RDMA0_EOF 41
+#define CMDQ_EVENT_DISP_RDMA1_EOF 42
+#define CMDQ_EVENT_DISP_RDMA2_EOF 43
+#define CMDQ_EVENT_DISP_WDMA0_EOF 44
+#define CMDQ_EVENT_DISP_WDMA1_EOF 45
+#define CMDQ_EVENT_DISP_COLOR0_EOF 46
+#define CMDQ_EVENT_DISP_COLOR1_EOF 47
+#define CMDQ_EVENT_DISP_AAL_EOF 48
+#define CMDQ_EVENT_DISP_GAMMA_EOF 49
+#define CMDQ_EVENT_DISP_UFOE_EOF 50
+#define CMDQ_EVENT_DISP_DPI0_EOF 51
+#define CMDQ_EVENT_MUTEX0_STREAM_EOF 52
+#define CMDQ_EVENT_MUTEX1_STREAM_EOF 53
+#define CMDQ_EVENT_MUTEX2_STREAM_EOF 54
+#define CMDQ_EVENT_MUTEX3_STREAM_EOF 55
+#define CMDQ_EVENT_MUTEX4_STREAM_EOF 56
+#define CMDQ_EVENT_MUTEX5_STREAM_EOF 57
+#define CMDQ_EVENT_MUTEX6_STREAM_EOF 58
+#define CMDQ_EVENT_MUTEX7_STREAM_EOF 59
+#define CMDQ_EVENT_MUTEX8_STREAM_EOF 60
+#define CMDQ_EVENT_MUTEX9_STREAM_EOF 61
+#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 62
+#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 63
+#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 64
+#define CMDQ_EVENT_ISP_PASS2_2_EOF 129
+#define CMDQ_EVENT_ISP_PASS2_1_EOF 130
+#define CMDQ_EVENT_ISP_PASS2_0_EOF 131
+#define CMDQ_EVENT_ISP_PASS1_1_EOF 132
+#define CMDQ_EVENT_ISP_PASS1_0_EOF 133
+#define CMDQ_EVENT_CAMSV_2_PASS1_EOF 134
+#define CMDQ_EVENT_CAMSV_1_PASS1_EOF 135
+#define CMDQ_EVENT_SENINF_CAM1_2_3_FIFO_FULL 136
+#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 137
+#define CMDQ_EVENT_JPGENC_PASS2_EOF 257
+#define CMDQ_EVENT_JPGENC_PASS1_EOF 258
+#define CMDQ_EVENT_JPGDEC_EOF 259
+
+#endif
--
2.40.0
The MT6795 SoC uses the same I2C controller parameters as MT8173:
add a new compatible string for it.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
index 72ae2e01cf22..685da4df688d 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
@@ -45,6 +45,10 @@ properties:
- enum:
- mediatek,mt8365-i2c
- const: mediatek,mt8168-i2c
+ - items:
+ - enum:
+ - mediatek,mt6795-i2c
+ - const: mediatek,mt8173-i2c
- items:
- enum:
- mediatek,mt8195-i2c
--
2.40.0
Add power domain tree for various hardware blocks on MT6795.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 79 ++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index ceb6fc948d8a..d63efb32e6bb 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mediatek,mt6795-clk.h>
#include <dt-bindings/pinctrl/mt6795-pinfunc.h>
+#include <dt-bindings/power/mt6795-power.h>
#include <dt-bindings/reset/mediatek,mt6795-resets.h>
/ {
@@ -264,6 +265,84 @@ pericfg: syscon@10003000 {
#reset-cells = <1>;
};
+ scpsys: syscon@10006000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+ #power-domain-cells = <1>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt6795-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domains of the SoC */
+ power-domain@MT6795_POWER_DOMAIN_VDEC {
+ reg = <MT6795_POWER_DOMAIN_VDEC>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ };
+ power-domain@MT6795_POWER_DOMAIN_VENC {
+ reg = <MT6795_POWER_DOMAIN_VENC>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_VENC_SEL>;
+ clock-names = "mm", "venc";
+ #power-domain-cells = <0>;
+ };
+ power-domain@MT6795_POWER_DOMAIN_ISP {
+ reg = <MT6795_POWER_DOMAIN_ISP>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT6795_POWER_DOMAIN_MM {
+ reg = <MT6795_POWER_DOMAIN_MM>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+
+ power-domain@MT6795_POWER_DOMAIN_MJC {
+ reg = <MT6795_POWER_DOMAIN_MJC>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_MJC_SEL>;
+ clock-names = "mm", "mjc";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT6795_POWER_DOMAIN_AUDIO {
+ reg = <MT6795_POWER_DOMAIN_AUDIO>;
+ #power-domain-cells = <0>;
+ };
+
+ mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC {
+ reg = <MT6795_POWER_DOMAIN_MFG_ASYNC>;
+ clocks = <&clk26m>;
+ clock-names = "mfg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT6795_POWER_DOMAIN_MFG_2D {
+ reg = <MT6795_POWER_DOMAIN_MFG_2D>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT6795_POWER_DOMAIN_MFG {
+ reg = <MT6795_POWER_DOMAIN_MFG>;
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+ };
+ };
+ };
+ };
+
pio: pinctrl@10005000 {
compatible = "mediatek,mt6795-pinctrl";
reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
--
2.40.0
Add the APMIXEDSYS node, providing a syscon to the APMIXED iospace and
also providing PLLs.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 4d2119751572..26d640e1bfb6 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -310,6 +310,12 @@ systimer: timer@10200670 {
clock-names = "clk13m";
};
+ apmixedsys: syscon@10209000 {
+ compatible = "mediatek,mt6795-apmixedsys", "syscon";
+ reg = <0 0x10209000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
fhctl: clock-controller@10209f00 {
compatible = "mediatek,mt6795-fhctl";
reg = <0 0x10209f00 0 0x100>;
--
2.40.0
Enable FHCTL with Spread Spectrum for MAINPLL, MPLL and MSDCPLL
as found on the downstream kernel for this smartphone.
Which one to enable, and at what SSC percentage, was found by
dumping the debugging data from a running downstream kernel and
checking the downstream code.
/proc/freqhopping # cat status
FH status:
===============================================
id == fh_status == pll_status == setting_id == curr_freq == user_defined
0 0 1 0 1599000 0
1 0 1 0 1716000 0
2 1 1 2 1092000 0
3 1 1 2 2912000 0
4 1 0 2 1600000 0
5 0 0 0 0 0
6 0 1 0 1518002 0
7 0 0 0 0 0
8 0 0 0 0 0
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
index d3415527d389..52ce3284a46f 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts
@@ -48,6 +48,13 @@ bootloader-region@46000000 {
};
};
+&fhctl {
+ clocks = <&apmixedsys CLK_APMIXED_MAINPLL>, <&apmixedsys CLK_APMIXED_MPLL>,
+ <&apmixedsys CLK_APMIXED_MSDCPLL>;
+ mediatek,hopping-ssc-percent = <8>, <5>, <8>;
+ status = "okay";
+};
+
&pio {
uart0_pins: uart0-pins {
pins-rx {
--
2.40.0
On 27/03/2023 10:36, AngeloGioacchino Del Regno wrote:
> Add the APMIXEDSYS node, providing a syscon to the APMIXED iospace and
> also providing PLLs.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt6795.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
> index 4d2119751572..26d640e1bfb6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
> @@ -310,6 +310,12 @@ systimer: timer@10200670 {
> clock-names = "clk13m";
> };
>
> + apmixedsys: syscon@10209000 {
> + compatible = "mediatek,mt6795-apmixedsys", "syscon";
Looks good although we have the compatible twice, in
bindings/clock/mediatek,apmixedsys.yaml and
bindings/clock/mediatek,mt6795-sys-clock.yaml
So we should see if we can merge both.
Matthias
> + reg = <0 0x10209000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> fhctl: clock-controller@10209f00 {
> compatible = "mediatek,mt6795-fhctl";
> reg = <0 0x10209f00 0 0x100>;
On 27/03/2023 10:36, AngeloGioacchino Del Regno wrote:
> Changes in v2:
> - Squashed the addition of mediatek,mt6795-gce.h header with the
> commit adding the MT6795 GCE compatible.
>
> This series further enhances the support for the MT6795 Helio X10 SoC
> and the Sony Xperia M5 smartphone.
>
> In particular, for the SoC support, this adds:
> - Frequency Hopping support
> - I2C controllers
> - Power domains
> - IOMMU support and LARBs
> - GCE/CMDQ Mailbox
> - VDECSYS and VENCSYS clocks
> - MMSYS support
>
> ...and, on the Xperia M5 smartphone, this adds:
> - Frequency Hopping with Spread Spectrum for MAINPLL, MPLL, MSDCPLL
> - Touchscreen support (Synaptics S2726, fw id: 1898977, RMI4 protocol)
> - Accelerometer
> - Magnetometer
> - Proximity sensor
> - NFC support
>
> ...all of which was successfully tested on the Xperia M5 smartphone.
>
> This series depends on [1] for the MMSYS support.
>
> Plan for step 3 is to push upstream full display support, which does
> already work on my custom tree ;-)
>
> [1]: https://lore.kernel.org/all/[email protected]/
>
> Cheers!
>
Applied all but:
4/17 dt-binding already applied
7/17 dt-binding not applied
8/17 we are missing the dt binding
Thanks a lot for the great work
Matthias
> AngeloGioacchino Del Regno (17):
> arm64: dts: mediatek: mt6795: Add Frequency Hopping Controller node
> arm64: dts: mediatek: mt6795: Add apmixedsys syscon node
> arm64: dts: mediatek: mt6795: xperia-m5: Enable Frequency Hopping
> dt-bindings: i2c: i2c-mt65xx: Add compatible for MT6795 Helio X10
> arm64: dts: mediatek: mt6795: Add nodes for I2C controllers
> arm64: dts: mediatek: mt6795: Add SoC power domains
> dt-bindings: mailbox: mediatek,gce-mailbox: Add support for MT6795
> arm64: dts: mediatek: mt6795: Add support for the CMDQ/GCE mailbox
> arm64: dts: mediatek: mt6795: Add MMSYS node for multimedia clocks
> arm64: dts: mediatek: mt6795: Add VDECSYS and VENCSYS clocks
> arm64: dts: mediatek: mt6795: Add support for IOMMU and LARBs
> arm64: dts: mediatek: mt6795-xperia-m5: Enable I2C 0-3 busses
> arm64: dts: mediatek: mt6795-xperia-m5: Add Synaptics RMI4 Touchscreen
> arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMA255 Accelerometer
> arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMM050 Magnetometer
> arm64: dts: mediatek: mt6795-xperia-m5: Add Sensortek STK3310
> Proximity
> arm64: dts: mediatek: mt6795-xperia-m5: Add NXP PN547 NFC on I2C3
>
> .../devicetree/bindings/i2c/i2c-mt65xx.yaml | 4 +
> .../mailbox/mediatek,gce-mailbox.yaml | 20 +-
> .../dts/mediatek/mt6795-sony-xperia-m5.dts | 166 ++++++++++++
> arch/arm64/boot/dts/mediatek/mt6795.dtsi | 245 ++++++++++++++++++
> include/dt-bindings/gce/mediatek,mt6795-gce.h | 123 +++++++++
> 5 files changed, 550 insertions(+), 8 deletions(-)
> create mode 100644 include/dt-bindings/gce/mediatek,mt6795-gce.h
>
Il 27/03/23 10:36, AngeloGioacchino Del Regno ha scritto:
> Add a compatible string for the MT6795 Helio X10 SoC using MT8173
> binding and add a header for the MT6795's GCE mailbox.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> ---
Hello Jassi,
This commit is blocking the entire series and Matthias already picked everything
but this one for obvious reasons.
Can you please pick this one, or give an ack for Matthias to pick it?
Thanks,
Angelo
> .../mailbox/mediatek,gce-mailbox.yaml | 20 +--
> include/dt-bindings/gce/mediatek,mt6795-gce.h | 123 ++++++++++++++++++
> 2 files changed, 135 insertions(+), 8 deletions(-)
> create mode 100644 include/dt-bindings/gce/mediatek,mt6795-gce.h
>
> diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
> index d383b2ab3ce8..cef9d7601398 100644
> --- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
> @@ -16,14 +16,18 @@ description:
>
> properties:
> compatible:
> - enum:
> - - mediatek,mt6779-gce
> - - mediatek,mt8173-gce
> - - mediatek,mt8183-gce
> - - mediatek,mt8186-gce
> - - mediatek,mt8188-gce
> - - mediatek,mt8192-gce
> - - mediatek,mt8195-gce
> + oneOf:
> + - enum:
> + - mediatek,mt6779-gce
> + - mediatek,mt8173-gce
> + - mediatek,mt8183-gce
> + - mediatek,mt8186-gce
> + - mediatek,mt8188-gce
> + - mediatek,mt8192-gce
> + - mediatek,mt8195-gce
> + - items:
> + - const: mediatek,mt6795-gce
> + - const: mediatek,mt8173-gce
>
> "#mbox-cells":
> const: 2
> diff --git a/include/dt-bindings/gce/mediatek,mt6795-gce.h b/include/dt-bindings/gce/mediatek,mt6795-gce.h
> new file mode 100644
> index 000000000000..97d5ba2d2b44
> --- /dev/null
> +++ b/include/dt-bindings/gce/mediatek,mt6795-gce.h
> @@ -0,0 +1,123 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2023 Collabora Ltd.
> + * Author: AngeloGioacchino Del Regno <[email protected]>
> + */
> +#ifndef _DT_BINDINGS_GCE_MT6795_H
> +#define _DT_BINDINGS_GCE_MT6795_H
> +
> +/* GCE HW thread priority */
> +#define CMDQ_THR_PRIO_LOWEST 0
> +#define CMDQ_THR_PRIO_NORMAL 1
> +#define CMDQ_THR_PRIO_NORMAL_2 2
> +#define CMDQ_THR_PRIO_MEDIUM 3
> +#define CMDQ_THR_PRIO_MEDIUM_2 4
> +#define CMDQ_THR_PRIO_HIGH 5
> +#define CMDQ_THR_PRIO_HIGHER 6
> +#define CMDQ_THR_PRIO_HIGHEST 7
> +
> +/* GCE SUBSYS */
> +#define SUBSYS_1300XXXX 0
> +#define SUBSYS_1400XXXX 1
> +#define SUBSYS_1401XXXX 2
> +#define SUBSYS_1402XXXX 3
> +#define SUBSYS_1500XXXX 4
> +#define SUBSYS_1600XXXX 5
> +#define SUBSYS_1700XXXX 6
> +#define SUBSYS_1800XXXX 7
> +#define SUBSYS_1000XXXX 8
> +#define SUBSYS_1001XXXX 9
> +#define SUBSYS_1002XXXX 10
> +#define SUBSYS_1003XXXX 11
> +#define SUBSYS_1004XXXX 12
> +#define SUBSYS_1005XXXX 13
> +#define SUBSYS_1020XXXX 14
> +#define SUBSYS_1021XXXX 15
> +#define SUBSYS_1120XXXX 16
> +#define SUBSYS_1121XXXX 17
> +#define SUBSYS_1122XXXX 18
> +#define SUBSYS_1123XXXX 19
> +#define SUBSYS_1124XXXX 20
> +#define SUBSYS_1125XXXX 21
> +#define SUBSYS_1126XXXX 22
> +
> +/* GCE HW EVENT */
> +#define CMDQ_EVENT_MDP_RDMA0_SOF 0
> +#define CMDQ_EVENT_MDP_RDMA1_SOF 1
> +#define CMDQ_EVENT_MDP_DSI0_TE_SOF 2
> +#define CMDQ_EVENT_MDP_DSI1_TE_SOF 3
> +#define CMDQ_EVENT_MDP_MVW_SOF 4
> +#define CMDQ_EVENT_MDP_TDSHP0_SOF 5
> +#define CMDQ_EVENT_MDP_TDSHP1_SOF 6
> +#define CMDQ_EVENT_MDP_WDMA_SOF 7
> +#define CMDQ_EVENT_MDP_WROT0_SOF 8
> +#define CMDQ_EVENT_MDP_WROT1_SOF 9
> +#define CMDQ_EVENT_MDP_CROP_SOF 10
> +#define CMDQ_EVENT_DISP_OVL0_SOF 11
> +#define CMDQ_EVENT_DISP_OVL1_SOF 12
> +#define CMDQ_EVENT_DISP_RDMA0_SOF 13
> +#define CMDQ_EVENT_DISP_RDMA1_SOF 14
> +#define CMDQ_EVENT_DISP_RDMA2_SOF 15
> +#define CMDQ_EVENT_DISP_WDMA0_SOF 16
> +#define CMDQ_EVENT_DISP_WDMA1_SOF 17
> +#define CMDQ_EVENT_DISP_COLOR0_SOF 18
> +#define CMDQ_EVENT_DISP_COLOR1_SOF 19
> +#define CMDQ_EVENT_DISP_AAL_SOF 20
> +#define CMDQ_EVENT_DISP_GAMMA_SOF 21
> +#define CMDQ_EVENT_DISP_UFOE_SOF 22
> +#define CMDQ_EVENT_DISP_PWM0_SOF 23
> +#define CMDQ_EVENT_DISP_PWM1_SOF 24
> +#define CMDQ_EVENT_DISP_OD_SOF 25
> +#define CMDQ_EVENT_MDP_RDMA0_EOF 26
> +#define CMDQ_EVENT_MDP_RDMA1_EOF 27
> +#define CMDQ_EVENT_MDP_RSZ0_EOF 28
> +#define CMDQ_EVENT_MDP_RSZ1_EOF 29
> +#define CMDQ_EVENT_MDP_RSZ2_EOF 30
> +#define CMDQ_EVENT_MDP_TDSHP0_EOF 31
> +#define CMDQ_EVENT_MDP_TDSHP1_EOF 32
> +#define CMDQ_EVENT_MDP_WDMA_EOF 33
> +#define CMDQ_EVENT_MDP_WROT0_WRITE_EOF 34
> +#define CMDQ_EVENT_MDP_WROT0_READ_EOF 35
> +#define CMDQ_EVENT_MDP_WROT1_WRITE_EOF 36
> +#define CMDQ_EVENT_MDP_WROT1_READ_EOF 37
> +#define CMDQ_EVENT_MDP_CROP_EOF 38
> +#define CMDQ_EVENT_DISP_OVL0_EOF 39
> +#define CMDQ_EVENT_DISP_OVL1_EOF 40
> +#define CMDQ_EVENT_DISP_RDMA0_EOF 41
> +#define CMDQ_EVENT_DISP_RDMA1_EOF 42
> +#define CMDQ_EVENT_DISP_RDMA2_EOF 43
> +#define CMDQ_EVENT_DISP_WDMA0_EOF 44
> +#define CMDQ_EVENT_DISP_WDMA1_EOF 45
> +#define CMDQ_EVENT_DISP_COLOR0_EOF 46
> +#define CMDQ_EVENT_DISP_COLOR1_EOF 47
> +#define CMDQ_EVENT_DISP_AAL_EOF 48
> +#define CMDQ_EVENT_DISP_GAMMA_EOF 49
> +#define CMDQ_EVENT_DISP_UFOE_EOF 50
> +#define CMDQ_EVENT_DISP_DPI0_EOF 51
> +#define CMDQ_EVENT_MUTEX0_STREAM_EOF 52
> +#define CMDQ_EVENT_MUTEX1_STREAM_EOF 53
> +#define CMDQ_EVENT_MUTEX2_STREAM_EOF 54
> +#define CMDQ_EVENT_MUTEX3_STREAM_EOF 55
> +#define CMDQ_EVENT_MUTEX4_STREAM_EOF 56
> +#define CMDQ_EVENT_MUTEX5_STREAM_EOF 57
> +#define CMDQ_EVENT_MUTEX6_STREAM_EOF 58
> +#define CMDQ_EVENT_MUTEX7_STREAM_EOF 59
> +#define CMDQ_EVENT_MUTEX8_STREAM_EOF 60
> +#define CMDQ_EVENT_MUTEX9_STREAM_EOF 61
> +#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 62
> +#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 63
> +#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 64
> +#define CMDQ_EVENT_ISP_PASS2_2_EOF 129
> +#define CMDQ_EVENT_ISP_PASS2_1_EOF 130
> +#define CMDQ_EVENT_ISP_PASS2_0_EOF 131
> +#define CMDQ_EVENT_ISP_PASS1_1_EOF 132
> +#define CMDQ_EVENT_ISP_PASS1_0_EOF 133
> +#define CMDQ_EVENT_CAMSV_2_PASS1_EOF 134
> +#define CMDQ_EVENT_CAMSV_1_PASS1_EOF 135
> +#define CMDQ_EVENT_SENINF_CAM1_2_3_FIFO_FULL 136
> +#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 137
> +#define CMDQ_EVENT_JPGENC_PASS2_EOF 257
> +#define CMDQ_EVENT_JPGENC_PASS1_EOF 258
> +#define CMDQ_EVENT_JPGDEC_EOF 259
> +
> +#endif
--
AngeloGioacchino Del Regno
Software Engineer
Collabora Ltd.
Platinum Building, St John's Innovation Park, Cambridge CB4 0DS, UK
Registered in England & Wales, no. 5513718
On 02/04/2023 19:26, Matthias Brugger wrote:
>
>
> On 27/03/2023 10:36, AngeloGioacchino Del Regno wrote:
>> Changes in v2:
>> - Squashed the addition of mediatek,mt6795-gce.h header with the
>> commit adding the MT6795 GCE compatible.
>>
>> This series further enhances the support for the MT6795 Helio X10 SoC
>> and the Sony Xperia M5 smartphone.
>>
>> In particular, for the SoC support, this adds:
>> - Frequency Hopping support
>> - I2C controllers
>> - Power domains
>> - IOMMU support and LARBs
>> - GCE/CMDQ Mailbox
>> - VDECSYS and VENCSYS clocks
>> - MMSYS support
>>
>> ...and, on the Xperia M5 smartphone, this adds:
>> - Frequency Hopping with Spread Spectrum for MAINPLL, MPLL, MSDCPLL
>> - Touchscreen support (Synaptics S2726, fw id: 1898977, RMI4 protocol)
>> - Accelerometer
>> - Magnetometer
>> - Proximity sensor
>> - NFC support
>>
>> ...all of which was successfully tested on the Xperia M5 smartphone.
>>
>> This series depends on [1] for the MMSYS support.
>>
>> Plan for step 3 is to push upstream full display support, which does
>> already work on my custom tree ;-)
>>
>> [1]:
>> https://lore.kernel.org/all/[email protected]/
>>
>> Cheers!
>>
>
> Applied all but:
> 4/17 dt-binding already applied
> 7/17 dt-binding not applied
> 8/17 we are missing the dt binding
>
I dropped the following patches for now:
09/17 and 11/17 due to missing 07/17 this break creation of DTBs.
I also dopped 14/17 and 15/17 as buidling the DTBs gave the following warning:
arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts:104.21-109.4: Warning
(unit_address_format): /soc/i2c@11010000/accelerometer@0x10: unit name should
not have leading "0x"
arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts:111.20-114.4: Warning
(unit_address_format): /soc/i2c@11010000/magnetometer@0x12: unit name should not
have leading "0x"
arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts:104.21-109.4: Warning
(i2c_bus_reg): /soc/i2c@11010000/accelerometer@0x10: I2C bus unit address format
error, expected "10"
arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts:111.20-114.4: Warning
(i2c_bus_reg): /soc/i2c@11010000/magnetometer@0x12: I2C bus unit address format
error, expected "12"
Regards,
Matthias
> Thanks a lot for the great work
> Matthias
>
>> AngeloGioacchino Del Regno (17):
>> arm64: dts: mediatek: mt6795: Add Frequency Hopping Controller node
>> arm64: dts: mediatek: mt6795: Add apmixedsys syscon node
>> arm64: dts: mediatek: mt6795: xperia-m5: Enable Frequency Hopping
>> dt-bindings: i2c: i2c-mt65xx: Add compatible for MT6795 Helio X10
>> arm64: dts: mediatek: mt6795: Add nodes for I2C controllers
>> arm64: dts: mediatek: mt6795: Add SoC power domains
>> dt-bindings: mailbox: mediatek,gce-mailbox: Add support for MT6795
>> arm64: dts: mediatek: mt6795: Add support for the CMDQ/GCE mailbox
>> arm64: dts: mediatek: mt6795: Add MMSYS node for multimedia clocks
>> arm64: dts: mediatek: mt6795: Add VDECSYS and VENCSYS clocks
>> arm64: dts: mediatek: mt6795: Add support for IOMMU and LARBs
>> arm64: dts: mediatek: mt6795-xperia-m5: Enable I2C 0-3 busses
>> arm64: dts: mediatek: mt6795-xperia-m5: Add Synaptics RMI4 Touchscreen
>> arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMA255 Accelerometer
>> arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMM050 Magnetometer
>> arm64: dts: mediatek: mt6795-xperia-m5: Add Sensortek STK3310
>> Proximity
>> arm64: dts: mediatek: mt6795-xperia-m5: Add NXP PN547 NFC on I2C3
>>
>> .../devicetree/bindings/i2c/i2c-mt65xx.yaml | 4 +
>> .../mailbox/mediatek,gce-mailbox.yaml | 20 +-
>> .../dts/mediatek/mt6795-sony-xperia-m5.dts | 166 ++++++++++++
>> arch/arm64/boot/dts/mediatek/mt6795.dtsi | 245 ++++++++++++++++++
>> include/dt-bindings/gce/mediatek,mt6795-gce.h | 123 +++++++++
>> 5 files changed, 550 insertions(+), 8 deletions(-)
>> create mode 100644 include/dt-bindings/gce/mediatek,mt6795-gce.h
>>