With this patchset, the Broadcom STB PCIe controller driver
supports Arm, Arm64, and now MIPs.
Jim Quinlan (4):
dt-bindings: PCI: Add compatible string for Brcmstb 74[23]5 MIPs SOCs
MIPS: bmips: Add support PCIe controller device nodes
MIPS: bmips: Remove obsolete DMA mapping support
PCI: brcmstb: Augment driver for MIPs SOCs
.../bindings/pci/brcm,stb-pcie.yaml | 2 +
arch/mips/Kconfig | 1 -
arch/mips/bmips/dma.c | 106 +-----------------
arch/mips/boot/dts/brcm/bcm7425.dtsi | 30 +++++
arch/mips/boot/dts/brcm/bcm7435.dtsi | 30 +++++
arch/mips/boot/dts/brcm/bcm97425svmb.dts | 9 ++
arch/mips/boot/dts/brcm/bcm97435svmb.dts | 9 ++
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pcie-brcmstb.c | 82 +++++++++++++-
9 files changed, 161 insertions(+), 110 deletions(-)
base-commit: ded746bfc94398d2ee9de315a187677b207b2004
prerequisite-patch-id: d47ce1906f7e175cc394be96f85a6eade86a9097
--
2.17.1
The Broadcom STB Arm and MIPs SOCs use the same PCIe controller
HW, although the MIPs version is older.
Signed-off-by: Jim Quinlan <[email protected]>
---
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 1fe102743f82..043412e7735f 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -19,6 +19,8 @@ properties:
- brcm,bcm7278-pcie # Broadcom 7278 Arm
- brcm,bcm7216-pcie # Broadcom 7216 Arm
- brcm,bcm7445-pcie # Broadcom 7445 Arm
+ - brcm,bcm7425-pcie # Broadcom 7425 MIPs
+ - brcm,bcm7435-pcie # Broadcom 7435 MIPs
reg:
maxItems: 1
--
2.17.1
For Broadcom STB PCIe HW. The 7425 and 7435 are MIPs-based SOCs. Not much
difference between the two for the DT properties except that they have
slightly different PCIe interrupt assignments.
Signed-off-by: Jim Quinlan <[email protected]>
---
arch/mips/boot/dts/brcm/bcm7425.dtsi | 30 ++++++++++++++++++++++++
arch/mips/boot/dts/brcm/bcm7435.dtsi | 30 ++++++++++++++++++++++++
arch/mips/boot/dts/brcm/bcm97425svmb.dts | 9 +++++++
arch/mips/boot/dts/brcm/bcm97435svmb.dts | 9 +++++++
4 files changed, 78 insertions(+)
diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi
index aa0b2d39c902..62588c53d356 100644
--- a/arch/mips/boot/dts/brcm/bcm7425.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -584,4 +584,34 @@
};
};
};
+
+ pcie_0: pcie@8b20000 {
+ status = "disabled";
+ compatible = "brcm,bcm7425-pcie";
+
+ ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0x0 0x08000000
+ 0x02000000 0x0 0xd8000000 0xd8000000 0x0 0x08000000
+ 0x02000000 0x0 0xe0000000 0xe0000000 0x0 0x08000000
+ 0x02000000 0x0 0xe8000000 0xe8000000 0x0 0x08000000>;
+
+ reg = <0x10410000 0x19310>;
+ aspm-no-l0s;
+ device_type = "pci";
+ msi-controller;
+ msi-parent = <&pcie_0>;
+ #address-cells = <0x3>;
+ #size-cells = <0x2>;
+ bus-range = <0x0 0xff>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ linux,pci-domain = <0x0>;
+
+ interrupt-parent = <&periph_intc>;
+ interrupts = <37>, <37>;
+ interrupt-names = "pcie", "msi";
+ #interrupt-cells = <0x1>;
+ interrupt-map = <0 0 0 1 &periph_intc 0x21
+ 0 0 0 1 &periph_intc 0x22
+ 0 0 0 1 &periph_intc 0x23
+ 0 0 0 1 &periph_intc 0x24>;
+ };
};
diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi
index 8398b7f68bf4..8c001b944c8b 100644
--- a/arch/mips/boot/dts/brcm/bcm7435.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi
@@ -599,4 +599,34 @@
};
};
};
+
+ pcie_0: pcie@8b20000 {
+ status = "disabled";
+ compatible = "brcm,bcm7435-pcie";
+
+ ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0x0 0x08000000
+ 0x02000000 0x0 0xd8000000 0xd8000000 0x0 0x08000000
+ 0x02000000 0x0 0xe0000000 0xe0000000 0x0 0x08000000
+ 0x02000000 0x0 0xe8000000 0xe8000000 0x0 0x08000000>;
+
+ reg = <0x10410000 0x19310>;
+ aspm-no-l0s;
+ device_type = "pci";
+ msi-controller;
+ msi-parent = <&pcie_0>;
+ #address-cells = <0x3>;
+ #size-cells = <0x2>;
+ bus-range = <0x0 0xff>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ linux,pci-domain = <0x0>;
+
+ interrupt-parent = <&periph_intc>;
+ interrupts = <39>, <39>;
+ interrupt-names = "pcie", "msi";
+ #interrupt-cells = <0x1>;
+ interrupt-map = <0 0 0 1 &periph_intc 0x23
+ 0 0 0 1 &periph_intc 0x24
+ 0 0 0 1 &periph_intc 0x25
+ 0 0 0 1 &periph_intc 0x26>;
+ };
};
diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
index 9efecfe1e05c..f38934934349 100644
--- a/arch/mips/boot/dts/brcm/bcm97425svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
@@ -152,3 +152,12 @@
&waketimer {
status = "okay";
};
+
+&pcie_0 {
+ status = "okay";
+ /* 1GB Memc0, 1GB Memc1 */
+ brcm,scb-sizes = <0 0x40000000 0 0x40000000>;
+ dma-ranges = <0x43000000 0x00000000 0x00000000 0x00000000 0x0 0x10000000
+ 0x43000000 0x00000000 0x10000000 0x20000000 0x0 0x30000000
+ 0x43000000 0x00000000 0x40000000 0x90000000 0x0 0x40000000>;
+};
diff --git a/arch/mips/boot/dts/brcm/bcm97435svmb.dts b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
index b653c6ff74b5..a0cf53e23c07 100644
--- a/arch/mips/boot/dts/brcm/bcm97435svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
@@ -128,3 +128,12 @@
&waketimer {
status = "okay";
};
+
+&pcie_0 {
+ status = "okay";
+ /* 1GB Memc0, 1GB Memc1 */
+ brcm,scb-sizes = <0 0x40000000 0 0x40000000>;
+ dma-ranges = <0x43000000 0x00000000 0x00000000 0x00000000 0x0 0x10000000
+ 0x43000000 0x00000000 0x10000000 0x20000000 0x0 0x30000000
+ 0x43000000 0x00000000 0x40000000 0x90000000 0x0 0x40000000>;
+};
--
2.17.1
The code in 'arch/mips/bmips/dma.c' performed DMA mapping for inbound
regions. This mapping was and is required for the Broadcom STB PCIe
controller HW. This code is removed as the current 'struct device' has a
@dma_range_map field which performs the same functionality by processing
the "dma-ranges" DT property.
Subsequently, ARCH_HAS_PHYS_TO_DMA is now unset since the dma_to_phys()
and phys_to_dma() functions are removed.
Signed-off-by: Jim Quinlan <[email protected]>
---
arch/mips/Kconfig | 1 -
arch/mips/bmips/dma.c | 106 +-----------------------------------------
2 files changed, 2 insertions(+), 105 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0215dc1529e9..eb1184a7254b 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -264,7 +264,6 @@ config BMIPS_GENERIC
bool "Broadcom Generic BMIPS kernel"
select ARCH_HAS_RESET_CONTROLLER
select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
- select ARCH_HAS_PHYS_TO_DMA
select BOOT_RAW
select NO_EXCEPT_FILL
select USE_OF
diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c
index 915ce4b189c1..c535f9cb75ec 100644
--- a/arch/mips/bmips/dma.c
+++ b/arch/mips/bmips/dma.c
@@ -1,68 +1,8 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2014 Kevin Cernekee <[email protected]>
- */
+// SPDX-License-Identifier: GPL-2.0+
-#define pr_fmt(fmt) "bmips-dma: " fmt
-
-#include <linux/device.h>
-#include <linux/dma-direction.h>
-#include <linux/dma-direct.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/printk.h>
-#include <linux/slab.h>
#include <linux/types.h>
#include <asm/bmips.h>
-
-/*
- * BCM338x has configurable address translation windows which allow the
- * peripherals' DMA addresses to be different from the Zephyr-visible
- * physical addresses. e.g. usb_dma_addr = zephyr_pa ^ 0x08000000
- *
- * If the "brcm,ubus" node has a "dma-ranges" property we will enable this
- * translation globally using the provided information. This implements a
- * very limited subset of "dma-ranges" support and it will probably be
- * replaced by a more generic version later.
- */
-
-struct bmips_dma_range {
- u32 child_addr;
- u32 parent_addr;
- u32 size;
-};
-
-static struct bmips_dma_range *bmips_dma_ranges;
-
-#define FLUSH_RAC 0x100
-
-dma_addr_t phys_to_dma(struct device *dev, phys_addr_t pa)
-{
- struct bmips_dma_range *r;
-
- for (r = bmips_dma_ranges; r && r->size; r++) {
- if (pa >= r->child_addr &&
- pa < (r->child_addr + r->size))
- return pa - r->child_addr + r->parent_addr;
- }
- return pa;
-}
-
-phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr)
-{
- struct bmips_dma_range *r;
-
- for (r = bmips_dma_ranges; r && r->size; r++) {
- if (dma_addr >= r->parent_addr &&
- dma_addr < (r->parent_addr + r->size))
- return dma_addr - r->parent_addr + r->child_addr;
- }
- return dma_addr;
-}
+#include <asm/io.h>
void arch_sync_dma_for_cpu_all(void)
{
@@ -79,45 +19,3 @@ void arch_sync_dma_for_cpu_all(void)
__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
__raw_readl(cbr + BMIPS_RAC_CONFIG);
}
-
-static int __init bmips_init_dma_ranges(void)
-{
- struct device_node *np =
- of_find_compatible_node(NULL, NULL, "brcm,ubus");
- const __be32 *data;
- struct bmips_dma_range *r;
- int len;
-
- if (!np)
- return 0;
-
- data = of_get_property(np, "dma-ranges", &len);
- if (!data)
- goto out_good;
-
- len /= sizeof(*data) * 3;
- if (!len)
- goto out_bad;
-
- /* add a dummy (zero) entry at the end as a sentinel */
- bmips_dma_ranges = kcalloc(len + 1, sizeof(struct bmips_dma_range),
- GFP_KERNEL);
- if (!bmips_dma_ranges)
- goto out_bad;
-
- for (r = bmips_dma_ranges; len; len--, r++) {
- r->child_addr = be32_to_cpup(data++);
- r->parent_addr = be32_to_cpup(data++);
- r->size = be32_to_cpup(data++);
- }
-
-out_good:
- of_node_put(np);
- return 0;
-
-out_bad:
- pr_err("error parsing dma-ranges property\n");
- of_node_put(np);
- return -EINVAL;
-}
-arch_initcall(bmips_init_dma_ranges);
--
2.17.1
The current brcmstb driver works for Arm and Arm64. A few things are
modified here for us to support MIPs as well.
o There are four outbound range register groups and each directs a window
of up to 128MB. Even though there are four 128MB DT "ranges" in the
bmips PCIe DT node, these ranges are contiguous and are collapsed into
a single range by the OF range parser. Now the driver assumes a single
range -- for MIPs only -- and splits it back into 128MB sizes.
o For bcm7425, the config space accesses must be 32-bit reads or
writes. In addition, the 4k config space register array is missing
and not used.
o The registers for the upper 32-bits of the outbound window address do
not exist.
o Burst size must be set to 256 (this refers to an internal bus).
Signed-off-by: Jim Quinlan <[email protected]>
---
drivers/pci/controller/Kconfig | 2 +-
drivers/pci/controller/pcie-brcmstb.c | 82 +++++++++++++++++++++++++--
2 files changed, 79 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 93b141110537..4ac474d4a956 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -274,7 +274,7 @@ config PCIE_BRCMSTB
BMIPS_GENERIC || COMPILE_TEST
depends on OF
depends on PCI_MSI_IRQ_DOMAIN
- default ARCH_BRCMSTB
+ default ARCH_BRCMSTB || BMIPS_GENERIC
help
Say Y here to enable PCIe host controller support for
Broadcom STB based SoCs, like the Raspberry Pi 4.
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 1fc7bd49a7ad..a267cd5b3233 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -118,6 +118,7 @@
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
+#define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
#define PCIE_INTR2_CPU_BASE 0x4300
@@ -205,6 +206,8 @@ enum {
enum pcie_type {
GENERIC,
+ BCM7425,
+ BCM7435,
BCM4908,
BCM7278,
BCM2711,
@@ -223,6 +226,12 @@ static const int pcie_offsets[] = {
[EXT_CFG_DATA] = 0x9004,
};
+static const int pcie_offsets_bmips_7425[] = {
+ [RGR1_SW_INIT_1] = 0x8010,
+ [EXT_CFG_INDEX] = 0x8300,
+ [EXT_CFG_DATA] = 0x8304,
+};
+
static const struct pcie_cfg_data generic_cfg = {
.offsets = pcie_offsets,
.type = GENERIC,
@@ -230,6 +239,20 @@ static const struct pcie_cfg_data generic_cfg = {
.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
};
+static const struct pcie_cfg_data bcm7425_cfg = {
+ .offsets = pcie_offsets_bmips_7425,
+ .type = BCM7425,
+ .perst_set = brcm_pcie_perst_set_generic,
+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+};
+
+static const struct pcie_cfg_data bcm7435_cfg = {
+ .offsets = pcie_offsets,
+ .type = BCM7435,
+ .perst_set = brcm_pcie_perst_set_generic,
+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+};
+
static const struct pcie_cfg_data bcm4908_cfg = {
.offsets = pcie_offsets,
.type = BCM4908,
@@ -297,6 +320,11 @@ struct brcm_pcie {
void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
};
+static inline bool is_bmips(const struct brcm_pcie *pcie)
+{
+ return pcie->type == BCM7435 || pcie->type == BCM7425;
+}
+
/*
* This is to convert the size of the inbound "BAR" region to the
* non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
@@ -443,6 +471,9 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
+ if (is_bmips(pcie))
+ return;
+
/* Write the cpu & limit addr upper bits */
high_addr_shift =
HWEIGHT32(PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
@@ -718,12 +749,35 @@ static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
return base + PCIE_EXT_CFG_DATA + where;
}
+static void __iomem *brcm_pcie_map_conf32(struct pci_bus *bus, unsigned int devfn,
+ int where)
+{
+ struct brcm_pcie *pcie = bus->sysdata;
+ void __iomem *base = pcie->base;
+ int idx;
+
+ /* Accesses to the RC go right to the RC registers if slot==0 */
+ if (pci_is_root_bus(bus))
+ return PCI_SLOT(devfn) ? NULL : base + (where & ~0x3);
+
+ /* For devices, write to the config space index register */
+ idx = PCIE_ECAM_OFFSET(bus->number, devfn, (where & ~3));
+ writel(idx, base + IDX_ADDR(pcie));
+ return base + DATA_ADDR(pcie);
+}
+
static struct pci_ops brcm_pcie_ops = {
.map_bus = brcm_pcie_map_conf,
.read = pci_generic_config_read,
.write = pci_generic_config_write,
};
+static struct pci_ops brcm_pcie_ops32 = {
+ .map_bus = brcm_pcie_map_conf32,
+ .read = pci_generic_config_read32,
+ .write = pci_generic_config_write32,
+};
+
static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
{
u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
@@ -883,7 +937,10 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
pcie->bridge_sw_init_set(pcie, 0);
tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
- tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
+ if (is_bmips(pcie))
+ tmp &= ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
+ else
+ tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
/* Wait for SerDes to be stable */
usleep_range(100, 200);
@@ -893,8 +950,10 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
* is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it
* is encoded as 0=Rsvd, 1=128, 2=256, 3=512.
*/
- if (pcie->type == BCM2711)
- burst = 0x0; /* 128B */
+ if (is_bmips(pcie))
+ burst = 0x1; /* 256 bytes */
+ else if (pcie->type == BCM2711)
+ burst = 0x0; /* 128 bytes */
else if (pcie->type == BCM7278)
burst = 0x3; /* 512 bytes */
else
@@ -988,6 +1047,19 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
return -EINVAL;
}
+ if (is_bmips(pcie)) {
+ u64 start = res->start;
+ unsigned int j, nwins = resource_size(res) / SZ_128M;
+
+ /* bmips PCIe outbound windows have a 128MB max size */
+ if (nwins > BRCM_NUM_PCIE_OUT_WINS)
+ nwins = BRCM_NUM_PCIE_OUT_WINS;
+ for (j = 0; j < nwins; j++, start += SZ_128M)
+ brcm_pcie_set_outbound_win(pcie, j, start,
+ start - entry->offset,
+ SZ_128M);
+ break;
+ }
brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
res->start - entry->offset,
resource_size(res));
@@ -1226,6 +1298,8 @@ static const struct of_device_id brcm_pcie_match[] = {
{ .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
{ .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
{ .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
+ { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
+ { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
{},
};
@@ -1315,7 +1389,7 @@ static int brcm_pcie_probe(struct platform_device *pdev)
}
}
- bridge->ops = &brcm_pcie_ops;
+ bridge->ops = pcie->type == BCM7425 ? &brcm_pcie_ops32 : &brcm_pcie_ops;
bridge->sysdata = pcie;
platform_set_drvdata(pdev, pcie);
--
2.17.1
On 12/9/21 12:47 PM, Jim Quinlan wrote:
> The Broadcom STB Arm and MIPs SOCs use the same PCIe controller
> HW, although the MIPs version is older.
>
> Signed-off-by: Jim Quinlan <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
--
Florian
On 12/9/21 12:47 PM, Jim Quinlan wrote:
> For Broadcom STB PCIe HW. The 7425 and 7435 are MIPs-based SOCs. Not much
> difference between the two for the DT properties except that they have
> slightly different PCIe interrupt assignments.
>
> Signed-off-by: Jim Quinlan <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
--
Florian
On 12/9/21 12:47 PM, Jim Quinlan wrote:
> The code in 'arch/mips/bmips/dma.c' performed DMA mapping for inbound
> regions. This mapping was and is required for the Broadcom STB PCIe
> controller HW. This code is removed as the current 'struct device' has a
> @dma_range_map field which performs the same functionality by processing
> the "dma-ranges" DT property.
>
> Subsequently, ARCH_HAS_PHYS_TO_DMA is now unset since the dma_to_phys()
> and phys_to_dma() functions are removed.
>
> Signed-off-by: Jim Quinlan <[email protected]>
CC Christoph so he can do the happy dance, thanks!
Acked-by: Florian Fainelli <[email protected]>
--
Florian
On 12/9/21 12:47 PM, Jim Quinlan wrote:
> The current brcmstb driver works for Arm and Arm64. A few things are
> modified here for us to support MIPs as well.
>
> o There are four outbound range register groups and each directs a window
> of up to 128MB. Even though there are four 128MB DT "ranges" in the
> bmips PCIe DT node, these ranges are contiguous and are collapsed into
> a single range by the OF range parser. Now the driver assumes a single
> range -- for MIPs only -- and splits it back into 128MB sizes.
>
> o For bcm7425, the config space accesses must be 32-bit reads or
> writes. In addition, the 4k config space register array is missing
> and not used.
>
> o The registers for the upper 32-bits of the outbound window address do
> not exist.
>
> o Burst size must be set to 256 (this refers to an internal bus).
>
> Signed-off-by: Jim Quinlan <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
--
Florian
On Thu, Dec 09, 2021 at 01:31:39PM -0800, Florian Fainelli wrote:
> On 12/9/21 12:47 PM, Jim Quinlan wrote:
> > The code in 'arch/mips/bmips/dma.c' performed DMA mapping for inbound
> > regions. This mapping was and is required for the Broadcom STB PCIe
> > controller HW. This code is removed as the current 'struct device' has a
> > @dma_range_map field which performs the same functionality by processing
> > the "dma-ranges" DT property.
> >
> > Subsequently, ARCH_HAS_PHYS_TO_DMA is now unset since the dma_to_phys()
> > and phys_to_dma() functions are removed.
> >
> > Signed-off-by: Jim Quinlan <[email protected]>
>
> CC Christoph so he can do the happy dance, thanks!
No actual patch content in this mail so I can't comment about the
substance, but removing another ARCH_HAS_PHYS_TO_DMA instance is always
awesome.
On Thu, 09 Dec 2021 15:47:22 -0500, Jim Quinlan wrote:
> The Broadcom STB Arm and MIPs SOCs use the same PCIe controller
> HW, although the MIPs version is older.
>
> Signed-off-by: Jim Quinlan <[email protected]>
> ---
> Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <[email protected]>
On Thu, Dec 09, 2021 at 03:47:21PM -0500, Jim Quinlan wrote:
> With this patchset, the Broadcom STB PCIe controller driver
> supports Arm, Arm64, and now MIPs.
>
> Jim Quinlan (4):
> dt-bindings: PCI: Add compatible string for Brcmstb 74[23]5 MIPs SOCs
> MIPS: bmips: Add support PCIe controller device nodes
> MIPS: bmips: Remove obsolete DMA mapping support
> PCI: brcmstb: Augment driver for MIPs SOCs
>
> .../bindings/pci/brcm,stb-pcie.yaml | 2 +
> arch/mips/Kconfig | 1 -
> arch/mips/bmips/dma.c | 106 +-----------------
> arch/mips/boot/dts/brcm/bcm7425.dtsi | 30 +++++
> arch/mips/boot/dts/brcm/bcm7435.dtsi | 30 +++++
> arch/mips/boot/dts/brcm/bcm97425svmb.dts | 9 ++
> arch/mips/boot/dts/brcm/bcm97435svmb.dts | 9 ++
> drivers/pci/controller/Kconfig | 2 +-
> drivers/pci/controller/pcie-brcmstb.c | 82 +++++++++++++-
> 9 files changed, 161 insertions(+), 110 deletions(-)
if nobody objects I'd like to add this series to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
On Wed, Jan 5, 2022 at 5:42 AM Thomas Bogendoerfer
<[email protected]> wrote:
>
> On Thu, Dec 09, 2021 at 03:47:21PM -0500, Jim Quinlan wrote:
> > With this patchset, the Broadcom STB PCIe controller driver
> > supports Arm, Arm64, and now MIPs.
> >
> > Jim Quinlan (4):
> > dt-bindings: PCI: Add compatible string for Brcmstb 74[23]5 MIPs SOCs
> > MIPS: bmips: Add support PCIe controller device nodes
> > MIPS: bmips: Remove obsolete DMA mapping support
> > PCI: brcmstb: Augment driver for MIPs SOCs
> >
> > .../bindings/pci/brcm,stb-pcie.yaml | 2 +
> > arch/mips/Kconfig | 1 -
> > arch/mips/bmips/dma.c | 106 +-----------------
> > arch/mips/boot/dts/brcm/bcm7425.dtsi | 30 +++++
> > arch/mips/boot/dts/brcm/bcm7435.dtsi | 30 +++++
> > arch/mips/boot/dts/brcm/bcm97425svmb.dts | 9 ++
> > arch/mips/boot/dts/brcm/bcm97435svmb.dts | 9 ++
> > drivers/pci/controller/Kconfig | 2 +-
> > drivers/pci/controller/pcie-brcmstb.c | 82 +++++++++++++-
> > 9 files changed, 161 insertions(+), 110 deletions(-)
>
> if nobody objects I'd like to add this series to mips-next.
Hi Thomas,
I have another pullreq in progress [1] that may possibly be accepted
soon. I have tested that
these two pullreqs do not conflict or cause compiler errors regardless
of their merge order.
Regards,
Jim Quinlan
Broadcom STB
[1] [PATCH v10 0/7] PCI: brcmstb: root port turns on sub-device power
[PATCH v10 0/7] PCI: brcmstb: root port turns on sub-device power
>
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea. [ RFC1925, 2.3 ]
On Thu, Dec 09, 2021 at 03:47:21PM -0500, Jim Quinlan wrote:
> With this patchset, the Broadcom STB PCIe controller driver
> supports Arm, Arm64, and now MIPs.
>
> Jim Quinlan (4):
> dt-bindings: PCI: Add compatible string for Brcmstb 74[23]5 MIPs SOCs
> MIPS: bmips: Add support PCIe controller device nodes
> MIPS: bmips: Remove obsolete DMA mapping support
> PCI: brcmstb: Augment driver for MIPs SOCs
>
> .../bindings/pci/brcm,stb-pcie.yaml | 2 +
> arch/mips/Kconfig | 1 -
> arch/mips/bmips/dma.c | 106 +-----------------
> arch/mips/boot/dts/brcm/bcm7425.dtsi | 30 +++++
> arch/mips/boot/dts/brcm/bcm7435.dtsi | 30 +++++
> arch/mips/boot/dts/brcm/bcm97425svmb.dts | 9 ++
> arch/mips/boot/dts/brcm/bcm97435svmb.dts | 9 ++
> drivers/pci/controller/Kconfig | 2 +-
> drivers/pci/controller/pcie-brcmstb.c | 82 +++++++++++++-
> 9 files changed, 161 insertions(+), 110 deletions(-)
series applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
On Thu, 2021-12-09 at 15:47 -0500, Jim Quinlan wrote:
> The code in 'arch/mips/bmips/dma.c' performed DMA mapping for inbound
> regions. This mapping was and is required for the Broadcom STB PCIe
> controller HW. This code is removed as the current 'struct device' has a
> @dma_range_map field which performs the same functionality by processing
> the "dma-ranges" DT property.
>
> Subsequently, ARCH_HAS_PHYS_TO_DMA is now unset since the dma_to_phys()
> and phys_to_dma() functions are removed.
>
> Signed-off-by: Jim Quinlan <[email protected]>
> ---
Reviewed-by: Nicolas Saenz Julienne <[email protected]>
Regards,
Nicolas
On Thu, Dec 09, 2021 at 03:47:25PM -0500, Jim Quinlan wrote:
> The current brcmstb driver works for Arm and Arm64. A few things are
> modified here for us to support MIPs as well.
>
> o There are four outbound range register groups and each directs a window
> of up to 128MB. Even though there are four 128MB DT "ranges" in the
> bmips PCIe DT node, these ranges are contiguous and are collapsed into
> a single range by the OF range parser. Now the driver assumes a single
> range -- for MIPs only -- and splits it back into 128MB sizes.
>
> o For bcm7425, the config space accesses must be 32-bit reads or
> writes. In addition, the 4k config space register array is missing
> and not used.
>
> o The registers for the upper 32-bits of the outbound window address do
> not exist.
>
> o Burst size must be set to 256 (this refers to an internal bus).
> ...
> @@ -118,6 +118,7 @@
> #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
> #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
> +#define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
> @@ -883,7 +937,10 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> pcie->bridge_sw_init_set(pcie, 0);
>
> tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> - tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
> + if (is_bmips(pcie))
> + tmp &= ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
> + else
> + tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
> writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> /* Wait for SerDes to be stable */
> usleep_range(100, 200);
brcm_pcie_resume() has similar code that updates
PCIE_MISC_HARD_PCIE_HARD_DEBUG [1]:
tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
/* wait for serdes to be stable */
udelay(100);
This patch didn't change brcm_pcie_resume() to check is_bmips().
Should it?
If so, it would be nice to use the same method for updating the value
(either u32p_replace_bits or plain C bitops) in both places.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-brcmstb.c?id=v5.18#n1452
On Wed, Jul 6, 2022 at 5:42 PM Bjorn Helgaas <[email protected]> wrote:
>
> On Thu, Dec 09, 2021 at 03:47:25PM -0500, Jim Quinlan wrote:
> > The current brcmstb driver works for Arm and Arm64. A few things are
> > modified here for us to support MIPs as well.
> >
> > o There are four outbound range register groups and each directs a window
> > of up to 128MB. Even though there are four 128MB DT "ranges" in the
> > bmips PCIe DT node, these ranges are contiguous and are collapsed into
> > a single range by the OF range parser. Now the driver assumes a single
> > range -- for MIPs only -- and splits it back into 128MB sizes.
> >
> > o For bcm7425, the config space accesses must be 32-bit reads or
> > writes. In addition, the 4k config space register array is missing
> > and not used.
> >
> > o The registers for the upper 32-bits of the outbound window address do
> > not exist.
> >
> > o Burst size must be set to 256 (this refers to an internal bus).
> > ...
>
> > @@ -118,6 +118,7 @@
> > #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
> > #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
> > #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
> > +#define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
>
> > @@ -883,7 +937,10 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> > pcie->bridge_sw_init_set(pcie, 0);
> >
> > tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> > - tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
> > + if (is_bmips(pcie))
> > + tmp &= ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
> > + else
> > + tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
> > writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> > /* Wait for SerDes to be stable */
> > usleep_range(100, 200);
>
> brcm_pcie_resume() has similar code that updates
> PCIE_MISC_HARD_PCIE_HARD_DEBUG [1]:
>
> tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
> writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
>
> /* wait for serdes to be stable */
> udelay(100);
>
> This patch didn't change brcm_pcie_resume() to check is_bmips().
> Should it?
>
> If so, it would be nice to use the same method for updating the value
> (either u32p_replace_bits or plain C bitops) in both places.
Will send a patch to fix this, thanks.
Jim Quinlan
Broadcom STB
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-brcmstb.c?id=v5.18#n1452