From: Maso Huang <[email protected]>
This series of patches adds support for MediaTek AFE of MT79xx SoC.
Patches are based on broonie tree "for-next" branch.
Maso Huang (7):
ASoC: mediatek: mt79xx: add common header
ASoC: mediatek: mt79xx: support audio clock control
ASoC: mediatek: mt79xx: add platform driver
ASoC: mediatek: mt79xx: support etdm in platform driver
ASoC: mediatek: mt79xx: add machine driver with wm8960
ASoC: dt-bindings: mediatek,mt79xx-wm8960: add mt79xx-wm8960 document
ASoC: dt-bindings: mediatek,mt79xx-afe: add audio afe document
.../bindings/sound/mediatek,mt79xx-afe.yaml | 102 +++
.../sound/mediatek,mt79xx-wm8960.yaml | 53 ++
sound/soc/mediatek/Kconfig | 20 +
sound/soc/mediatek/Makefile | 1 +
sound/soc/mediatek/mt79xx/Makefile | 10 +
sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c | 123 ++++
sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h | 18 +
sound/soc/mediatek/mt79xx/mt79xx-afe-common.h | 49 ++
sound/soc/mediatek/mt79xx/mt79xx-afe-pcm.c | 608 ++++++++++++++++++
sound/soc/mediatek/mt79xx/mt79xx-dai-etdm.c | 421 ++++++++++++
sound/soc/mediatek/mt79xx/mt79xx-reg.h | 206 ++++++
sound/soc/mediatek/mt79xx/mt79xx-wm8960.c | 185 ++++++
12 files changed, 1796 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt79xx-afe.yaml
create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt79xx-wm8960.yaml
create mode 100644 sound/soc/mediatek/mt79xx/Makefile
create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-common.h
create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-pcm.c
create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-dai-etdm.c
create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-reg.h
create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-wm8960.c
--
2.18.0
From: Maso Huang <[email protected]>
Add audio clock wrapper and audio tuner control.
Signed-off-by: Maso Huang <[email protected]>
---
sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c | 123 +++++++++++++++++++++
sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h | 18 +++
2 files changed, 141 insertions(+)
create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
diff --git a/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
new file mode 100644
index 000000000000..f00f0d7de861
--- /dev/null
+++ b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * mt79xx-afe-clk.c -- MediaTek 79xx afe clock ctrl
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Vic Wu <[email protected]>
+ * Maso Huang <[email protected]>
+ */
+
+#include <linux/clk.h>
+
+#include "mt79xx-afe-common.h"
+#include "mt79xx-afe-clk.h"
+#include "mt79xx-reg.h"
+
+enum {
+ CK_INFRA_AUD_BUS_CK = 0,
+ CK_INFRA_AUD_26M_CK,
+ CK_INFRA_AUD_L_CK,
+ CK_INFRA_AUD_AUD_CK,
+ CK_INFRA_AUD_EG2_CK,
+ CLK_NUM
+};
+
+static const char *aud_clks[CLK_NUM] = {
+ [CK_INFRA_AUD_BUS_CK] = "aud_bus_ck",
+ [CK_INFRA_AUD_26M_CK] = "aud_26m_ck",
+ [CK_INFRA_AUD_L_CK] = "aud_l_ck",
+ [CK_INFRA_AUD_AUD_CK] = "aud_aud_ck",
+ [CK_INFRA_AUD_EG2_CK] = "aud_eg2_ck",
+};
+
+int mt79xx_init_clock(struct mtk_base_afe *afe)
+{
+ struct mt79xx_afe_private *afe_priv = afe->platform_priv;
+ int i;
+
+ afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
+ GFP_KERNEL);
+ if (!afe_priv->clk)
+ return -ENOMEM;
+
+ for (i = 0; i < CLK_NUM; i++) {
+ afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
+ if (IS_ERR(afe_priv->clk[i])) {
+ dev_err(afe->dev, "%s(), devm_clk_get %s fail,
+ ret %ld\n", __func__, aud_clks[i],
+ PTR_ERR(afe_priv->clk[i]));
+ return PTR_ERR(afe_priv->clk[i]);
+ }
+ }
+
+ return 0;
+}
+
+int mt79xx_afe_enable_clock(struct mtk_base_afe *afe)
+{
+ struct mt79xx_afe_private *afe_priv = afe->platform_priv;
+ int ret;
+
+ ret = clk_prepare_enable(afe_priv->clk[CK_INFRA_AUD_BUS_CK]);
+ if (ret) {
+ dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
+ __func__, aud_clks[CK_INFRA_AUD_BUS_CK], ret);
+ goto CK_INFRA_AUD_BUS_CK_ERR;
+ }
+
+ ret = clk_prepare_enable(afe_priv->clk[CK_INFRA_AUD_26M_CK]);
+ if (ret) {
+ dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
+ __func__, aud_clks[CK_INFRA_AUD_26M_CK], ret);
+ goto CK_INFRA_AUD_26M_ERR;
+ }
+
+ ret = clk_prepare_enable(afe_priv->clk[CK_INFRA_AUD_L_CK]);
+ if (ret) {
+ dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
+ __func__, aud_clks[CK_INFRA_AUD_L_CK], ret);
+ goto CK_INFRA_AUD_L_CK_ERR;
+ }
+
+ ret = clk_prepare_enable(afe_priv->clk[CK_INFRA_AUD_AUD_CK]);
+ if (ret) {
+ dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
+ __func__, aud_clks[CK_INFRA_AUD_AUD_CK], ret);
+ goto CK_INFRA_AUD_AUD_CK_ERR;
+ }
+
+ ret = clk_prepare_enable(afe_priv->clk[CK_INFRA_AUD_EG2_CK]);
+ if (ret) {
+ dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
+ __func__, aud_clks[CK_INFRA_AUD_EG2_CK], ret);
+ goto CK_INFRA_AUD_EG2_CK_ERR;
+ }
+
+ return 0;
+
+CK_INFRA_AUD_EG2_CK_ERR:
+ clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_AUD_CK]);
+CK_INFRA_AUD_AUD_CK_ERR:
+ clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_L_CK]);
+CK_INFRA_AUD_L_CK_ERR:
+ clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_26M_CK]);
+CK_INFRA_AUD_26M_ERR:
+ clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_BUS_CK]);
+CK_INFRA_AUD_BUS_CK_ERR:
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mt79xx_afe_enable_clock);
+
+int mt79xx_afe_disable_clock(struct mtk_base_afe *afe)
+{
+ struct mt79xx_afe_private *afe_priv = afe->platform_priv;
+
+ clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_EG2_CK]);
+ clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_AUD_CK]);
+ clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_L_CK]);
+ clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_26M_CK]);
+ clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_BUS_CK]);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt79xx_afe_disable_clock);
diff --git a/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
new file mode 100644
index 000000000000..bf9c3edb6922
--- /dev/null
+++ b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * mt79xx-afe-clk.h -- MediaTek 79xx afe clock ctrl definition
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Vic Wu <[email protected]>
+ * Maso Huang <[email protected]>
+ */
+
+#ifndef _MT79XX_AFE_CLK_H_
+#define _MT79XX_AFE_CLK_H_
+
+struct mtk_base_afe;
+
+int mt79xx_init_clock(struct mtk_base_afe *afe);
+int mt79xx_afe_enable_clock(struct mtk_base_afe *afe);
+int mt79xx_afe_disable_clock(struct mtk_base_afe *afe);
+#endif
--
2.18.0
From: Maso Huang <[email protected]>
Add header files for register definition and structure.
Signed-off-by: Maso Huang <[email protected]>
---
sound/soc/mediatek/mt79xx/mt79xx-afe-common.h | 49 +++++
sound/soc/mediatek/mt79xx/mt79xx-reg.h | 206 ++++++++++++++++++
2 files changed, 255 insertions(+)
create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-common.h
create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-reg.h
diff --git a/sound/soc/mediatek/mt79xx/mt79xx-afe-common.h b/sound/soc/mediatek/mt79xx/mt79xx-afe-common.h
new file mode 100644
index 000000000000..13c9e51d7b38
--- /dev/null
+++ b/sound/soc/mediatek/mt79xx/mt79xx-afe-common.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * mt79xx-afe-common.h -- MediaTek 79xx audio driver definitions
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Vic Wu <[email protected]>
+ * Maso Huang <[email protected]>
+ */
+
+#ifndef _MT_79XX_AFE_COMMON_H_
+#define _MT_79XX_AFE_COMMON_H_
+
+#include <sound/soc.h>
+#include <linux/list.h>
+#include <linux/regmap.h>
+#include "../common/mtk-base-afe.h"
+
+enum {
+ MT79XX_MEMIF_DL1,
+ MT79XX_MEMIF_VUL12,
+ MT79XX_MEMIF_NUM,
+ MT79XX_DAI_ETDM = MT79XX_MEMIF_NUM,
+ MT79XX_DAI_NUM,
+};
+
+enum {
+ MT79XX_IRQ_0,
+ MT79XX_IRQ_1,
+ MT79XX_IRQ_2,
+ MT79XX_IRQ_NUM,
+};
+
+struct clk;
+
+struct mt79xx_afe_private {
+ struct clk **clk;
+
+ int pm_runtime_bypass_reg_ctl;
+
+ /* dai */
+ void *dai_priv[MT79XX_DAI_NUM];
+};
+
+unsigned int mt79xx_afe_rate_transform(struct device *dev,
+ unsigned int rate);
+
+/* dai register */
+int mt79xx_dai_etdm_register(struct mtk_base_afe *afe);
+#endif
diff --git a/sound/soc/mediatek/mt79xx/mt79xx-reg.h b/sound/soc/mediatek/mt79xx/mt79xx-reg.h
new file mode 100644
index 000000000000..28c0aeba9bdf
--- /dev/null
+++ b/sound/soc/mediatek/mt79xx/mt79xx-reg.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * mt79xx-reg.h -- MediaTek 79xx audio driver reg definition
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Vic Wu <[email protected]>
+ * Maso Huang <[email protected]>
+ */
+
+#ifndef _MT79XX_REG_H_
+#define _MT79XX_REG_H_
+
+#define AUDIO_TOP_CON2 0x0008
+#define AUDIO_TOP_CON4 0x0010
+#define AUDIO_ENGEN_CON0 0x0014
+#define AFE_IRQ_MCU_EN 0x0100
+#define AFE_IRQ_MCU_STATUS 0x0120
+#define AFE_IRQ_MCU_CLR 0x0128
+#define AFE_IRQ0_MCU_CFG0 0x0140
+#define AFE_IRQ0_MCU_CFG1 0x0144
+#define AFE_IRQ1_MCU_CFG0 0x0148
+#define AFE_IRQ1_MCU_CFG1 0x014c
+#define AFE_IRQ2_MCU_CFG0 0x0150
+#define AFE_IRQ2_MCU_CFG1 0x0154
+#define ETDM_IN5_CON0 0x13f0
+#define ETDM_IN5_CON1 0x13f4
+#define ETDM_IN5_CON2 0x13f8
+#define ETDM_IN5_CON3 0x13fc
+#define ETDM_IN5_CON4 0x1400
+#define ETDM_OUT5_CON0 0x1570
+#define ETDM_OUT5_CON4 0x1580
+#define ETDM_OUT5_CON5 0x1584
+#define ETDM_4_7_COWORK_CON0 0x15e0
+#define ETDM_4_7_COWORK_CON1 0x15e4
+#define AFE_CONN018_1 0x1b44
+#define AFE_CONN018_4 0x1b50
+#define AFE_CONN019_1 0x1b64
+#define AFE_CONN019_4 0x1b70
+#define AFE_CONN124_1 0x2884
+#define AFE_CONN124_4 0x2890
+#define AFE_CONN125_1 0x28a4
+#define AFE_CONN125_4 0x28b0
+#define AFE_CONN_RS_0 0x3920
+#define AFE_CONN_RS_3 0x392c
+#define AFE_CONN_16BIT_0 0x3960
+#define AFE_CONN_16BIT_3 0x396c
+#define AFE_CONN_24BIT_0 0x3980
+#define AFE_CONN_24BIT_3 0x398c
+#define AFE_MEMIF_CON0 0x3d98
+#define AFE_MEMIF_RD_MON 0x3da0
+#define AFE_MEMIF_WR_MON 0x3da4
+#define AFE_DL0_BASE_MSB 0x3e40
+#define AFE_DL0_BASE 0x3e44
+#define AFE_DL0_CUR_MSB 0x3e48
+#define AFE_DL0_CUR 0x3e4c
+#define AFE_DL0_END_MSB 0x3e50
+#define AFE_DL0_END 0x3e54
+#define AFE_DL0_RCH_MON 0x3e58
+#define AFE_DL0_LCH_MON 0x3e5c
+#define AFE_DL0_CON0 0x3e60
+#define AFE_VUL0_BASE_MSB 0x4220
+#define AFE_VUL0_BASE 0x4224
+#define AFE_VUL0_CUR_MSB 0x4228
+#define AFE_VUL0_CUR 0x422c
+#define AFE_VUL0_END_MSB 0x4230
+#define AFE_VUL0_END 0x4234
+#define AFE_VUL0_CON0 0x4238
+
+#define AFE_MAX_REGISTER AFE_VUL0_CON0
+#define AFE_IRQ_STATUS_BITS 0x7
+#define AFE_IRQ_CNT_SHIFT 0
+#define AFE_IRQ_CNT_MASK 0xffffff
+
+/* AUDIO_TOP_CON2 */
+#define CLK_OUT5_PDN BIT(14)
+#define CLK_OUT5_PDN_MASK BIT(14)
+#define CLK_IN5_PDN BIT(7)
+#define CLK_IN5_PDN_MASK BIT(7)
+
+/* AUDIO_TOP_CON4 */
+#define PDN_APLL_TUNER2 BIT(12)
+#define PDN_APLL_TUNER2_MASK BIT(12)
+
+/* AUDIO_ENGEN_CON0 */
+#define AUD_APLL2_EN BIT(3)
+#define AUD_APLL2_EN_MASK BIT(3)
+#define AUD_26M_EN BIT(0)
+#define AUD_26M_EN_MASK BIT(0)
+
+/* AFE_DL0_CON0 */
+#define DL0_ON_SFT 28
+#define DL0_ON_MASK 0x1
+#define DL0_ON_MASK_SFT BIT(28)
+#define DL0_MINLEN_SFT 20
+#define DL0_MINLEN_MASK 0xf
+#define DL0_MINLEN_MASK_SFT (0xf << 20)
+#define DL0_MODE_SFT 8
+#define DL0_MODE_MASK 0x1f
+#define DL0_MODE_MASK_SFT (0x1f << 8)
+#define DL0_PBUF_SIZE_SFT 5
+#define DL0_PBUF_SIZE_MASK 0x3
+#define DL0_PBUF_SIZE_MASK_SFT (0x3 << 5)
+#define DL0_MONO_SFT 4
+#define DL0_MONO_MASK 0x1
+#define DL0_MONO_MASK_SFT BIT(4)
+#define DL0_HALIGN_SFT 2
+#define DL0_HALIGN_MASK 0x1
+#define DL0_HALIGN_MASK_SFT BIT(2)
+#define DL0_HD_MODE_SFT 0
+#define DL0_HD_MODE_MASK 0x3
+#define DL0_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_VUL0_CON0 */
+#define VUL0_ON_SFT 28
+#define VUL0_ON_MASK 0x1
+#define VUL0_ON_MASK_SFT BIT(28)
+#define VUL0_MODE_SFT 8
+#define VUL0_MODE_MASK 0x1f
+#define VUL0_MODE_MASK_SFT (0x1f << 8)
+#define VUL0_MONO_SFT 4
+#define VUL0_MONO_MASK 0x1
+#define VUL0_MONO_MASK_SFT BIT(4)
+#define VUL0_HALIGN_SFT 2
+#define VUL0_HALIGN_MASK 0x1
+#define VUL0_HALIGN_MASK_SFT BIT(2)
+#define VUL0_HD_MODE_SFT 0
+#define VUL0_HD_MODE_MASK 0x3
+#define VUL0_HD_MODE_MASK_SFT (0x3 << 0)
+
+/* AFE_IRQ_MCU_CON */
+#define IRQ_MCU_MODE_SFT 4
+#define IRQ_MCU_MODE_MASK 0x1f
+#define IRQ_MCU_MODE_MASK_SFT (0x1f << 4)
+#define IRQ_MCU_ON_SFT 0
+#define IRQ_MCU_ON_MASK 0x1
+#define IRQ_MCU_ON_MASK_SFT BIT(0)
+#define IRQ0_MCU_CLR_SFT 0
+#define IRQ0_MCU_CLR_MASK 0x1
+#define IRQ0_MCU_CLR_MASK_SFT BIT(0)
+#define IRQ1_MCU_CLR_SFT 1
+#define IRQ1_MCU_CLR_MASK 0x1
+#define IRQ1_MCU_CLR_MASK_SFT BIT(1)
+#define IRQ2_MCU_CLR_SFT 2
+#define IRQ2_MCU_CLR_MASK 0x1
+#define IRQ2_MCU_CLR_MASK_SFT BIT(2)
+
+/* ETDM_IN5_CON2 */
+#define IN_CLK_SRC(x) ((x) << 10)
+#define IN_CLK_SRC_SFT 10
+#define IN_CLK_SRC_MASK GENMASK(12, 10)
+
+/* ETDM_IN5_CON3 */
+#define IN_SEL_FS(x) ((x) << 26)
+#define IN_SEL_FS_SFT 26
+#define IN_SEL_FS_MASK GENMASK(30, 26)
+
+/* ETDM_IN5_CON4 */
+#define IN_RELATCH(x) ((x) << 20)
+#define IN_RELATCH_SFT 20
+#define IN_RELATCH_MASK GENMASK(24, 20)
+#define IN_CLK_INV BIT(18)
+#define IN_CLK_INV_MASK BIT(18)
+
+/* ETDM_IN5_CON0 & ETDM_OUT5_CON0 */
+#define RELATCH_SRC(x) ((x) << 28)
+#define RELATCH_SRC_SFT 28
+#define RELATCH_SRC_MASK GENMASK(30, 28)
+#define ETDM_CH_NUM(x) (((x) - 1) << 23)
+#define ETDM_CH_NUM_SFT 23
+#define ETDM_CH_NUM_MASK GENMASK(27, 23)
+#define ETDM_WRD_LEN(x) (((x) - 1) << 16)
+#define ETDM_WRD_LEN_SFT 16
+#define ETDM_WRD_LEN_MASK GENMASK(20, 16)
+#define ETDM_BIT_LEN(x) (((x) - 1) << 11)
+#define ETDM_BIT_LEN_SFT 11
+#define ETDM_BIT_LEN_MASK GENMASK(15, 11)
+#define ETDM_FMT(x) ((x) << 6)
+#define ETDM_FMT_SFT 6
+#define ETDM_FMT_MASK GENMASK(8, 6)
+#define ETDM_SYNC BIT(1)
+#define ETDM_SYNC_MASK BIT(1)
+#define ETDM_EN BIT(0)
+#define ETDM_EN_MASK BIT(0)
+
+/* ETDM_OUT5_CON4 */
+#define OUT_RELATCH(x) ((x) << 24)
+#define OUT_RELATCH_SFT 24
+#define OUT_RELATCH_MASK GENMASK(28, 24)
+#define OUT_CLK_SRC(x) ((x) << 6)
+#define OUT_CLK_SRC_SFT 6
+#define OUT_CLK_SRC_MASK GENMASK(8, 6)
+#define OUT_SEL_FS(x) ((x) << 0)
+#define OUT_SEL_FS_SFT 0
+#define OUT_SEL_FS_MASK GENMASK(4, 0)
+
+/* ETDM_OUT5_CON5 */
+#define ETDM_CLK_DIV BIT(12)
+#define ETDM_CLK_DIV_MASK BIT(12)
+#define OUT_CLK_INV BIT(9)
+#define OUT_CLK_INV_MASK BIT(9)
+
+/* ETDM_4_7_COWORK_CON0 */
+#define OUT_SEL(x) ((x) << 12)
+#define OUT_SEL_SFT 12
+#define OUT_SEL_MASK GENMASK(15, 12)
+#endif
--
2.18.0
On 12.06.2023 13:52, Maso Hunag wrote:
> [You don't often get email from [email protected]. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Maso Huang <[email protected]>
>
> Add audio clock wrapper and audio tuner control.
>
> Signed-off-by: Maso Huang <[email protected]>
> ---
> sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c | 123 +++++++++++++++++++++
> sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h | 18 +++
> 2 files changed, 141 insertions(+)
> create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
> create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
>
> diff --git a/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
> new file mode 100644
> index 000000000000..f00f0d7de861
> --- /dev/null
> +++ b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
> @@ -0,0 +1,123 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * mt79xx-afe-clk.c -- MediaTek 79xx afe clock ctrl
> + *
> + * Copyright (c) 2021 MediaTek Inc.
> + * Author: Vic Wu <[email protected]>
> + * Maso Huang <[email protected]>
> + */
> +
> +#include <linux/clk.h>
> +
> +#include "mt79xx-afe-common.h"
> +#include "mt79xx-afe-clk.h"
> +#include "mt79xx-reg.h"
> +
> +enum {
> + CK_INFRA_AUD_BUS_CK = 0,
> + CK_INFRA_AUD_26M_CK,
> + CK_INFRA_AUD_L_CK,
> + CK_INFRA_AUD_AUD_CK,
> + CK_INFRA_AUD_EG2_CK,
> + CLK_NUM
> +};
> +
> +static const char *aud_clks[CLK_NUM] = {
> + [CK_INFRA_AUD_BUS_CK] = "aud_bus_ck",
> + [CK_INFRA_AUD_26M_CK] = "aud_26m_ck",
> + [CK_INFRA_AUD_L_CK] = "aud_l_ck",
> + [CK_INFRA_AUD_AUD_CK] = "aud_aud_ck",
> + [CK_INFRA_AUD_EG2_CK] = "aud_eg2_ck",
> +};
> +
> +int mt79xx_init_clock(struct mtk_base_afe *afe)
> +{
> + struct mt79xx_afe_private *afe_priv = afe->platform_priv;
> + int i;
> +
> + afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
> + GFP_KERNEL);
> + if (!afe_priv->clk)
> + return -ENOMEM;
> +
> + for (i = 0; i < CLK_NUM; i++) {
> + afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
> + if (IS_ERR(afe_priv->clk[i])) {
> + dev_err(afe->dev, "%s(), devm_clk_get %s fail,
> + ret %ld\n", __func__, aud_clks[i],
> + PTR_ERR(afe_priv->clk[i]));
> + return PTR_ERR(afe_priv->clk[i]);
> + }
> + }
You can use devm_clk_bulk_get()
> +
> + return 0;
> +}
> +
> +int mt79xx_afe_enable_clock(struct mtk_base_afe *afe)
> +{
> + struct mt79xx_afe_private *afe_priv = afe->platform_priv;
> + int ret;
> +
> + ret = clk_prepare_enable(afe_priv->clk[CK_INFRA_AUD_BUS_CK]);
> + if (ret) {
> + dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
> + __func__, aud_clks[CK_INFRA_AUD_BUS_CK], ret);
> + goto CK_INFRA_AUD_BUS_CK_ERR;
> + }
> +
> + ret = clk_prepare_enable(afe_priv->clk[CK_INFRA_AUD_26M_CK]);
> + if (ret) {
> + dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
> + __func__, aud_clks[CK_INFRA_AUD_26M_CK], ret);
> + goto CK_INFRA_AUD_26M_ERR;
> + }
> +
> + ret = clk_prepare_enable(afe_priv->clk[CK_INFRA_AUD_L_CK]);
> + if (ret) {
> + dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
> + __func__, aud_clks[CK_INFRA_AUD_L_CK], ret);
> + goto CK_INFRA_AUD_L_CK_ERR;
> + }
> +
> + ret = clk_prepare_enable(afe_priv->clk[CK_INFRA_AUD_AUD_CK]);
> + if (ret) {
> + dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
> + __func__, aud_clks[CK_INFRA_AUD_AUD_CK], ret);
> + goto CK_INFRA_AUD_AUD_CK_ERR;
> + }
> +
> + ret = clk_prepare_enable(afe_priv->clk[CK_INFRA_AUD_EG2_CK]);
> + if (ret) {
> + dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
> + __func__, aud_clks[CK_INFRA_AUD_EG2_CK], ret);
> + goto CK_INFRA_AUD_EG2_CK_ERR;
> + }
And clk_bulk_prepare_enable() instead all these.
> +
> + return 0;
> +
> +CK_INFRA_AUD_EG2_CK_ERR:
> + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_AUD_CK]);
> +CK_INFRA_AUD_AUD_CK_ERR:
> + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_L_CK]);
> +CK_INFRA_AUD_L_CK_ERR:
> + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_26M_CK]);
> +CK_INFRA_AUD_26M_ERR:
> + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_BUS_CK]);
> +CK_INFRA_AUD_BUS_CK_ERR:
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(mt79xx_afe_enable_clock);
> +
> +int mt79xx_afe_disable_clock(struct mtk_base_afe *afe)
> +{
> + struct mt79xx_afe_private *afe_priv = afe->platform_priv;
> +
> + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_EG2_CK]);
> + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_AUD_CK]);
> + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_L_CK]);
> + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_26M_CK]);
> + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_BUS_CK]);
> +
And also clk_bulk_disable_unprepare() here.
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(mt79xx_afe_disable_clock);
> diff --git a/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
> new file mode 100644
> index 000000000000..bf9c3edb6922
> --- /dev/null
> +++ b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * mt79xx-afe-clk.h -- MediaTek 79xx afe clock ctrl definition
> + *
> + * Copyright (c) 2021 MediaTek Inc.
> + * Author: Vic Wu <[email protected]>
> + * Maso Huang <[email protected]>
> + */
> +
> +#ifndef _MT79XX_AFE_CLK_H_
> +#define _MT79XX_AFE_CLK_H_
> +
> +struct mtk_base_afe;
> +
> +int mt79xx_init_clock(struct mtk_base_afe *afe);
> +int mt79xx_afe_enable_clock(struct mtk_base_afe *afe);
> +int mt79xx_afe_disable_clock(struct mtk_base_afe *afe);
> +#endif
> --
> 2.18.0
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Il 12/06/23 12:52, Maso Hunag ha scritto:
> From: Maso Huang <[email protected]>
>
> Add header files for register definition and structure.
>
> Signed-off-by: Maso Huang <[email protected]>
> ---
> sound/soc/mediatek/mt79xx/mt79xx-afe-common.h | 49 +++++
> sound/soc/mediatek/mt79xx/mt79xx-reg.h | 206 ++++++++++++++++++
Please, s/mt79xx/mt7981/g. Wildcards are not permitted.
> 2 files changed, 255 insertions(+)
> create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-common.h
> create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-reg.h
>
> diff --git a/sound/soc/mediatek/mt79xx/mt79xx-afe-common.h b/sound/soc/mediatek/mt79xx/mt79xx-afe-common.h
> new file mode 100644
> index 000000000000..13c9e51d7b38
> --- /dev/null
> +++ b/sound/soc/mediatek/mt79xx/mt79xx-afe-common.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * mt79xx-afe-common.h -- MediaTek 79xx audio driver definitions
> + *
> + * Copyright (c) 2021 MediaTek Inc.
> + * Author: Vic Wu <[email protected]>
> + * Maso Huang <[email protected]>
> + */
> +
> +#ifndef _MT_79XX_AFE_COMMON_H_
> +#define _MT_79XX_AFE_COMMON_H_
> +
> +#include <sound/soc.h>
> +#include <linux/list.h>
> +#include <linux/regmap.h>
> +#include "../common/mtk-base-afe.h"
> +
> +enum {
> + MT79XX_MEMIF_DL1,
> + MT79XX_MEMIF_VUL12,
> + MT79XX_MEMIF_NUM,
> + MT79XX_DAI_ETDM = MT79XX_MEMIF_NUM,
> + MT79XX_DAI_NUM,
> +};
Same for the enumeration entries, and the definitions and the function names.
Please change everything to `mt7981` (strategy is to use the name of the oldest
SoC: if the oldest is not 7981, change accordingly).
> +
> +enum {
> + MT79XX_IRQ_0,
> + MT79XX_IRQ_1,
> + MT79XX_IRQ_2,
> + MT79XX_IRQ_NUM,
> +};
> +
> +struct clk;
> +
> +struct mt79xx_afe_private {
> + struct clk **clk;
> +
> + int pm_runtime_bypass_reg_ctl;
> +
> + /* dai */
> + void *dai_priv[MT79XX_DAI_NUM];
> +};
> +
> +unsigned int mt79xx_afe_rate_transform(struct device *dev,
> + unsigned int rate);
> +
> +/* dai register */
> +int mt79xx_dai_etdm_register(struct mtk_base_afe *afe);
> +#endif
> diff --git a/sound/soc/mediatek/mt79xx/mt79xx-reg.h b/sound/soc/mediatek/mt79xx/mt79xx-reg.h
> new file mode 100644
> index 000000000000..28c0aeba9bdf
> --- /dev/null
> +++ b/sound/soc/mediatek/mt79xx/mt79xx-reg.h
> @@ -0,0 +1,206 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * mt79xx-reg.h -- MediaTek 79xx audio driver reg definition
> + *
> + * Copyright (c) 2021 MediaTek Inc.
> + * Author: Vic Wu <[email protected]>
> + * Maso Huang <[email protected]>
> + */
> +
> +#ifndef _MT79XX_REG_H_
> +#define _MT79XX_REG_H_
_MT7981_REG_H_
Everything else looks ok.
Thanks,
Angelo
On Tue, 2023-06-13 at 07:27 +0000, [email protected] wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> On 12.06.2023 13:52, Maso Hunag wrote:
> > [You don't often get email from [email protected]. Learn why
> this is important at https://aka.ms/LearnAboutSenderIdentification ]
> >
> > EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> >
> > From: Maso Huang <[email protected]>
> >
> > Add audio clock wrapper and audio tuner control.
> >
> > Signed-off-by: Maso Huang <[email protected]>
> > ---
> > sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c | 123
> +++++++++++++++++++++
> > sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h | 18 +++
> > 2 files changed, 141 insertions(+)
> > create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
> > create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
> >
> > diff --git a/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
> b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
> > new file mode 100644
> > index 000000000000..f00f0d7de861
> > --- /dev/null
> > +++ b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.c
> > @@ -0,0 +1,123 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * mt79xx-afe-clk.c -- MediaTek 79xx afe clock ctrl
> > + *
> > + * Copyright (c) 2021 MediaTek Inc.
> > + * Author: Vic Wu <[email protected]>
> > + * Maso Huang <[email protected]>
> > + */
> > +
> > +#include <linux/clk.h>
> > +
> > +#include "mt79xx-afe-common.h"
> > +#include "mt79xx-afe-clk.h"
> > +#include "mt79xx-reg.h"
> > +
> > +enum {
> > + CK_INFRA_AUD_BUS_CK = 0,
> > + CK_INFRA_AUD_26M_CK,
> > + CK_INFRA_AUD_L_CK,
> > + CK_INFRA_AUD_AUD_CK,
> > + CK_INFRA_AUD_EG2_CK,
> > + CLK_NUM
> > +};
> > +
> > +static const char *aud_clks[CLK_NUM] = {
> > + [CK_INFRA_AUD_BUS_CK] = "aud_bus_ck",
> > + [CK_INFRA_AUD_26M_CK] = "aud_26m_ck",
> > + [CK_INFRA_AUD_L_CK] = "aud_l_ck",
> > + [CK_INFRA_AUD_AUD_CK] = "aud_aud_ck",
> > + [CK_INFRA_AUD_EG2_CK] = "aud_eg2_ck",
> > +};
> > +
> > +int mt79xx_init_clock(struct mtk_base_afe *afe)
> > +{
> > + struct mt79xx_afe_private *afe_priv = afe->platform_priv;
> > + int i;
> > +
> > + afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM,
> sizeof(*afe_priv->clk),
> > + GFP_KERNEL);
> > + if (!afe_priv->clk)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < CLK_NUM; i++) {
> > + afe_priv->clk[i] = devm_clk_get(afe->dev,
> aud_clks[i]);
> > + if (IS_ERR(afe_priv->clk[i])) {
> > + dev_err(afe->dev, "%s(), devm_clk_get %s
> fail,
> > + ret %ld\n", __func__, aud_clks[i],
> > + PTR_ERR(afe_priv->clk[i]));
> > + return PTR_ERR(afe_priv->clk[i]);
> > + }
> > + }
>
> You can use devm_clk_bulk_get()
>
Hi Claudiu,
Thanks for your review.
I'll use this api in v2 patch.
> > +
> > + return 0;
> > +}
> > +
> > +int mt79xx_afe_enable_clock(struct mtk_base_afe *afe)
> > +{
> > + struct mt79xx_afe_private *afe_priv = afe->platform_priv;
> > + int ret;
> > +
> > + ret = clk_prepare_enable(afe_priv-
> >clk[CK_INFRA_AUD_BUS_CK]);
> > + if (ret) {
> > + dev_err(afe->dev, "%s(), clk_prepare_enable %s fail
> %d\n",
> > + __func__, aud_clks[CK_INFRA_AUD_BUS_CK],
> ret);
> > + goto CK_INFRA_AUD_BUS_CK_ERR;
> > + }
> > +
> > + ret = clk_prepare_enable(afe_priv-
> >clk[CK_INFRA_AUD_26M_CK]);
> > + if (ret) {
> > + dev_err(afe->dev, "%s(), clk_prepare_enable %s fail
> %d\n",
> > + __func__, aud_clks[CK_INFRA_AUD_26M_CK],
> ret);
> > + goto CK_INFRA_AUD_26M_ERR;
> > + }
> > +
> > + ret = clk_prepare_enable(afe_priv->clk[CK_INFRA_AUD_L_CK]);
> > + if (ret) {
> > + dev_err(afe->dev, "%s(), clk_prepare_enable %s fail
> %d\n",
> > + __func__, aud_clks[CK_INFRA_AUD_L_CK],
> ret);
> > + goto CK_INFRA_AUD_L_CK_ERR;
> > + }
> > +
> > + ret = clk_prepare_enable(afe_priv-
> >clk[CK_INFRA_AUD_AUD_CK]);
> > + if (ret) {
> > + dev_err(afe->dev, "%s clk_prepare_enable %s fail
> %d\n",
> > + __func__, aud_clks[CK_INFRA_AUD_AUD_CK],
> ret);
> > + goto CK_INFRA_AUD_AUD_CK_ERR;
> > + }
> > +
> > + ret = clk_prepare_enable(afe_priv-
> >clk[CK_INFRA_AUD_EG2_CK]);
> > + if (ret) {
> > + dev_err(afe->dev, "%s clk_prepare_enable %s fail
> %d\n",
> > + __func__, aud_clks[CK_INFRA_AUD_EG2_CK],
> ret);
> > + goto CK_INFRA_AUD_EG2_CK_ERR;
> > + }
>
> And clk_bulk_prepare_enable() instead all these.
>
I'll use this api in v2 patch.
> > +
> > + return 0;
> > +
> > +CK_INFRA_AUD_EG2_CK_ERR:
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_AUD_CK]);
> > +CK_INFRA_AUD_AUD_CK_ERR:
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_L_CK]);
> > +CK_INFRA_AUD_L_CK_ERR:
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_26M_CK]);
> > +CK_INFRA_AUD_26M_ERR:
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_BUS_CK]);
> > +CK_INFRA_AUD_BUS_CK_ERR:
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(mt79xx_afe_enable_clock);
> > +
> > +int mt79xx_afe_disable_clock(struct mtk_base_afe *afe)
> > +{
> > + struct mt79xx_afe_private *afe_priv = afe->platform_priv;
> > +
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_EG2_CK]);
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_AUD_CK]);
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_L_CK]);
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_26M_CK]);
> > + clk_disable_unprepare(afe_priv->clk[CK_INFRA_AUD_BUS_CK]);
> > +
>
> And also clk_bulk_disable_unprepare() here.
>
I'll use this api in v2 patch.
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(mt79xx_afe_disable_clock);
> > diff --git a/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
> b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
> > new file mode 100644
> > index 000000000000..bf9c3edb6922
> > --- /dev/null
> > +++ b/sound/soc/mediatek/mt79xx/mt79xx-afe-clk.h
> > @@ -0,0 +1,18 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * mt79xx-afe-clk.h -- MediaTek 79xx afe clock ctrl definition
> > + *
> > + * Copyright (c) 2021 MediaTek Inc.
> > + * Author: Vic Wu <[email protected]>
> > + * Maso Huang <[email protected]>
> > + */
> > +
> > +#ifndef _MT79XX_AFE_CLK_H_
> > +#define _MT79XX_AFE_CLK_H_
> > +
> > +struct mtk_base_afe;
> > +
> > +int mt79xx_init_clock(struct mtk_base_afe *afe);
> > +int mt79xx_afe_enable_clock(struct mtk_base_afe *afe);
> > +int mt79xx_afe_disable_clock(struct mtk_base_afe *afe);
> > +#endif
> > --
> > 2.18.0
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>
Best regards,
Maso
On Wed, 2023-06-14 at 09:44 +0200, AngeloGioacchino Del Regno wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> Il 12/06/23 12:52, Maso Hunag ha scritto:
> > From: Maso Huang <[email protected]>
> >
> > Add header files for register definition and structure.
> >
> > Signed-off-by: Maso Huang <[email protected]>
> > ---
> > sound/soc/mediatek/mt79xx/mt79xx-afe-common.h | 49 +++++
> > sound/soc/mediatek/mt79xx/mt79xx-reg.h | 206
> ++++++++++++++++++
>
> Please, s/mt79xx/mt7981/g. Wildcards are not permitted.
>
Hi Angelo,
Thanks for your review.
The oldest is mt7986, so I'll use mt7986 instead of mt79xx in v2 patch.
> > 2 files changed, 255 insertions(+)
> > create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-afe-common.h
> > create mode 100644 sound/soc/mediatek/mt79xx/mt79xx-reg.h
> >
> > diff --git a/sound/soc/mediatek/mt79xx/mt79xx-afe-common.h
> b/sound/soc/mediatek/mt79xx/mt79xx-afe-common.h
> > new file mode 100644
> > index 000000000000..13c9e51d7b38
> > --- /dev/null
> > +++ b/sound/soc/mediatek/mt79xx/mt79xx-afe-common.h
> > @@ -0,0 +1,49 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * mt79xx-afe-common.h -- MediaTek 79xx audio driver definitions
> > + *
> > + * Copyright (c) 2021 MediaTek Inc.
> > + * Author: Vic Wu <[email protected]>
> > + * Maso Huang <[email protected]>
> > + */
> > +
> > +#ifndef _MT_79XX_AFE_COMMON_H_
> > +#define _MT_79XX_AFE_COMMON_H_
> > +
> > +#include <sound/soc.h>
> > +#include <linux/list.h>
> > +#include <linux/regmap.h>
> > +#include "../common/mtk-base-afe.h"
> > +
> > +enum {
> > +MT79XX_MEMIF_DL1,
> > +MT79XX_MEMIF_VUL12,
> > +MT79XX_MEMIF_NUM,
> > +MT79XX_DAI_ETDM = MT79XX_MEMIF_NUM,
> > +MT79XX_DAI_NUM,
> > +};
>
> Same for the enumeration entries, and the definitions and the
> function names.
> Please change everything to `mt7981` (strategy is to use the name of
> the oldest
> SoC: if the oldest is not 7981, change accordingly).
>
The oldest is mt7986, so I'll use mt7986 instead of mt79xx in v2 patch.
> > +
> > +enum {
> > +MT79XX_IRQ_0,
> > +MT79XX_IRQ_1,
> > +MT79XX_IRQ_2,
> > +MT79XX_IRQ_NUM,
> > +};
> > +
> > +struct clk;
> > +
> > +struct mt79xx_afe_private {
> > +struct clk **clk;
> > +
> > +int pm_runtime_bypass_reg_ctl;
> > +
> > +/* dai */
> > +void *dai_priv[MT79XX_DAI_NUM];
> > +};
> > +
> > +unsigned int mt79xx_afe_rate_transform(struct device *dev,
> > + unsigned int rate);
> > +
> > +/* dai register */
> > +int mt79xx_dai_etdm_register(struct mtk_base_afe *afe);
> > +#endif
> > diff --git a/sound/soc/mediatek/mt79xx/mt79xx-reg.h
> b/sound/soc/mediatek/mt79xx/mt79xx-reg.h
> > new file mode 100644
> > index 000000000000..28c0aeba9bdf
> > --- /dev/null
> > +++ b/sound/soc/mediatek/mt79xx/mt79xx-reg.h
> > @@ -0,0 +1,206 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * mt79xx-reg.h -- MediaTek 79xx audio driver reg definition
> > + *
> > + * Copyright (c) 2021 MediaTek Inc.
> > + * Author: Vic Wu <[email protected]>
> > + * Maso Huang <[email protected]>
> > + */
> > +
> > +#ifndef _MT79XX_REG_H_
> > +#define _MT79XX_REG_H_
>
> _MT7981_REG_H_
>
> Everything else looks ok.
>
The oldest is mt7986, so I'll use mt7986 instead of mt79xx in v2 patch.
> Thanks,
> Angelo
>
Best regards,
Maso