2016-03-31 10:28:44

by Jan Glauber

Subject: [PATCH v5 00/14] i2c-octeon and i2c-thunderx drivers

This series for the Octeon i2c driver is an attempt to upstream some
bug fixes and features that accumulated for some time.

On top of the Octeon changes a i2c driver for the ThunderX SOC is
added which uses the same functional block as the Octeon driver.

Patches #1-9 are forward-ports of Octeon features and bugfixes.
Patches #10-12 prepare for the driver split.
Patches #13-14 add the ThunderX driver.

Patches are on top of 4.6-rc1 and were tested on OCTEON, OCTEON-78
and ThunderX.

Changes to v4:
- Splitted the High-Level Controller patch into several patches
- Reworded some commit messages

Changes to v3:
- Added more functionality flags for SMBUS
- Removed both module parameters
- Make xfer return also other errors than EGAIN
- Return EPROTO on invalid SMBUS block length
- Use devm_ioremap_resource
- Added rename-only patch
- Removed kerneldoc patch from series
- Improved defines

Changes to v2:
- Split clenaup patch into several patches
- Strictly moved functional changes to later patches
- Fixed do-while checkpatch errors
- Moved defines to the patches that use them
- Use BIT_ULL macro
- Split ThunderX patch into 2 patches

Changes to v1:
- Fixed compile error on x86_64
- Disabled thunderx driver on MIPS
- Re-ordered some thunderx probe functions for readability
- Fix missing of_irq.h and i2c-smbus.h includes
- Use IS_ENABLED for CONFIG options

Jan

-------------------------------------------------


David Daney (3):
i2c: octeon: Enable High-Level Controller
i2c: octeon: Add support for cn78xx chips
i2c: octeon: Add workaround for broken irqs on CN3860

Jan Glauber (8):
i2c: octeon: Increase retry default and use fixed timeout value
i2c: octeon: Move set-clock and init-lowlevel upward
dt-bindings: i2c: Add Octeon cn78xx TWSI
i2c: octeon: Move read function before write
i2c: octeon: Rename driver to prepare for split
i2c: octeon: Split the driver into two parts
i2c: thunderx: Add i2c driver for ThunderX SOC
i2c: thunderx: Add smbus alert support

Peter Swain (3):
i2c: octeon: Improve error handling
i2c: octeon: Flush TWSI writes with readback
i2c: octeon: Faster operation when IFLG signals late

.../devicetree/bindings/i2c/i2c-octeon.txt | 6 +
drivers/i2c/busses/Kconfig | 10 +
drivers/i2c/busses/Makefile | 3 +
drivers/i2c/busses/i2c-cavium.c | 822 +++++++++++++++++++++
drivers/i2c/busses/i2c-cavium.h | 212 ++++++
drivers/i2c/busses/i2c-octeon-core.c | 283 +++++++
drivers/i2c/busses/i2c-octeon.c | 600 ---------------
drivers/i2c/busses/i2c-thunderx-core.c | 303 ++++++++
8 files changed, 1639 insertions(+), 600 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-cavium.c
create mode 100644 drivers/i2c/busses/i2c-cavium.h
create mode 100644 drivers/i2c/busses/i2c-octeon-core.c
delete mode 100644 drivers/i2c/busses/i2c-octeon.c
create mode 100644 drivers/i2c/busses/i2c-thunderx-core.c

--
1.9.1

2016-03-31 10:28:50

by Jan Glauber

Subject: [PATCH v5 04/14] i2c: octeon: Enable High-Level Controller

From: David Daney <[email protected]>

Use High-Level Controller (HLC) when possible. The HLC can read/write
up to 8 bytes and is completely optional. The most important difference
of the HLC is that it only requires one interrupt for a transfer
(up to 8 bytes) where the low-level read/write requires 2 interrupts plus
one interrupt per transferred byte. Since the interrupts are costly using
the HLC improves the performance. Also, the HLC provides improved error
handling.

Signed-off-by: David Daney <[email protected]>
Signed-off-by: Jan Glauber <[email protected]>
---
drivers/i2c/busses/i2c-octeon.c | 397 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 380 insertions(+), 17 deletions(-)

diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c
index a037245..bc0ed20 100644
--- a/drivers/i2c/busses/i2c-octeon.c
+++ b/drivers/i2c/busses/i2c-octeon.c
@@ -29,13 +29,23 @@
/* Register offsets */
#define SW_TWSI 0x00
#define TWSI_INT 0x10
+#define SW_TWSI_EXT 0x18

/* Controller command patterns */
#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
+#define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */
#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
+#define SW_TWSI_SOVR BIT_ULL(55) /* Size override */
+#define SW_TWSI_SIZE_SHIFT 52
+#define SW_TWSI_ADDR_SHIFT 40
+#define SW_TWSI_IA_SHIFT 32 /* Internal address */

/* Controller opcode word (bits 60:57) */
#define SW_TWSI_OP_SHIFT 57
+#define SW_TWSI_OP_7 (0ULL << SW_TWSI_OP_SHIFT)
+#define SW_TWSI_OP_7_IA (1ULL << SW_TWSI_OP_SHIFT)
+#define SW_TWSI_OP_10 (2ULL << SW_TWSI_OP_SHIFT)
+#define SW_TWSI_OP_10_IA (3ULL << SW_TWSI_OP_SHIFT)
#define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
#define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */

@@ -48,7 +58,7 @@
#define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)

/* Controller command and status bits */
-#define TWSI_CTL_CE 0x80
+#define TWSI_CTL_CE 0x80 /* High level controller enable */
#define TWSI_CTL_ENAB 0x40 /* Bus enable */
#define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
#define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
@@ -87,9 +97,16 @@
#define STAT_IDLE 0xF8

/* TWSI_INT values */
+#define TWSI_INT_ST_INT BIT_ULL(0)
+#define TWSI_INT_TS_INT BIT_ULL(1)
+#define TWSI_INT_CORE_INT BIT_ULL(2)
+#define TWSI_INT_ST_EN BIT_ULL(4)
+#define TWSI_INT_TS_EN BIT_ULL(5)
#define TWSI_INT_CORE_EN BIT_ULL(6)
#define TWSI_INT_SDA_OVR BIT_ULL(8)
#define TWSI_INT_SCL_OVR BIT_ULL(9)
+#define TWSI_INT_SDA BIT_ULL(10)
+#define TWSI_INT_SCL BIT_ULL(11)

struct octeon_i2c {
wait_queue_head_t queue;
@@ -99,6 +116,7 @@ struct octeon_i2c {
int sys_freq;
void __iomem *twsi_base;
struct device *dev;
+ bool hlc_enabled;
};

static int reset_how;
@@ -111,7 +129,7 @@ static int reset_how;
*
* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
*/
-static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
+static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u32 data)
{
u64 tmp;

@@ -122,7 +140,7 @@ static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
}

/**
- * octeon_i2c_read_sw - read lower bits of an I2C core register
+ * octeon_i2c_read_sw64 - read an I2C core register
* @i2c: The struct octeon_i2c
* @eop_reg: Register selector
*
@@ -130,7 +148,7 @@ static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
*
* The I2C core registers are accessed indirectly via the SW_TWSI CSR.
*/
-static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
+static u64 octeon_i2c_read_sw64(struct octeon_i2c *i2c, u64 eop_reg)
{
u64 tmp;

@@ -139,7 +157,21 @@ static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
} while ((tmp & SW_TWSI_V) != 0);

- return tmp & 0xFF;
+ return tmp;
+}
+
+/**
+ * octeon_i2c_read_sw - read lower bits of an I2C core register
+ * @i2c: The struct octeon_i2c
+ * @eop_reg: Register selector
+ *
+ * Returns the data.
+ *
+ * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
+ */
+static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
+{
+ return octeon_i2c_read_sw64(i2c, eop_reg) & 0xFF;
}

/**
@@ -172,6 +204,15 @@ static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
octeon_i2c_write_int(i2c, 0);
}

+static void octeon_i2c_disable_hlc(struct octeon_i2c *i2c)
+{
+ if (!i2c->hlc_enabled)
+ return;
+
+ i2c->hlc_enabled = false;
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
+}
+
/**
* octeon_i2c_unblock - unblock the bus
* @i2c: The struct octeon_i2c
@@ -181,13 +222,18 @@ static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
*/
static void octeon_i2c_unblock(struct octeon_i2c *i2c)
{
- int i;
+ int state, i;

+ octeon_i2c_disable_hlc(i2c);
dev_dbg(i2c->dev, "%s\n", __func__);

+ /* cycle 8+1 clocks with SDA high */
for (i = 0; i < 9; i++) {
octeon_i2c_write_int(i2c, 0);
udelay(5);
+ state = __raw_readq(i2c->twsi_base + TWSI_INT);
+ if (state & (TWSI_INT_SDA | TWSI_INT_SCL))
+ break;
octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);
udelay(5);
}
@@ -210,9 +256,14 @@ static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
return IRQ_HANDLED;
}

+static u64 octeon_i2c_read_ctl(struct octeon_i2c *i2c)
+{
+ return octeon_i2c_read_sw64(i2c, SW_TWSI_EOP_TWSI_CTL);
+}
+
static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
{
- return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
+ return (octeon_i2c_read_ctl(i2c) & TWSI_CTL_IFLG) != 0;
}

/**
@@ -237,6 +288,43 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c)
return 0;
}

+/*
+ * Cleanup low-level state & enable high-level.
+ * Returns -EAGAIN if low-level state could not be cleaned.
+ */
+static int octeon_i2c_enable_hlc(struct octeon_i2c *i2c)
+{
+ int try = 0, ret = 0;
+ u64 val;
+
+ if (i2c->hlc_enabled)
+ return 0;
+ i2c->hlc_enabled = true;
+
+ while (1) {
+ val = octeon_i2c_read_ctl(i2c) & (TWSI_CTL_STA | TWSI_CTL_STP);
+ if (!val)
+ break;
+
+ /* clear IFLG event */
+ if (val & TWSI_CTL_IFLG)
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
+
+ if (try++ > 100) {
+ pr_err("%s: giving up\n", __func__);
+ ret = -EAGAIN;
+ break;
+ }
+
+ /* spin until any start/stop has finished */
+ udelay(10);
+ }
+
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
+ TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);
+ return ret;
+}
+
static int octeon_i2c_lost_arb(u8 code, int final_read)
{
switch (code) {
@@ -297,6 +385,253 @@ static void octeon_i2c_stop(struct octeon_i2c *i2c)
TWSI_CTL_ENAB | TWSI_CTL_STP);
}

+static bool octeon_i2c_hlc_test_ready(struct octeon_i2c *i2c)
+{
+ u64 val = __raw_readq(i2c->twsi_base + SW_TWSI);
+
+ return (val & SW_TWSI_V) == 0;
+}
+
+static void octeon_i2c_hlc_int_enable(struct octeon_i2c *i2c)
+{
+ octeon_i2c_write_int(i2c, TWSI_INT_ST_EN);
+}
+
+static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
+{
+ /* clear ST/TS events, listen for neither */
+ octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);
+}
+
+/**
+ * octeon_i2c_hlc_wait - wait for an HLC operation to complete
+ * @i2c: The struct octeon_i2c
+ *
+ * Returns 0 on success, otherwise a negative errno.
+ */
+static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
+{
+ int time_left;
+
+ octeon_i2c_hlc_int_enable(i2c);
+ time_left = wait_event_interruptible_timeout(i2c->queue,
+ octeon_i2c_hlc_test_ready(i2c),
+ i2c->adap.timeout);
+ octeon_i2c_int_disable(i2c);
+ if (!time_left) {
+ octeon_i2c_hlc_int_clear(i2c);
+ dev_dbg(i2c->dev, "%s: timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ if (time_left < 0) {
+ dev_dbg(i2c->dev, "%s: wait interrupted\n", __func__);
+ return time_left;
+ }
+ return 0;
+}
+
+/* high-level-controller pure read of up to 8 bytes */
+static int octeon_i2c_simple_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
+{
+ int i, j, ret = 0;
+ u64 cmd;
+
+ octeon_i2c_enable_hlc(i2c);
+ cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
+ /* SIZE */
+ cmd |= (u64) (msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
+ /* A */
+ cmd |= (u64) (msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
+
+ if (msgs[0].flags & I2C_M_TEN)
+ cmd |= SW_TWSI_OP_10;
+ else
+ cmd |= SW_TWSI_OP_7;
+
+ octeon_i2c_hlc_int_clear(i2c);
+ __raw_writeq(cmd, i2c->twsi_base + SW_TWSI);
+
+ ret = octeon_i2c_hlc_wait(i2c);
+ if (ret)
+ goto err;
+
+ cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
+ if ((cmd & SW_TWSI_R) == 0)
+ return -EAGAIN;
+
+ for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
+ msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
+
+ if (msgs[0].len > 4) {
+ cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT);
+ for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
+ msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
+ }
+
+err:
+ return ret;
+}
+
+/* high-level-controller pure write of up to 8 bytes */
+static int octeon_i2c_simple_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
+{
+ int i, j, ret = 0;
+ u64 cmd;
+
+ octeon_i2c_enable_hlc(i2c);
+ octeon_i2c_hlc_int_clear(i2c);
+
+ ret = check_arb(i2c, false);
+ if (ret)
+ goto err;
+
+ cmd = SW_TWSI_V | SW_TWSI_SOVR;
+ /* SIZE */
+ cmd |= (u64) (msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
+ /* A */
+ cmd |= (u64) (msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
+
+ if (msgs[0].flags & I2C_M_TEN)
+ cmd |= SW_TWSI_OP_10;
+ else
+ cmd |= SW_TWSI_OP_7;
+
+ for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
+ cmd |= (u64)msgs[0].buf[j] << (8 * i);
+
+ if (msgs[0].len > 4) {
+ u64 ext = 0;
+
+ for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
+ ext |= (u64) msgs[0].buf[j] << (8 * i);
+ __raw_writeq(ext, i2c->twsi_base + SW_TWSI_EXT);
+ }
+
+ __raw_writeq(cmd, i2c->twsi_base + SW_TWSI);
+
+ ret = octeon_i2c_hlc_wait(i2c);
+ if (ret)
+ goto err;
+
+ cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
+ if ((cmd & SW_TWSI_R) == 0)
+ return -EAGAIN;
+
+ ret = check_arb(i2c, false);
+
+err:
+ return ret;
+}
+
+/* high-level-controller composite write+read, msg0=addr, msg1=data */
+static int octeon_i2c_ia_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
+{
+ int i, j, ret = 0;
+ u64 cmd;
+
+ octeon_i2c_enable_hlc(i2c);
+
+ cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
+ /* SIZE */
+ cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
+ /* A */
+ cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
+
+ if (msgs[0].flags & I2C_M_TEN)
+ cmd |= SW_TWSI_OP_10_IA;
+ else
+ cmd |= SW_TWSI_OP_7_IA;
+
+ if (msgs[0].len == 2) {
+ u64 ext = 0;
+
+ cmd |= SW_TWSI_EIA;
+ ext = (u64) msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
+ cmd |= (u64) msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
+ __raw_writeq(ext, i2c->twsi_base + SW_TWSI_EXT);
+ } else
+ cmd |= (u64) msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
+
+ octeon_i2c_hlc_int_clear(i2c);
+ __raw_writeq(cmd, i2c->twsi_base + SW_TWSI);
+
+ ret = octeon_i2c_hlc_wait(i2c);
+ if (ret)
+ goto err;
+
+ cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
+ if ((cmd & SW_TWSI_R) == 0)
+ return -EAGAIN;
+
+ for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
+ msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
+
+ if (msgs[1].len > 4) {
+ cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT);
+ for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
+ msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
+ }
+
+err:
+ return ret;
+}
+
+/* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
+static int octeon_i2c_ia_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
+{
+ bool set_ext = false;
+ int i, j, ret = 0;
+ u64 cmd, ext = 0;
+
+ octeon_i2c_enable_hlc(i2c);
+
+ cmd = SW_TWSI_V | SW_TWSI_SOVR;
+ /* SIZE */
+ cmd |= (u64) (msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
+ /* A */
+ cmd |= (u64) (msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
+
+ if (msgs[0].flags & I2C_M_TEN)
+ cmd |= SW_TWSI_OP_10_IA;
+ else
+ cmd |= SW_TWSI_OP_7_IA;
+
+ if (msgs[0].len == 2) {
+ cmd |= SW_TWSI_EIA;
+ ext |= (u64) msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
+ set_ext = true;
+ cmd |= (u64) msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
+ } else
+ cmd |= (u64) msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
+
+ for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
+ cmd |= (u64) msgs[1].buf[j] << (8 * i);
+
+ if (msgs[1].len > 4) {
+ for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
+ ext |= (u64)msgs[1].buf[j] << (8 * i);
+ set_ext = true;
+ }
+ if (set_ext)
+ __raw_writeq(ext, i2c->twsi_base + SW_TWSI_EXT);
+
+ octeon_i2c_hlc_int_clear(i2c);
+ __raw_writeq(cmd, i2c->twsi_base + SW_TWSI);
+
+ ret = octeon_i2c_hlc_wait(i2c);
+ if (ret)
+ goto err;
+
+ cmd = octeon_i2c_read_sw64(i2c, SW_TWSI_EOP_TWSI_STAT);
+ if ((cmd & SW_TWSI_R) == 0)
+ return -EAGAIN;
+ ret = octeon_i2c_lost_arb(cmd, false);
+
+err:
+ return ret;
+}
+
/* calculate and set clock divisors */
static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
{
@@ -341,23 +676,27 @@ static void octeon_i2c_set_clock(struct octeon_i2c *i2c)

static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
{
- u8 status;
+ u8 status = 0;
int tries;

- /* disable high level controller, enable bus access */
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
-
/* reset controller */
octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);

- for (tries = 10; tries; tries--) {
+ for (tries = 10; tries && status != STAT_IDLE; tries--) {
udelay(1);
status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
- if (status == STAT_IDLE)
- return 0;
}
- dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
- return -EIO;
+
+ if (status != STAT_IDLE) {
+ dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",
+ __func__, status);
+ return -EIO;
+ }
+
+ /* toggle twice to force both teardowns */
+ octeon_i2c_enable_hlc(i2c);
+ octeon_i2c_disable_hlc(i2c);
+ return 0;
}

/*
@@ -408,6 +747,8 @@ static int octeon_i2c_start(struct octeon_i2c *i2c, int first)
int result;
u8 data;

+ octeon_i2c_disable_hlc(i2c);
+
while (1) {
octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
TWSI_CTL_ENAB | TWSI_CTL_STA);
@@ -565,6 +906,28 @@ static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
struct octeon_i2c *i2c = i2c_get_adapdata(adap);
int i, ret = 0;

+ if (num == 1) {
+ if (msgs[0].len > 0 && msgs[0].len <= 8) {
+ if (msgs[0].flags & I2C_M_RD)
+ ret = octeon_i2c_simple_read(i2c, msgs);
+ else
+ ret = octeon_i2c_simple_write(i2c, msgs);
+ goto out;
+ }
+ } else if (num == 2) {
+ if ((msgs[0].flags & I2C_M_RD) == 0 &&
+ (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
+ msgs[0].len > 0 && msgs[0].len <= 2 &&
+ msgs[1].len > 0 && msgs[1].len <= 8 &&
+ msgs[0].addr == msgs[1].addr) {
+ if (msgs[1].flags & I2C_M_RD)
+ ret = octeon_i2c_ia_read(i2c, msgs);
+ else
+ ret = octeon_i2c_ia_write(i2c, msgs);
+ goto out;
+ }
+ }
+
for (i = 0; ret == 0 && i < num; i++) {
struct i2c_msg *pmsg = &msgs[i];
bool last = (i == (num - 1));
@@ -582,7 +945,7 @@ static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
pmsg->len, !i, last);
}
octeon_i2c_stop(i2c);
-
+out:
return (ret != 0) ? ret : num;
}

--
1.9.1

2016-03-31 10:28:53

by Jan Glauber

Subject: [PATCH v5 08/14] i2c: octeon: Faster operation when IFLG signals late

From: Peter Swain <[email protected]>

Some versions can deliver low-level twsi irq before twsi_ctl.iflg
is set, leading to timeout-driven i/o.
When an irq signals event, but woken task does not see the expected
twsi_ctl.iflg, re-check about 80uS later.

EEPROM reads on 100kHz i2c now measure ~5.2kB/s, about 1/2 what's
achievable, and much better than the worst-case 100 bytes/sec before.

Signed-off-by: Peter Swain <[email protected]>
Signed-off-by: Jan Glauber <[email protected]>
Acked-by: David Daney <[email protected]>
---
drivers/i2c/busses/i2c-octeon.c | 25 ++++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c
index 44ce9d4..cc1fe51 100644
--- a/drivers/i2c/busses/i2c-octeon.c
+++ b/drivers/i2c/busses/i2c-octeon.c
@@ -342,6 +342,28 @@ static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
return (octeon_i2c_read_ctl(i2c) & TWSI_CTL_IFLG) != 0;
}

+#define I2C_OCTEON_IFLG_WAIT 80 /* microseconds */
+
+/*
+ * Wait-helper which addresses the delayed-IFLAG problem by re-polling for
+ * missing TWSI_CTL[IFLG] a few us later, when irq has signalled an event,
+ * but none found. Skip this re-poll on the first (non-wakeup) call.
+ */
+static int poll_iflg(struct octeon_i2c *i2c, int *first_p)
+{
+ int iflg = octeon_i2c_test_iflg(i2c);
+
+ if (iflg)
+ return 1;
+ if (*first_p)
+ *first_p = 0;
+ else {
+ usleep_range(I2C_OCTEON_IFLG_WAIT, 2 * I2C_OCTEON_IFLG_WAIT);
+ iflg = octeon_i2c_test_iflg(i2c);
+ }
+ return iflg;
+}
+
/**
* octeon_i2c_wait - wait for the IFLG to be set
* @i2c: The struct octeon_i2c
@@ -351,9 +373,10 @@ static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
static int octeon_i2c_wait(struct octeon_i2c *i2c)
{
long time_left;
+ int first = 1;

i2c->int_en(i2c);
- time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),
+ time_left = wait_event_timeout(i2c->queue, poll_iflg(i2c, &first),
i2c->adap.timeout);
i2c->int_dis(i2c);
if (!time_left) {
--
1.9.1

2016-03-31 10:29:00

by Jan Glauber

Subject: [PATCH v5 13/14] i2c: thunderx: Add i2c driver for ThunderX SOC

The ThunderX SOC uses the same i2c block as the Octeon SOC.
The main difference is that on ThunderX the device is a PCI device
so device probing is done via PCI, interrupts are MSIX and the
clock is taken from device tree.

Signed-off-by: Jan Glauber <[email protected]>
---
drivers/i2c/busses/Kconfig | 10 ++
drivers/i2c/busses/Makefile | 2 +
drivers/i2c/busses/i2c-cavium.h | 17 ++-
drivers/i2c/busses/i2c-thunderx-core.c | 268 +++++++++++++++++++++++++++++++++
4 files changed, 294 insertions(+), 3 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-thunderx-core.c

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index faa8e68..92d23de 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -953,6 +953,16 @@ config I2C_OCTEON
This driver can also be built as a module. If so, the module
will be called i2c-octeon.

+config I2C_THUNDERX
+ tristate "Cavium ThunderX I2C bus support"
+ depends on 64BIT && PCI && !CAVIUM_OCTEON_SOC
+ help
+ Say yes if you want to support the I2C serial bus on Cavium
+ ThunderX SOC.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-thunderx.
+
config I2C_XILINX
tristate "Xilinx I2C Controller"
depends on HAS_IOMEM
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 282f781..a32ff14 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -93,6 +93,8 @@ obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_WMT) += i2c-wmt.o
i2c-octeon-objs := i2c-cavium.o i2c-octeon-core.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
+i2c-thunderx-objs := i2c-cavium.o i2c-thunderx-core.o
+obj-$(CONFIG_I2C_THUNDERX) += i2c-thunderx.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
diff --git a/drivers/i2c/busses/i2c-cavium.h b/drivers/i2c/busses/i2c-cavium.h
index 7f78bf0..31608c4 100644
--- a/drivers/i2c/busses/i2c-cavium.h
+++ b/drivers/i2c/busses/i2c-cavium.h
@@ -8,9 +8,15 @@
#include <linux/pci.h>

/* Register offsets */
-#define SW_TWSI 0x00
-#define TWSI_INT 0x10
-#define SW_TWSI_EXT 0x18
+#if IS_ENABLED(CONFIG_I2C_THUNDERX)
+ #define SW_TWSI 0x1000
+ #define TWSI_INT 0x1010
+ #define SW_TWSI_EXT 0x1018
+#else
+ #define SW_TWSI 0x00
+ #define TWSI_INT 0x10
+ #define SW_TWSI_EXT 0x18
+#endif

/* Controller command patterns */
#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
@@ -92,6 +98,7 @@
struct octeon_i2c {
wait_queue_head_t queue;
struct i2c_adapter adap;
+ struct clk *clk;
int irq;
int hlc_irq; /* For cn7890 only */
u32 twsi_freq;
@@ -107,6 +114,10 @@ struct octeon_i2c {
void (*hlc_int_dis)(struct octeon_i2c *);
atomic_t int_en_cnt;
atomic_t hlc_int_en_cnt;
+
+#if IS_ENABLED(CONFIG_I2C_THUNDERX)
+ struct msix_entry i2c_msix;
+#endif
};

static inline void writeqflush(u64 val, void __iomem *addr)
diff --git a/drivers/i2c/busses/i2c-thunderx-core.c b/drivers/i2c/busses/i2c-thunderx-core.c
new file mode 100644
index 0000000..2ce985b
--- /dev/null
+++ b/drivers/i2c/busses/i2c-thunderx-core.c
@@ -0,0 +1,268 @@
+/*
+ * Cavium ThunderX i2c driver.
+ *
+ * Copyright (C) 2015,2016 Cavium Inc.
+ * Authors: Fred Martin <[email protected]>
+ * Jan Glauber <[email protected]>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+
+#include "i2c-cavium.h"
+
+#define DRV_NAME "i2c-thunderx"
+
+#define PCI_CFG_REG_BAR_NUM 0
+#define PCI_DEVICE_ID_THUNDER_TWSI 0xa012
+
+#define TWSI_DFL_RATE 100000
+#define SYS_FREQ_DEFAULT 800000000
+
+#define TWSI_INT_ENA_W1C 0x1028
+#define TWSI_INT_ENA_W1S 0x1030
+
+/*
+ * Enable the CORE interrupt.
+ * The interrupt will be asserted when there is non-STAT_IDLE state in the
+ * SW_TWSI_EOP_TWSI_STAT register.
+ */
+static void thunder_i2c_int_enable(struct octeon_i2c *i2c)
+{
+ __raw_writeq(TWSI_INT_CORE_INT, i2c->twsi_base + TWSI_INT_ENA_W1S);
+ __raw_readq(i2c->twsi_base + TWSI_INT_ENA_W1S);
+}
+
+/*
+ * Disable the CORE interrupt.
+ */
+static void thunder_i2c_int_disable(struct octeon_i2c *i2c)
+{
+ __raw_writeq(TWSI_INT_CORE_INT, i2c->twsi_base + TWSI_INT_ENA_W1C);
+ __raw_readq(i2c->twsi_base + TWSI_INT_ENA_W1C);
+}
+
+static void thunder_i2c_hlc_int_enable(struct octeon_i2c *i2c)
+{
+ __raw_writeq(TWSI_INT_ST_INT | TWSI_INT_TS_INT,
+ i2c->twsi_base + TWSI_INT_ENA_W1S);
+ __raw_readq(i2c->twsi_base + TWSI_INT_ENA_W1S);
+}
+
+static void thunder_i2c_hlc_int_disable(struct octeon_i2c *i2c)
+{
+ __raw_writeq(TWSI_INT_ST_INT | TWSI_INT_TS_INT,
+ i2c->twsi_base + TWSI_INT_ENA_W1C);
+ __raw_readq(i2c->twsi_base + TWSI_INT_ENA_W1C);
+}
+
+static u32 thunderx_i2c_functionality(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
+ I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_SMBUS_BLOCK_PROC_CALL;
+}
+
+static const struct i2c_algorithm thunderx_i2c_algo = {
+ .master_xfer = octeon_i2c_xfer,
+ .functionality = thunderx_i2c_functionality,
+};
+
+static struct i2c_adapter thunderx_i2c_ops = {
+ .owner = THIS_MODULE,
+ .name = "ThunderX adapter",
+ .algo = &thunderx_i2c_algo,
+};
+
+static void thunder_i2c_clock_enable(struct device *dev, struct octeon_i2c *i2c)
+{
+ int ret;
+
+ i2c->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(i2c->clk)) {
+ i2c->clk = NULL;
+ goto skip;
+ }
+
+ ret = clk_prepare_enable(i2c->clk);
+ if (ret)
+ goto skip;
+ i2c->sys_freq = clk_get_rate(i2c->clk);
+
+skip:
+ if (!i2c->sys_freq)
+ i2c->sys_freq = SYS_FREQ_DEFAULT;
+
+ dev_info(dev, "Set system clock to %u\n", i2c->sys_freq);
+}
+
+static void thunder_i2c_clock_disable(struct device *dev, struct clk *clk)
+{
+ if (!clk)
+ return;
+ clk_disable_unprepare(clk);
+ devm_clk_put(dev, clk);
+}
+
+static void thunder_i2c_set_name(struct pci_dev *pdev, struct octeon_i2c *i2c,
+ char *name)
+{
+ u8 i2c_bus_id, soc_node;
+ resource_size_t start;
+
+ start = pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM);
+ soc_node = (start >> 44) & 0x3;
+ i2c_bus_id = (start >> 24) & 0x7;
+ snprintf(name, 10, "i2c%d", soc_node * 6 + i2c_bus_id);
+
+ snprintf(i2c->adap.name, sizeof(i2c->adap.name), "thunderx-i2c-%d.%d",
+ soc_node, i2c_bus_id);
+}
+
+static int thunder_i2c_probe_pci(struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = NULL;
+ struct octeon_i2c *i2c;
+ char i2c_name[10];
+ int ret = 0;
+
+ i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
+ if (!i2c)
+ return -ENOMEM;
+
+ i2c->dev = dev;
+ pci_set_drvdata(pdev, i2c);
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ dev_err(dev, "Failed to enable PCI device\n");
+ goto out_free_i2c;
+ }
+
+ ret = pci_request_regions(pdev, DRV_NAME);
+ if (ret) {
+ dev_err(dev, "PCI request regions failed 0x%x\n", ret);
+ goto out_disable_device;
+ }
+
+ i2c->twsi_base = pci_ioremap_bar(pdev, PCI_CFG_REG_BAR_NUM);
+ if (!i2c->twsi_base) {
+ dev_err(dev, "Cannot map CSR memory space\n");
+ ret = -EINVAL;
+ goto out_release_regions;
+ }
+
+ thunder_i2c_clock_enable(dev, i2c);
+
+ thunder_i2c_set_name(pdev, i2c, i2c_name);
+ node = of_find_node_by_name(NULL, i2c_name);
+ if (!node || of_property_read_u32(node, "clock-frequency",
+ &i2c->twsi_freq))
+ i2c->twsi_freq = TWSI_DFL_RATE;
+
+ init_waitqueue_head(&i2c->queue);
+
+ i2c->int_en = thunder_i2c_int_enable;
+ i2c->int_dis = thunder_i2c_int_disable;
+ i2c->hlc_int_en = thunder_i2c_hlc_int_enable;
+ i2c->hlc_int_dis = thunder_i2c_hlc_int_disable;
+
+ ret = pci_enable_msix(pdev, &i2c->i2c_msix, 1);
+ if (ret) {
+ dev_err(dev, "Unable to enable MSI-X\n");
+ goto out_unmap;
+ }
+
+ ret = devm_request_irq(dev, i2c->i2c_msix.vector, octeon_i2c_isr, 0,
+ DRV_NAME, i2c);
+ if (ret < 0) {
+ dev_err(dev, "Failed to attach i2c interrupt\n");
+ goto out_msix;
+ }
+
+ ret = octeon_i2c_init_lowlevel(i2c);
+ if (ret) {
+ dev_err(dev, "Init low level failed\n");
+ goto out_msix;
+ }
+
+ octeon_i2c_set_clock(i2c);
+
+ i2c->adap = thunderx_i2c_ops;
+ i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
+ i2c->adap.timeout = msecs_to_jiffies(5);
+ i2c->adap.retries = 5;
+ i2c->adap.dev.parent = dev;
+ i2c->adap.dev.of_node = pdev->dev.of_node;
+ i2c_set_adapdata(&i2c->adap, i2c);
+
+ ret = i2c_add_adapter(&i2c->adap);
+ if (ret < 0) {
+ dev_err(dev, "Failed to add i2c adapter\n");
+ goto out_irq;
+ }
+
+ dev_info(i2c->dev, "probed\n");
+ return 0;
+
+out_irq:
+ devm_free_irq(dev, i2c->i2c_msix.vector, i2c);
+out_msix:
+ pci_disable_msix(pdev);
+out_unmap:
+ iounmap(i2c->twsi_base);
+ thunder_i2c_clock_disable(dev, i2c->clk);
+out_release_regions:
+ pci_release_regions(pdev);
+out_disable_device:
+ pci_disable_device(pdev);
+out_free_i2c:
+ pci_set_drvdata(pdev, NULL);
+ devm_kfree(dev, i2c);
+ return ret;
+}
+
+static void thunder_i2c_remove_pci(struct pci_dev *pdev)
+{
+ struct octeon_i2c *i2c = pci_get_drvdata(pdev);
+ struct device *dev;
+
+ if (!i2c)
+ return;
+
+ dev = i2c->dev;
+ thunder_i2c_clock_disable(dev, i2c->clk);
+ i2c_del_adapter(&i2c->adap);
+ devm_free_irq(dev, i2c->i2c_msix.vector, i2c);
+ pci_disable_msix(pdev);
+ iounmap(i2c->twsi_base);
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+ pci_set_drvdata(pdev, NULL);
+ devm_kfree(dev, i2c);
+}
+
+static const struct pci_device_id thunder_i2c_pci_id_table[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_TWSI) },
+ { 0, }
+};
+
+MODULE_DEVICE_TABLE(pci, thunder_i2c_pci_id_table);
+
+static struct pci_driver thunder_i2c_pci_driver = {
+ .name = DRV_NAME,
+ .id_table = thunder_i2c_pci_id_table,
+ .probe = thunder_i2c_probe_pci,
+ .remove = thunder_i2c_remove_pci,
+};
+
+module_pci_driver(thunder_i2c_pci_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Fred Martin <[email protected]>");
+MODULE_DESCRIPTION("I2C-Bus adapter for Cavium ThunderX SOC");
--
1.9.1

2016-03-31 10:29:06

by Jan Glauber

Subject: [PATCH v5 12/14] i2c: octeon: Split the driver into two parts

Move common functionality into a separate file in preparation of the
re-use from the ThunderX i2c driver.

Signed-off-by: Jan Glauber <[email protected]>
---
drivers/i2c/busses/Makefile | 3 +-
drivers/i2c/busses/i2c-cavium.c | 822 +++++++++++++++++++++++++++++
drivers/i2c/busses/i2c-cavium.h | 195 +++++++
drivers/i2c/busses/i2c-octeon-core.c | 983 +----------------------------------
4 files changed, 1020 insertions(+), 983 deletions(-)
create mode 100644 drivers/i2c/busses/i2c-cavium.c
create mode 100644 drivers/i2c/busses/i2c-cavium.h

diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 3405286..282f781 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -91,7 +91,8 @@ obj-$(CONFIG_I2C_UNIPHIER) += i2c-uniphier.o
obj-$(CONFIG_I2C_UNIPHIER_F) += i2c-uniphier-f.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_WMT) += i2c-wmt.o
-obj-$(CONFIG_I2C_OCTEON) += i2c-octeon-core.o
+i2c-octeon-objs := i2c-cavium.o i2c-octeon-core.o
+obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
diff --git a/drivers/i2c/busses/i2c-cavium.c b/drivers/i2c/busses/i2c-cavium.c
new file mode 100644
index 0000000..9ad1f23
--- /dev/null
+++ b/drivers/i2c/busses/i2c-cavium.c
@@ -0,0 +1,822 @@
+/*
+ * (C) Copyright 2009-2010
+ * Nokia Siemens Networks, [email protected]
+ *
+ * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
+ *
+ * This file contains the shared part of the driver for the i2c adapter in
+ * Cavium Networks' OCTEON processors and ThunderX SOCs.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include "i2c-cavium.h"
+
+static int reset_how;
+
+/* interrupt service routine */
+irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
+{
+ struct octeon_i2c *i2c = dev_id;
+
+ i2c->int_dis(i2c);
+ wake_up(&i2c->queue);
+
+ return IRQ_HANDLED;
+}
+
+static void octeon_i2c_disable_hlc(struct octeon_i2c *i2c)
+{
+ if (!i2c->hlc_enabled)
+ return;
+
+ i2c->hlc_enabled = false;
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
+}
+
+#define I2C_OCTEON_IFLG_WAIT 80 /* microseconds */
+
+/*
+ * Wait-helper which addresses the delayed-IFLAG problem by re-polling for
+ * missing TWSI_CTL[IFLG] a few us later, when irq has signalled an event,
+ * but none found. Skip this re-poll on the first (non-wakeup) call.
+ */
+static int poll_iflg(struct octeon_i2c *i2c, int *first_p)
+{
+ int iflg = octeon_i2c_test_iflg(i2c);
+
+ if (iflg)
+ return 1;
+ if (*first_p)
+ *first_p = 0;
+ else {
+ usleep_range(I2C_OCTEON_IFLG_WAIT, 2 * I2C_OCTEON_IFLG_WAIT);
+ iflg = octeon_i2c_test_iflg(i2c);
+ }
+ return iflg;
+}
+
+/**
+ * octeon_i2c_wait - wait for the IFLG to be set
+ * @i2c: The struct octeon_i2c
+ *
+ * Returns 0 on success, otherwise a negative errno.
+ */
+static int octeon_i2c_wait(struct octeon_i2c *i2c)
+{
+ long time_left;
+ int first = 1;
+
+ if (i2c->broken_irq_mode) {
+ /*
+ * Some chip revisions seem to not assert the irq in
+ * the interrupt controller. So we must poll for the
+ * IFLG change.
+ */
+ u64 end = get_jiffies_64() + i2c->adap.timeout;
+
+ while (!octeon_i2c_test_iflg(i2c) &&
+ time_before64(get_jiffies_64(), end))
+ udelay(50);
+
+ return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT;
+ }
+
+ i2c->int_en(i2c);
+ time_left = wait_event_timeout(i2c->queue, poll_iflg(i2c, &first),
+ i2c->adap.timeout);
+ i2c->int_dis(i2c);
+
+ if (time_left <= 0 && i2c->broken_irq_check &&
+ octeon_i2c_test_iflg(i2c)) {
+ dev_err(i2c->dev,
+ "broken irq connection detected, switching to polling mode.\n");
+ i2c->broken_irq_mode = true;
+ return 0;
+ }
+ if (!time_left) {
+ dev_dbg(i2c->dev, "%s: timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/*
+ * Cleanup low-level state & enable high-level.
+ * Returns -EAGAIN if low-level state could not be cleaned.
+ */
+static int octeon_i2c_enable_hlc(struct octeon_i2c *i2c)
+{
+ int try = 0, ret = 0;
+ u64 val;
+
+ if (i2c->hlc_enabled)
+ return 0;
+ i2c->hlc_enabled = true;
+
+ while (1) {
+ val = octeon_i2c_read_ctl(i2c) & (TWSI_CTL_STA | TWSI_CTL_STP);
+ if (!val)
+ break;
+
+ /* clear IFLG event */
+ if (val & TWSI_CTL_IFLG)
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
+
+ if (try++ > 100) {
+ pr_err("%s: giving up\n", __func__);
+ ret = -EAGAIN;
+ break;
+ }
+
+ /* spin until any start/stop has finished */
+ udelay(10);
+ }
+
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
+ TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);
+ return ret;
+}
+
+static int octeon_i2c_lost_arb(u8 code, int final_read)
+{
+ switch (code) {
+ /* Arbitration lost */
+ case STAT_LOST_ARB_38:
+ case STAT_LOST_ARB_68:
+ case STAT_LOST_ARB_78:
+ case STAT_LOST_ARB_B0:
+ return -EAGAIN;
+
+ /* Being addressed as slave, should back off & listen */
+ case STAT_SLAVE_60:
+ case STAT_SLAVE_70:
+ case STAT_GENDATA_ACK:
+ case STAT_GENDATA_NAK:
+ return -EIO;
+
+ /* Core busy as slave */
+ case STAT_SLAVE_80:
+ case STAT_SLAVE_88:
+ case STAT_SLAVE_A0:
+ case STAT_SLAVE_A8:
+ case STAT_SLAVE_LOST:
+ case STAT_SLAVE_NAK:
+ case STAT_SLAVE_ACK:
+ return -EIO;
+
+ /* ACK allowed on pre-terminal bytes only */
+ case STAT_RXDATA_ACK:
+ if (!final_read)
+ return 0;
+ return -EAGAIN;
+
+ /* NAK allowed on terminal byte only */
+ case STAT_RXDATA_NAK:
+ if (final_read)
+ return 0;
+ return -EAGAIN;
+ case STAT_TXDATA_NAK:
+ case STAT_TXADDR_NAK:
+ case STAT_RXADDR_NAK:
+ case STAT_AD2W_NAK:
+ return -EAGAIN;
+ }
+ return 0;
+}
+
+static int check_arb(struct octeon_i2c *i2c, int final_read)
+{
+ return octeon_i2c_lost_arb(octeon_i2c_read_sw(i2c,
+ SW_TWSI_EOP_TWSI_STAT), final_read);
+}
+
+/* send STOP to the bus */
+static void octeon_i2c_stop(struct octeon_i2c *i2c)
+{
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
+ TWSI_CTL_ENAB | TWSI_CTL_STP);
+}
+
+/**
+ * octeon_i2c_unblock - unblock the bus
+ * @i2c: The struct octeon_i2c
+ *
+ * If there was a reset while a device was driving 0 to bus, bus is blocked.
+ * We toggle it free manually by some clock cycles and send a stop.
+ */
+static void octeon_i2c_unblock(struct octeon_i2c *i2c)
+{
+ int state, i;
+
+ octeon_i2c_disable_hlc(i2c);
+ dev_dbg(i2c->dev, "%s\n", __func__);
+
+ /* cycle 8+1 clocks with SDA high */
+ for (i = 0; i < 9; i++) {
+ octeon_i2c_write_int(i2c, 0);
+ udelay(5);
+ state = __raw_readq(i2c->twsi_base + TWSI_INT);
+ if (state & (TWSI_INT_SDA | TWSI_INT_SCL))
+ break;
+ octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);
+ udelay(5);
+ }
+ /* hand-crank a STOP */
+ octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);
+ udelay(5);
+ octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);
+ udelay(5);
+ octeon_i2c_write_int(i2c, 0);
+}
+
+/*
+ * TWSI state seems stuck. Not sure if it's TWSI-engine state or something
+ * else on bus. The initial _stop() is always harmless, it just resets state
+ * machine, does not _transmit_ STOP unless engine was active.
+ */
+static int start_unstick(struct octeon_i2c *i2c)
+{
+ octeon_i2c_stop(i2c);
+
+ /*
+ * Response is escalated over successive calls,
+ * as EAGAIN provokes retries from i2c/core.
+ */
+ switch (reset_how++ % 4) {
+ case 0:
+ /* just the stop above */
+ break;
+ case 1:
+ /*
+ * Controller refused to send start flag. May be a
+ * client is holding SDA low? Let's try to free it.
+ */
+ octeon_i2c_unblock(i2c);
+ break;
+ case 2:
+ /* re-init our TWSI hardware */
+ octeon_i2c_init_lowlevel(i2c);
+ break;
+ default:
+ /* retry in caller */
+ reset_how = 0;
+ return -EAGAIN;
+ }
+ return 0;
+}
+
+/**
+ * octeon_i2c_start - send START to the bus
+ * @i2c: The struct octeon_i2c
+ * @first: first msg in combined operation?
+ *
+ * Returns 0 on success, otherwise a negative errno.
+ */
+static int octeon_i2c_start(struct octeon_i2c *i2c, int first)
+{
+ int result;
+ u8 data;
+
+ octeon_i2c_disable_hlc(i2c);
+
+ while (1) {
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
+ TWSI_CTL_ENAB | TWSI_CTL_STA);
+
+ result = octeon_i2c_wait(i2c);
+ data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
+
+ switch (data) {
+ case STAT_START:
+ case STAT_RSTART:
+ if (!first)
+ return -EAGAIN;
+ reset_how = 0;
+ return 0;
+ case STAT_RXADDR_ACK:
+ if (first)
+ return -EAGAIN;
+ return start_unstick(i2c);
+ /*
+ * case STAT_IDLE:
+ * case STAT_ERROR:
+ */
+ default:
+ if (!first)
+ return -EAGAIN;
+ start_unstick(i2c);
+ }
+ }
+ return 0;
+}
+
+static bool octeon_i2c_hlc_test_ready(struct octeon_i2c *i2c)
+{
+ u64 val = __raw_readq(i2c->twsi_base + SW_TWSI);
+
+ return (val & SW_TWSI_V) == 0;
+}
+
+static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
+{
+ /* clear ST/TS events, listen for neither */
+ octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);
+}
+
+/**
+ * octeon_i2c_hlc_wait - wait for an HLC operation to complete
+ * @i2c: The struct octeon_i2c
+ *
+ * Returns 0 on success, otherwise a negative errno.
+ */
+static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
+{
+ int time_left;
+
+ if (i2c->broken_irq_mode) {
+ /*
+ * Some cn38xx boards did not assert the irq in
+ * the interrupt controller. So we must poll for the
+ * IFLG change.
+ */
+ u64 end = get_jiffies_64() + i2c->adap.timeout;
+
+ while (!octeon_i2c_hlc_test_ready(i2c) &&
+ time_before64(get_jiffies_64(), end))
+ udelay(50);
+
+ return octeon_i2c_hlc_test_ready(i2c) ? 0 : -ETIMEDOUT;
+ }
+
+ i2c->hlc_int_en(i2c);
+ time_left = wait_event_interruptible_timeout(i2c->queue,
+ octeon_i2c_hlc_test_ready(i2c),
+ i2c->adap.timeout);
+ i2c->hlc_int_dis(i2c);
+ if (!time_left)
+ octeon_i2c_hlc_int_clear(i2c);
+
+ if (time_left <= 0 && i2c->broken_irq_check &&
+ octeon_i2c_hlc_test_ready(i2c)) {
+ dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
+ i2c->broken_irq_mode = true;
+ return 0;
+ }
+
+ if (!time_left) {
+ dev_dbg(i2c->dev, "%s: timeout\n", __func__);
+ return -ETIMEDOUT;
+ }
+ if (time_left < 0) {
+ dev_dbg(i2c->dev, "%s: wait interrupted\n", __func__);
+ return time_left;
+ }
+ return 0;
+}
+
+/**
+ * octeon_i2c_read - receive data from the bus via low-level controller
+ * @i2c: The struct octeon_i2c
+ * @target: Target address
+ * @data: Pointer to the location to store the data
+ * @rlength: Length of the data
+ * @phase: which phase of a combined operation.
+ * @recv_len: flag for length byte
+ *
+ * The address is sent over the bus, then the data is read.
+ *
+ * Returns 0 on success, otherwise a negative errno.
+ */
+static int octeon_i2c_read(struct octeon_i2c *i2c, int target, u8 *data,
+ u16 *rlength, bool first, bool last, bool recv_len)
+{
+ u8 ctl = TWSI_CTL_ENAB | TWSI_CTL_AAK;
+ int i, result, length = *rlength;
+ u8 tmp;
+
+ if (length < 1)
+ return -EINVAL;
+
+ result = octeon_i2c_start(i2c, first);
+ if (result)
+ return result;
+
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) | 1);
+
+ for (i = 0; i < length; ) {
+ tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
+ result = octeon_i2c_lost_arb(tmp, !(ctl & TWSI_CTL_AAK));
+ if (result)
+ return result;
+
+ switch (tmp) {
+ case STAT_RXDATA_ACK:
+ case STAT_RXDATA_NAK:
+ data[i++] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
+ }
+
+
+ /* NAK last recv'd byte, as a no-more-please */
+ if (last && i == length - 1)
+ ctl &= ~TWSI_CTL_AAK;
+
+ /* clr iflg to allow next event */
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, ctl);
+ result = octeon_i2c_wait(i2c);
+ if (result)
+ return result;
+ if (recv_len && i == 0) {
+ if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) {
+ dev_err(i2c->dev,
+ "%s: read len > I2C_SMBUS_BLOCK_MAX %d\n",
+ __func__, data[i]);
+ return -EPROTO;
+ }
+ length += data[i];
+ }
+ }
+ *rlength = length;
+ return 0;
+}
+
+/**
+ * octeon_i2c_write - send data to the bus via low-level controller
+ * @i2c: The struct octeon_i2c
+ * @target: Target address
+ * @data: Pointer to the data to be sent
+ * @length: Length of the data
+ * @last: is last msg in combined operation?
+ *
+ * The address is sent over the bus, then the data.
+ *
+ * Returns 0 on success, otherwise a negative errno.
+ */
+static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
+ const u8 *data, int length, int first, int last)
+{
+ int i, result;
+
+ result = octeon_i2c_start(i2c, first);
+ if (result)
+ return result;
+
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
+
+ result = octeon_i2c_wait(i2c);
+ if (result)
+ return result;
+
+ for (i = 0; i < length; i++) {
+ result = check_arb(i2c, false);
+ if (result)
+ return result;
+
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
+
+ result = octeon_i2c_wait(i2c);
+ if (result)
+ return result;
+ result = check_arb(i2c, false);
+ if (result)
+ return result;
+ }
+
+ return 0;
+}
+
+/* high-level-controller pure read of up to 8 bytes */
+static int octeon_i2c_simple_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
+{
+ int i, j, ret = 0;
+ u64 cmd;
+
+ octeon_i2c_enable_hlc(i2c);
+ cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
+ /* SIZE */
+ cmd |= (u64) (msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
+ /* A */
+ cmd |= (u64) (msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
+
+ if (msgs[0].flags & I2C_M_TEN)
+ cmd |= SW_TWSI_OP_10;
+ else
+ cmd |= SW_TWSI_OP_7;
+
+ octeon_i2c_hlc_int_clear(i2c);
+ __raw_writeq(cmd, i2c->twsi_base + SW_TWSI);
+
+ ret = octeon_i2c_hlc_wait(i2c);
+ if (ret)
+ goto err;
+
+ cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
+ if ((cmd & SW_TWSI_R) == 0)
+ return -EAGAIN;
+
+ for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
+ msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
+
+ if (msgs[0].len > 4) {
+ cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT);
+ for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
+ msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
+ }
+
+err:
+ return ret;
+}
+
+/* high-level-controller pure write of up to 8 bytes */
+static int octeon_i2c_simple_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
+{
+ int i, j, ret = 0;
+ u64 cmd;
+
+ octeon_i2c_enable_hlc(i2c);
+ octeon_i2c_hlc_int_clear(i2c);
+
+ ret = check_arb(i2c, false);
+ if (ret)
+ goto err;
+
+ cmd = SW_TWSI_V | SW_TWSI_SOVR;
+ /* SIZE */
+ cmd |= (u64) (msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
+ /* A */
+ cmd |= (u64) (msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
+
+ if (msgs[0].flags & I2C_M_TEN)
+ cmd |= SW_TWSI_OP_10;
+ else
+ cmd |= SW_TWSI_OP_7;
+
+ for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
+ cmd |= (u64)msgs[0].buf[j] << (8 * i);
+
+ if (msgs[0].len > 4) {
+ u64 ext = 0;
+
+ for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
+ ext |= (u64) msgs[0].buf[j] << (8 * i);
+ writeqflush(ext, i2c->twsi_base + SW_TWSI_EXT);
+ }
+
+ writeqflush(cmd, i2c->twsi_base + SW_TWSI);
+
+ ret = octeon_i2c_hlc_wait(i2c);
+ if (ret)
+ goto err;
+
+ cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
+ if ((cmd & SW_TWSI_R) == 0)
+ return -EAGAIN;
+
+ ret = check_arb(i2c, false);
+
+err:
+ return ret;
+}
+
+/* high-level-controller composite write+read, msg0=addr, msg1=data */
+static int octeon_i2c_ia_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
+{
+ int i, j, ret = 0;
+ u64 cmd;
+
+ octeon_i2c_enable_hlc(i2c);
+
+ cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
+ /* SIZE */
+ cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
+ /* A */
+ cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
+
+ if (msgs[0].flags & I2C_M_TEN)
+ cmd |= SW_TWSI_OP_10_IA;
+ else
+ cmd |= SW_TWSI_OP_7_IA;
+
+ if (msgs[0].len == 2) {
+ u64 ext = 0;
+
+ cmd |= SW_TWSI_EIA;
+ ext = (u64) msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
+ cmd |= (u64) msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
+ __raw_writeq(ext, i2c->twsi_base + SW_TWSI_EXT);
+ } else
+ cmd |= (u64) msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
+
+ octeon_i2c_hlc_int_clear(i2c);
+ writeqflush(cmd, i2c->twsi_base + SW_TWSI);
+
+ ret = octeon_i2c_hlc_wait(i2c);
+ if (ret)
+ goto err;
+
+ cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
+ if ((cmd & SW_TWSI_R) == 0)
+ return -EAGAIN;
+
+ for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
+ msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
+
+ if (msgs[1].len > 4) {
+ cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT);
+ for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
+ msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
+ }
+
+err:
+ return ret;
+}
+
+/* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
+static int octeon_i2c_ia_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
+{
+ bool set_ext = false;
+ int i, j, ret = 0;
+ u64 cmd, ext = 0;
+
+ octeon_i2c_enable_hlc(i2c);
+
+ cmd = SW_TWSI_V | SW_TWSI_SOVR;
+ /* SIZE */
+ cmd |= (u64) (msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
+ /* A */
+ cmd |= (u64) (msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
+
+ if (msgs[0].flags & I2C_M_TEN)
+ cmd |= SW_TWSI_OP_10_IA;
+ else
+ cmd |= SW_TWSI_OP_7_IA;
+
+ if (msgs[0].len == 2) {
+ cmd |= SW_TWSI_EIA;
+ ext |= (u64) msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
+ set_ext = true;
+ cmd |= (u64) msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
+ } else
+ cmd |= (u64) msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
+
+ for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
+ cmd |= (u64) msgs[1].buf[j] << (8 * i);
+
+ if (msgs[1].len > 4) {
+ for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
+ ext |= (u64)msgs[1].buf[j] << (8 * i);
+ set_ext = true;
+ }
+ if (set_ext)
+ writeqflush(ext, i2c->twsi_base + SW_TWSI_EXT);
+
+ octeon_i2c_hlc_int_clear(i2c);
+ writeqflush(cmd, i2c->twsi_base + SW_TWSI);
+
+ ret = octeon_i2c_hlc_wait(i2c);
+ if (ret)
+ goto err;
+
+ cmd = octeon_i2c_read_sw64(i2c, SW_TWSI_EOP_TWSI_STAT);
+ if ((cmd & SW_TWSI_R) == 0)
+ return -EAGAIN;
+ ret = octeon_i2c_lost_arb(cmd, false);
+
+err:
+ return ret;
+}
+
+/**
+ * octeon_i2c_xfer - The driver's master_xfer function
+ * @adap: Pointer to the i2c_adapter structure
+ * @msgs: Pointer to the messages to be processed
+ * @num: Length of the MSGS array
+ *
+ * Returns the number of messages processed, or a negative errno on failure.
+ */
+int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
+ int num)
+{
+ struct octeon_i2c *i2c = i2c_get_adapdata(adap);
+ int i, ret = 0;
+
+ if (num == 1) {
+ if (msgs[0].len > 0 && msgs[0].len <= 8) {
+ if (msgs[0].flags & I2C_M_RD)
+ ret = octeon_i2c_simple_read(i2c, msgs);
+ else
+ ret = octeon_i2c_simple_write(i2c, msgs);
+ goto out;
+ }
+ } else if (num == 2) {
+ if ((msgs[0].flags & I2C_M_RD) == 0 &&
+ (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
+ msgs[0].len > 0 && msgs[0].len <= 2 &&
+ msgs[1].len > 0 && msgs[1].len <= 8 &&
+ msgs[0].addr == msgs[1].addr) {
+ if (msgs[1].flags & I2C_M_RD)
+ ret = octeon_i2c_ia_read(i2c, msgs);
+ else
+ ret = octeon_i2c_ia_write(i2c, msgs);
+ goto out;
+ }
+ }
+
+ for (i = 0; ret == 0 && i < num; i++) {
+ struct i2c_msg *pmsg = &msgs[i];
+ bool last = (i == (num - 1));
+
+ dev_dbg(i2c->dev,
+ "Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
+ pmsg->flags & I2C_M_RD ? "read" : "write",
+ pmsg->len, pmsg->addr, i + 1, num);
+ if (pmsg->flags & I2C_M_RD)
+ ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
+ &pmsg->len, !i, last,
+ pmsg->flags & I2C_M_RECV_LEN);
+ else
+ ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
+ pmsg->len, !i, last);
+ }
+ octeon_i2c_stop(i2c);
+out:
+ return (ret != 0) ? ret : num;
+}
+
+/* calculate and set clock divisors */
+void octeon_i2c_set_clock(struct octeon_i2c *i2c)
+{
+ int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
+ int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
+
+ for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
+ /*
+ * An mdiv value of less than 2 seems to not work well
+ * with ds1337 RTCs, so we constrain it to larger values.
+ */
+ for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
+ /*
+ * For given ndiv and mdiv values check the
+ * two closest thp values.
+ */
+ tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
+ tclk *= (1 << ndiv_idx);
+ thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
+
+ for (inc = 0; inc <= 1; inc++) {
+ thp_idx = thp_base + inc;
+ if (thp_idx < 5 || thp_idx > 0xff)
+ continue;
+
+ foscl = i2c->sys_freq / (2 * (thp_idx + 1));
+ foscl = foscl / (1 << ndiv_idx);
+ foscl = foscl / (mdiv_idx + 1) / 10;
+ diff = abs(foscl - i2c->twsi_freq);
+ if (diff < delta_hz) {
+ delta_hz = diff;
+ thp = thp_idx;
+ mdiv = mdiv_idx;
+ ndiv = ndiv_idx;
+ }
+ }
+ }
+ }
+ octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
+}
+
+int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
+{
+ u8 status = 0;
+ int tries;
+
+ /* reset controller */
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);
+
+ for (tries = 10; tries && status != STAT_IDLE; tries--) {
+ udelay(1);
+ status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
+ }
+
+ if (status != STAT_IDLE) {
+ dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",
+ __func__, status);
+ return -EIO;
+ }
+
+ /* toggle twice to force both teardowns */
+ octeon_i2c_enable_hlc(i2c);
+ octeon_i2c_disable_hlc(i2c);
+ return 0;
+}
diff --git a/drivers/i2c/busses/i2c-cavium.h b/drivers/i2c/busses/i2c-cavium.h
new file mode 100644
index 0000000..7f78bf0
--- /dev/null
+++ b/drivers/i2c/busses/i2c-cavium.h
@@ -0,0 +1,195 @@
+#include <linux/atomic.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+
+/* Register offsets */
+#define SW_TWSI 0x00
+#define TWSI_INT 0x10
+#define SW_TWSI_EXT 0x18
+
+/* Controller command patterns */
+#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
+#define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */
+#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
+#define SW_TWSI_SOVR BIT_ULL(55) /* Size override */
+#define SW_TWSI_SIZE_SHIFT 52
+#define SW_TWSI_ADDR_SHIFT 40
+#define SW_TWSI_IA_SHIFT 32 /* Internal address */
+
+/* Controller opcode word (bits 60:57) */
+#define SW_TWSI_OP_SHIFT 57
+#define SW_TWSI_OP_7 (0ULL << SW_TWSI_OP_SHIFT)
+#define SW_TWSI_OP_7_IA (1ULL << SW_TWSI_OP_SHIFT)
+#define SW_TWSI_OP_10 (2ULL << SW_TWSI_OP_SHIFT)
+#define SW_TWSI_OP_10_IA (3ULL << SW_TWSI_OP_SHIFT)
+#define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
+#define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
+
+/* Controller extended opcode word (bits 34:32) */
+#define SW_TWSI_EOP_SHIFT 32
+#define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
+#define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
+#define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
+#define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
+#define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
+
+/* Controller command and status bits */
+#define TWSI_CTL_CE 0x80 /* High level controller enable */
+#define TWSI_CTL_ENAB 0x40 /* Bus enable */
+#define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
+#define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
+#define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
+#define TWSI_CTL_AAK 0x04 /* Assert ACK */
+
+/* Some status values */
+#define STAT_ERROR 0x00
+#define STAT_START 0x08
+#define STAT_RSTART 0x10
+#define STAT_TXADDR_ACK 0x18
+#define STAT_TXADDR_NAK 0x20
+#define STAT_TXDATA_ACK 0x28
+#define STAT_TXDATA_NAK 0x30
+#define STAT_LOST_ARB_38 0x38
+#define STAT_RXADDR_ACK 0x40
+#define STAT_RXADDR_NAK 0x48
+#define STAT_RXDATA_ACK 0x50
+#define STAT_RXDATA_NAK 0x58
+#define STAT_SLAVE_60 0x60
+#define STAT_LOST_ARB_68 0x68
+#define STAT_SLAVE_70 0x70
+#define STAT_LOST_ARB_78 0x78
+#define STAT_SLAVE_80 0x80
+#define STAT_SLAVE_88 0x88
+#define STAT_GENDATA_ACK 0x90
+#define STAT_GENDATA_NAK 0x98
+#define STAT_SLAVE_A0 0xA0
+#define STAT_SLAVE_A8 0xA8
+#define STAT_LOST_ARB_B0 0xB0
+#define STAT_SLAVE_LOST 0xB8
+#define STAT_SLAVE_NAK 0xC0
+#define STAT_SLAVE_ACK 0xC8
+#define STAT_AD2W_ACK 0xD0
+#define STAT_AD2W_NAK 0xD8
+#define STAT_IDLE 0xF8
+
+/* TWSI_INT values */
+#define TWSI_INT_ST_INT BIT_ULL(0)
+#define TWSI_INT_TS_INT BIT_ULL(1)
+#define TWSI_INT_CORE_INT BIT_ULL(2)
+#define TWSI_INT_ST_EN BIT_ULL(4)
+#define TWSI_INT_TS_EN BIT_ULL(5)
+#define TWSI_INT_CORE_EN BIT_ULL(6)
+#define TWSI_INT_SDA_OVR BIT_ULL(8)
+#define TWSI_INT_SCL_OVR BIT_ULL(9)
+#define TWSI_INT_SDA BIT_ULL(10)
+#define TWSI_INT_SCL BIT_ULL(11)
+
+struct octeon_i2c {
+ wait_queue_head_t queue;
+ struct i2c_adapter adap;
+ int irq;
+ int hlc_irq; /* For cn7890 only */
+ u32 twsi_freq;
+ int sys_freq;
+ void __iomem *twsi_base;
+ struct device *dev;
+ bool hlc_enabled;
+ bool broken_irq_mode;
+ bool broken_irq_check;
+ void (*int_en)(struct octeon_i2c *);
+ void (*int_dis)(struct octeon_i2c *);
+ void (*hlc_int_en)(struct octeon_i2c *);
+ void (*hlc_int_dis)(struct octeon_i2c *);
+ atomic_t int_en_cnt;
+ atomic_t hlc_int_en_cnt;
+};
+
+static inline void writeqflush(u64 val, void __iomem *addr)
+{
+ __raw_writeq(val, addr);
+ __raw_readq(addr); /* wait for write to land */
+}
+
+/**
+ * octeon_i2c_write_sw - write an I2C core register
+ * @i2c: The struct octeon_i2c
+ * @eop_reg: Register selector
+ * @data: Value to be written
+ *
+ * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
+ */
+static inline void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u32 data)
+{
+ u64 tmp;
+
+ __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
+ do {
+ tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
+ } while ((tmp & SW_TWSI_V) != 0);
+}
+
+/**
+ * octeon_i2c_read_sw64 - read an I2C core register
+ * @i2c: The struct octeon_i2c
+ * @eop_reg: Register selector
+ *
+ * Returns the data.
+ *
+ * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
+ */
+static inline u64 octeon_i2c_read_sw64(struct octeon_i2c *i2c, u64 eop_reg)
+{
+ u64 tmp;
+
+ __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
+ do {
+ tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
+ } while ((tmp & SW_TWSI_V) != 0);
+
+ return tmp;
+}
+
+/**
+ * octeon_i2c_read_sw - read lower bits of an I2C core register
+ * @i2c: The struct octeon_i2c
+ * @eop_reg: Register selector
+ *
+ * Returns the data.
+ *
+ * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
+ */
+static inline u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
+{
+ return octeon_i2c_read_sw64(i2c, eop_reg) & 0xFF;
+}
+
+/**
+ * octeon_i2c_write_int - write the TWSI_INT register
+ * @i2c: The struct octeon_i2c
+ * @data: Value to be written
+ */
+static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
+{
+ writeqflush(data, i2c->twsi_base + TWSI_INT);
+}
+
+static inline u64 octeon_i2c_read_ctl(struct octeon_i2c *i2c)
+{
+ return octeon_i2c_read_sw64(i2c, SW_TWSI_EOP_TWSI_CTL);
+}
+
+static inline int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
+{
+ return (octeon_i2c_read_ctl(i2c) & TWSI_CTL_IFLG) != 0;
+}
+
+/* Prototypes */
+irqreturn_t octeon_i2c_isr(int irq, void *dev_id);
+int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
+int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c);
+void octeon_i2c_set_clock(struct octeon_i2c *i2c);
diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c
index 95cd301..87e7649 100644
--- a/drivers/i2c/busses/i2c-octeon-core.c
+++ b/drivers/i2c/busses/i2c-octeon-core.c
@@ -24,182 +24,10 @@
#include <linux/of.h>

#include <asm/octeon/octeon.h>
+#include "i2c-cavium.h"

#define DRV_NAME "i2c-octeon"

-/* Register offsets */
-#define SW_TWSI 0x00
-#define TWSI_INT 0x10
-#define SW_TWSI_EXT 0x18
-
-/* Controller command patterns */
-#define SW_TWSI_V BIT_ULL(63) /* Valid bit */
-#define SW_TWSI_EIA BIT_ULL(61) /* Extended internal address */
-#define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
-#define SW_TWSI_SOVR BIT_ULL(55) /* Size override */
-#define SW_TWSI_SIZE_SHIFT 52
-#define SW_TWSI_ADDR_SHIFT 40
-#define SW_TWSI_IA_SHIFT 32 /* Internal address */
-
-/* Controller opcode word (bits 60:57) */
-#define SW_TWSI_OP_SHIFT 57
-#define SW_TWSI_OP_7 (0ULL << SW_TWSI_OP_SHIFT)
-#define SW_TWSI_OP_7_IA (1ULL << SW_TWSI_OP_SHIFT)
-#define SW_TWSI_OP_10 (2ULL << SW_TWSI_OP_SHIFT)
-#define SW_TWSI_OP_10_IA (3ULL << SW_TWSI_OP_SHIFT)
-#define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
-#define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
-
-/* Controller extended opcode word (bits 34:32) */
-#define SW_TWSI_EOP_SHIFT 32
-#define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
-#define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
-#define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
-#define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
-#define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
-
-/* Controller command and status bits */
-#define TWSI_CTL_CE 0x80 /* High level controller enable */
-#define TWSI_CTL_ENAB 0x40 /* Bus enable */
-#define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
-#define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
-#define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
-#define TWSI_CTL_AAK 0x04 /* Assert ACK */
-
-/* Some status values */
-#define STAT_ERROR 0x00
-#define STAT_START 0x08
-#define STAT_RSTART 0x10
-#define STAT_TXADDR_ACK 0x18
-#define STAT_TXADDR_NAK 0x20
-#define STAT_TXDATA_ACK 0x28
-#define STAT_TXDATA_NAK 0x30
-#define STAT_LOST_ARB_38 0x38
-#define STAT_RXADDR_ACK 0x40
-#define STAT_RXADDR_NAK 0x48
-#define STAT_RXDATA_ACK 0x50
-#define STAT_RXDATA_NAK 0x58
-#define STAT_SLAVE_60 0x60
-#define STAT_LOST_ARB_68 0x68
-#define STAT_SLAVE_70 0x70
-#define STAT_LOST_ARB_78 0x78
-#define STAT_SLAVE_80 0x80
-#define STAT_SLAVE_88 0x88
-#define STAT_GENDATA_ACK 0x90
-#define STAT_GENDATA_NAK 0x98
-#define STAT_SLAVE_A0 0xA0
-#define STAT_SLAVE_A8 0xA8
-#define STAT_LOST_ARB_B0 0xB0
-#define STAT_SLAVE_LOST 0xB8
-#define STAT_SLAVE_NAK 0xC0
-#define STAT_SLAVE_ACK 0xC8
-#define STAT_AD2W_ACK 0xD0
-#define STAT_AD2W_NAK 0xD8
-#define STAT_IDLE 0xF8
-
-/* TWSI_INT values */
-#define TWSI_INT_ST_INT BIT_ULL(0)
-#define TWSI_INT_TS_INT BIT_ULL(1)
-#define TWSI_INT_CORE_INT BIT_ULL(2)
-#define TWSI_INT_ST_EN BIT_ULL(4)
-#define TWSI_INT_TS_EN BIT_ULL(5)
-#define TWSI_INT_CORE_EN BIT_ULL(6)
-#define TWSI_INT_SDA_OVR BIT_ULL(8)
-#define TWSI_INT_SCL_OVR BIT_ULL(9)
-#define TWSI_INT_SDA BIT_ULL(10)
-#define TWSI_INT_SCL BIT_ULL(11)
-
-struct octeon_i2c {
- wait_queue_head_t queue;
- struct i2c_adapter adap;
- int irq;
- int hlc_irq; /* For cn7890 only */
- u32 twsi_freq;
- int sys_freq;
- void __iomem *twsi_base;
- struct device *dev;
- bool hlc_enabled;
- bool broken_irq_mode;
- bool broken_irq_check;
- void (*int_en)(struct octeon_i2c *);
- void (*int_dis)(struct octeon_i2c *);
- void (*hlc_int_en)(struct octeon_i2c *);
- void (*hlc_int_dis)(struct octeon_i2c *);
- atomic_t int_en_cnt;
- atomic_t hlc_int_en_cnt;
-};
-
-static int reset_how;
-
-static void writeqflush(u64 val, void __iomem *addr)
-{
- __raw_writeq(val, addr);
- __raw_readq(addr); /* wait for write to land */
-}
-
-/**
- * octeon_i2c_write_sw - write an I2C core register
- * @i2c: The struct octeon_i2c
- * @eop_reg: Register selector
- * @data: Value to be written
- *
- * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
- */
-static void octeon_i2c_write_sw(struct octeon_i2c *i2c, u64 eop_reg, u32 data)
-{
- u64 tmp;
-
- __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
- do {
- tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
- } while ((tmp & SW_TWSI_V) != 0);
-}
-
-/**
- * octeon_i2c_read_sw64 - read an I2C core register
- * @i2c: The struct octeon_i2c
- * @eop_reg: Register selector
- *
- * Returns the data.
- *
- * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
- */
-static u64 octeon_i2c_read_sw64(struct octeon_i2c *i2c, u64 eop_reg)
-{
- u64 tmp;
-
- __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
- do {
- tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
- } while ((tmp & SW_TWSI_V) != 0);
-
- return tmp;
-}
-
-/**
- * octeon_i2c_read_sw - read lower bits of an I2C core register
- * @i2c: The struct octeon_i2c
- * @eop_reg: Register selector
- *
- * Returns the data.
- *
- * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
- */
-static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
-{
- return octeon_i2c_read_sw64(i2c, eop_reg) & 0xFF;
-}
-
-/**
- * octeon_i2c_write_int - write the TWSI_INT register
- * @i2c: The struct octeon_i2c
- * @data: Value to be written
- */
-static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
-{
- writeqflush(data, i2c->twsi_base + TWSI_INT);
-}
-
/**
* octeon_i2c_int_enable - enable the CORE interrupt
* @i2c: The struct octeon_i2c
@@ -219,15 +47,6 @@ static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
octeon_i2c_write_int(i2c, 0);
}

-static void octeon_i2c_disable_hlc(struct octeon_i2c *i2c)
-{
- if (!i2c->hlc_enabled)
- return;
-
- i2c->hlc_enabled = false;
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
-}
-
/**
* octeon_i2c_int_enable78 - enable the CORE interrupt
* @i2c: The struct octeon_i2c
@@ -280,49 +99,6 @@ static void octeon_i2c_hlc_int_disable78(struct octeon_i2c *i2c)
__octeon_i2c_irq_disable(&i2c->hlc_int_en_cnt, i2c->hlc_irq);
}

-/**
- * octeon_i2c_unblock - unblock the bus
- * @i2c: The struct octeon_i2c
- *
- * If there was a reset while a device was driving 0 to bus, bus is blocked.
- * We toggle it free manually by some clock cycles and send a stop.
- */
-static void octeon_i2c_unblock(struct octeon_i2c *i2c)
-{
- int state, i;
-
- octeon_i2c_disable_hlc(i2c);
- dev_dbg(i2c->dev, "%s\n", __func__);
-
- /* cycle 8+1 clocks with SDA high */
- for (i = 0; i < 9; i++) {
- octeon_i2c_write_int(i2c, 0);
- udelay(5);
- state = __raw_readq(i2c->twsi_base + TWSI_INT);
- if (state & (TWSI_INT_SDA | TWSI_INT_SCL))
- break;
- octeon_i2c_write_int(i2c, TWSI_INT_SCL_OVR);
- udelay(5);
- }
- /* hand-crank a STOP */
- octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);
- udelay(5);
- octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);
- udelay(5);
- octeon_i2c_write_int(i2c, 0);
-}
-
-/* interrupt service routine */
-static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
-{
- struct octeon_i2c *i2c = dev_id;
-
- i2c->int_dis(i2c);
- wake_up(&i2c->queue);
-
- return IRQ_HANDLED;
-}
-
/* HLC interrupt service routine */
static irqreturn_t octeon_i2c_hlc_isr78(int irq, void *dev_id)
{
@@ -334,768 +110,11 @@ static irqreturn_t octeon_i2c_hlc_isr78(int irq, void *dev_id)
return IRQ_HANDLED;
}

-static u64 octeon_i2c_read_ctl(struct octeon_i2c *i2c)
-{
- return octeon_i2c_read_sw64(i2c, SW_TWSI_EOP_TWSI_CTL);
-}
-
-static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
-{
- return (octeon_i2c_read_ctl(i2c) & TWSI_CTL_IFLG) != 0;
-}
-
-#define I2C_OCTEON_IFLG_WAIT 80 /* microseconds */
-
-/*
- * Wait-helper which addresses the delayed-IFLAG problem by re-polling for
- * missing TWSI_CTL[IFLG] a few us later, when irq has signalled an event,
- * but none found. Skip this re-poll on the first (non-wakeup) call.
- */
-static int poll_iflg(struct octeon_i2c *i2c, int *first_p)
-{
- int iflg = octeon_i2c_test_iflg(i2c);
-
- if (iflg)
- return 1;
- if (*first_p)
- *first_p = 0;
- else {
- usleep_range(I2C_OCTEON_IFLG_WAIT, 2 * I2C_OCTEON_IFLG_WAIT);
- iflg = octeon_i2c_test_iflg(i2c);
- }
- return iflg;
-}
-
-/**
- * octeon_i2c_wait - wait for the IFLG to be set
- * @i2c: The struct octeon_i2c
- *
- * Returns 0 on success, otherwise a negative errno.
- */
-static int octeon_i2c_wait(struct octeon_i2c *i2c)
-{
- long time_left;
- int first = 1;
-
- if (i2c->broken_irq_mode) {
- /*
- * Some chip revisions seem to not assert the irq in
- * the interrupt controller. So we must poll for the
- * IFLG change.
- */
- u64 end = get_jiffies_64() + i2c->adap.timeout;
-
- while (!octeon_i2c_test_iflg(i2c) &&
- time_before64(get_jiffies_64(), end))
- udelay(50);
-
- return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT;
- }
-
- i2c->int_en(i2c);
- time_left = wait_event_timeout(i2c->queue, poll_iflg(i2c, &first),
- i2c->adap.timeout);
- i2c->int_dis(i2c);
-
- if (time_left <= 0 && i2c->broken_irq_check &&
- octeon_i2c_test_iflg(i2c)) {
- dev_err(i2c->dev,
- "broken irq connection detected, switching to polling mode.\n");
- i2c->broken_irq_mode = true;
- return 0;
- }
- if (!time_left) {
- dev_dbg(i2c->dev, "%s: timeout\n", __func__);
- return -ETIMEDOUT;
- }
-
- return 0;
-}
-
-/*
- * Cleanup low-level state & enable high-level.
- * Returns -EAGAIN if low-level state could not be cleaned.
- */
-static int octeon_i2c_enable_hlc(struct octeon_i2c *i2c)
-{
- int try = 0, ret = 0;
- u64 val;
-
- if (i2c->hlc_enabled)
- return 0;
- i2c->hlc_enabled = true;
-
- while (1) {
- val = octeon_i2c_read_ctl(i2c) & (TWSI_CTL_STA | TWSI_CTL_STP);
- if (!val)
- break;
-
- /* clear IFLG event */
- if (val & TWSI_CTL_IFLG)
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
-
- if (try++ > 100) {
- pr_err("%s: giving up\n", __func__);
- ret = -EAGAIN;
- break;
- }
-
- /* spin until any start/stop has finished */
- udelay(10);
- }
-
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
- TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);
- return ret;
-}
-
-static int octeon_i2c_lost_arb(u8 code, int final_read)
-{
- switch (code) {
- /* Arbitration lost */
- case STAT_LOST_ARB_38:
- case STAT_LOST_ARB_68:
- case STAT_LOST_ARB_78:
- case STAT_LOST_ARB_B0:
- return -EAGAIN;
-
- /* Being addressed as slave, should back off & listen */
- case STAT_SLAVE_60:
- case STAT_SLAVE_70:
- case STAT_GENDATA_ACK:
- case STAT_GENDATA_NAK:
- return -EIO;
-
- /* Core busy as slave */
- case STAT_SLAVE_80:
- case STAT_SLAVE_88:
- case STAT_SLAVE_A0:
- case STAT_SLAVE_A8:
- case STAT_SLAVE_LOST:
- case STAT_SLAVE_NAK:
- case STAT_SLAVE_ACK:
- return -EIO;
-
- /* ACK allowed on pre-terminal bytes only */
- case STAT_RXDATA_ACK:
- if (!final_read)
- return 0;
- return -EAGAIN;
-
- /* NAK allowed on terminal byte only */
- case STAT_RXDATA_NAK:
- if (final_read)
- return 0;
- return -EAGAIN;
- case STAT_TXDATA_NAK:
- case STAT_TXADDR_NAK:
- case STAT_RXADDR_NAK:
- case STAT_AD2W_NAK:
- return -EAGAIN;
- }
- return 0;
-}
-
-static int check_arb(struct octeon_i2c *i2c, int final_read)
-{
- return octeon_i2c_lost_arb(octeon_i2c_read_sw(i2c,
- SW_TWSI_EOP_TWSI_STAT), final_read);
-}
-
-/* send STOP to the bus */
-static void octeon_i2c_stop(struct octeon_i2c *i2c)
-{
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
- TWSI_CTL_ENAB | TWSI_CTL_STP);
-}
-
-static bool octeon_i2c_hlc_test_ready(struct octeon_i2c *i2c)
-{
- u64 val = __raw_readq(i2c->twsi_base + SW_TWSI);
-
- return (val & SW_TWSI_V) == 0;
-}
-
static void octeon_i2c_hlc_int_enable(struct octeon_i2c *i2c)
{
octeon_i2c_write_int(i2c, TWSI_INT_ST_EN);
}

-static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)
-{
- /* clear ST/TS events, listen for neither */
- octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);
-}
-
-/**
- * octeon_i2c_hlc_wait - wait for an HLC operation to complete
- * @i2c: The struct octeon_i2c
- *
- * Returns 0 on success, otherwise a negative errno.
- */
-static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
-{
- int time_left;
-
- if (i2c->broken_irq_mode) {
- /*
- * Some cn38xx boards did not assert the irq in
- * the interrupt controller. So we must poll for the
- * IFLG change.
- */
- u64 end = get_jiffies_64() + i2c->adap.timeout;
-
- while (!octeon_i2c_hlc_test_ready(i2c) &&
- time_before64(get_jiffies_64(), end))
- udelay(50);
-
- return octeon_i2c_hlc_test_ready(i2c) ? 0 : -ETIMEDOUT;
- }
-
- i2c->hlc_int_en(i2c);
- time_left = wait_event_interruptible_timeout(i2c->queue,
- octeon_i2c_hlc_test_ready(i2c),
- i2c->adap.timeout);
- i2c->hlc_int_dis(i2c);
- if (!time_left)
- octeon_i2c_hlc_int_clear(i2c);
-
- if (time_left <= 0 && i2c->broken_irq_check &&
- octeon_i2c_hlc_test_ready(i2c)) {
- dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
- i2c->broken_irq_mode = true;
- return 0;
- }
-
- if (!time_left) {
- dev_dbg(i2c->dev, "%s: timeout\n", __func__);
- return -ETIMEDOUT;
- }
- if (time_left < 0) {
- dev_dbg(i2c->dev, "%s: wait interrupted\n", __func__);
- return time_left;
- }
- return 0;
-}
-
-/* high-level-controller pure read of up to 8 bytes */
-static int octeon_i2c_simple_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
-{
- int i, j, ret = 0;
- u64 cmd;
-
- octeon_i2c_enable_hlc(i2c);
- cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
- /* SIZE */
- cmd |= (u64) (msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
- /* A */
- cmd |= (u64) (msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
-
- if (msgs[0].flags & I2C_M_TEN)
- cmd |= SW_TWSI_OP_10;
- else
- cmd |= SW_TWSI_OP_7;
-
- octeon_i2c_hlc_int_clear(i2c);
- __raw_writeq(cmd, i2c->twsi_base + SW_TWSI);
-
- ret = octeon_i2c_hlc_wait(i2c);
- if (ret)
- goto err;
-
- cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
- if ((cmd & SW_TWSI_R) == 0)
- return -EAGAIN;
-
- for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
- msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
-
- if (msgs[0].len > 4) {
- cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT);
- for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
- msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff;
- }
-
-err:
- return ret;
-}
-
-/* high-level-controller pure write of up to 8 bytes */
-static int octeon_i2c_simple_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
-{
- int i, j, ret = 0;
- u64 cmd;
-
- octeon_i2c_enable_hlc(i2c);
- octeon_i2c_hlc_int_clear(i2c);
-
- ret = check_arb(i2c, false);
- if (ret)
- goto err;
-
- cmd = SW_TWSI_V | SW_TWSI_SOVR;
- /* SIZE */
- cmd |= (u64) (msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;
- /* A */
- cmd |= (u64) (msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
-
- if (msgs[0].flags & I2C_M_TEN)
- cmd |= SW_TWSI_OP_10;
- else
- cmd |= SW_TWSI_OP_7;
-
- for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--)
- cmd |= (u64)msgs[0].buf[j] << (8 * i);
-
- if (msgs[0].len > 4) {
- u64 ext = 0;
-
- for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
- ext |= (u64) msgs[0].buf[j] << (8 * i);
- writeqflush(ext, i2c->twsi_base + SW_TWSI_EXT);
- }
-
- writeqflush(cmd, i2c->twsi_base + SW_TWSI);
-
- ret = octeon_i2c_hlc_wait(i2c);
- if (ret)
- goto err;
-
- cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
- if ((cmd & SW_TWSI_R) == 0)
- return -EAGAIN;
-
- ret = check_arb(i2c, false);
-
-err:
- return ret;
-}
-
-/* high-level-controller composite write+read, msg0=addr, msg1=data */
-static int octeon_i2c_ia_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
-{
- int i, j, ret = 0;
- u64 cmd;
-
- octeon_i2c_enable_hlc(i2c);
-
- cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR;
- /* SIZE */
- cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
- /* A */
- cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
-
- if (msgs[0].flags & I2C_M_TEN)
- cmd |= SW_TWSI_OP_10_IA;
- else
- cmd |= SW_TWSI_OP_7_IA;
-
- if (msgs[0].len == 2) {
- u64 ext = 0;
-
- cmd |= SW_TWSI_EIA;
- ext = (u64) msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
- cmd |= (u64) msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
- __raw_writeq(ext, i2c->twsi_base + SW_TWSI_EXT);
- } else
- cmd |= (u64) msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
-
- octeon_i2c_hlc_int_clear(i2c);
- writeqflush(cmd, i2c->twsi_base + SW_TWSI);
-
- ret = octeon_i2c_hlc_wait(i2c);
- if (ret)
- goto err;
-
- cmd = __raw_readq(i2c->twsi_base + SW_TWSI);
- if ((cmd & SW_TWSI_R) == 0)
- return -EAGAIN;
-
- for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
- msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
-
- if (msgs[1].len > 4) {
- cmd = __raw_readq(i2c->twsi_base + SW_TWSI_EXT);
- for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
- msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;
- }
-
-err:
- return ret;
-}
-
-/* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
-static int octeon_i2c_ia_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
-{
- bool set_ext = false;
- int i, j, ret = 0;
- u64 cmd, ext = 0;
-
- octeon_i2c_enable_hlc(i2c);
-
- cmd = SW_TWSI_V | SW_TWSI_SOVR;
- /* SIZE */
- cmd |= (u64) (msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;
- /* A */
- cmd |= (u64) (msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT;
-
- if (msgs[0].flags & I2C_M_TEN)
- cmd |= SW_TWSI_OP_10_IA;
- else
- cmd |= SW_TWSI_OP_7_IA;
-
- if (msgs[0].len == 2) {
- cmd |= SW_TWSI_EIA;
- ext |= (u64) msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
- set_ext = true;
- cmd |= (u64) msgs[0].buf[1] << SW_TWSI_IA_SHIFT;
- } else
- cmd |= (u64) msgs[0].buf[0] << SW_TWSI_IA_SHIFT;
-
- for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--)
- cmd |= (u64) msgs[1].buf[j] << (8 * i);
-
- if (msgs[1].len > 4) {
- for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)
- ext |= (u64)msgs[1].buf[j] << (8 * i);
- set_ext = true;
- }
- if (set_ext)
- writeqflush(ext, i2c->twsi_base + SW_TWSI_EXT);
-
- octeon_i2c_hlc_int_clear(i2c);
- writeqflush(cmd, i2c->twsi_base + SW_TWSI);
-
- ret = octeon_i2c_hlc_wait(i2c);
- if (ret)
- goto err;
-
- cmd = octeon_i2c_read_sw64(i2c, SW_TWSI_EOP_TWSI_STAT);
- if ((cmd & SW_TWSI_R) == 0)
- return -EAGAIN;
- ret = octeon_i2c_lost_arb(cmd, false);
-
-err:
- return ret;
-}
-
-/* calculate and set clock divisors */
-static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
-{
- int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
- int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
-
- for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
- /*
- * An mdiv value of less than 2 seems to not work well
- * with ds1337 RTCs, so we constrain it to larger values.
- */
- for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
- /*
- * For given ndiv and mdiv values check the
- * two closest thp values.
- */
- tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
- tclk *= (1 << ndiv_idx);
- thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
-
- for (inc = 0; inc <= 1; inc++) {
- thp_idx = thp_base + inc;
- if (thp_idx < 5 || thp_idx > 0xff)
- continue;
-
- foscl = i2c->sys_freq / (2 * (thp_idx + 1));
- foscl = foscl / (1 << ndiv_idx);
- foscl = foscl / (mdiv_idx + 1) / 10;
- diff = abs(foscl - i2c->twsi_freq);
- if (diff < delta_hz) {
- delta_hz = diff;
- thp = thp_idx;
- mdiv = mdiv_idx;
- ndiv = ndiv_idx;
- }
- }
- }
- }
- octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
-}
-
-static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
-{
- u8 status = 0;
- int tries;
-
- /* reset controller */
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);
-
- for (tries = 10; tries && status != STAT_IDLE; tries--) {
- udelay(1);
- status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
- }
-
- if (status != STAT_IDLE) {
- dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",
- __func__, status);
- return -EIO;
- }
-
- /* toggle twice to force both teardowns */
- octeon_i2c_enable_hlc(i2c);
- octeon_i2c_disable_hlc(i2c);
- return 0;
-}
-
-/*
- * TWSI state seems stuck. Not sure if it's TWSI-engine state or something
- * else on bus. The initial _stop() is always harmless, it just resets state
- * machine, does not _transmit_ STOP unless engine was active.
- */
-static int start_unstick(struct octeon_i2c *i2c)
-{
- octeon_i2c_stop(i2c);
-
- /*
- * Response is escalated over successive calls,
- * as EAGAIN provokes retries from i2c/core.
- */
- switch (reset_how++ % 4) {
- case 0:
- /* just the stop above */
- break;
- case 1:
- /*
- * Controller refused to send start flag. May be a
- * client is holding SDA low? Let's try to free it.
- */
- octeon_i2c_unblock(i2c);
- break;
- case 2:
- /* re-init our TWSI hardware */
- octeon_i2c_init_lowlevel(i2c);
- break;
- default:
- /* retry in caller */
- reset_how = 0;
- return -EAGAIN;
- }
- return 0;
-}
-
-/**
- * octeon_i2c_start - send START to the bus
- * @i2c: The struct octeon_i2c
- * @first: first msg in combined operation?
- *
- * Returns 0 on success, otherwise a negative errno.
- */
-static int octeon_i2c_start(struct octeon_i2c *i2c, int first)
-{
- int result;
- u8 data;
-
- octeon_i2c_disable_hlc(i2c);
-
- while (1) {
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
- TWSI_CTL_ENAB | TWSI_CTL_STA);
-
- result = octeon_i2c_wait(i2c);
- data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
-
- switch (data) {
- case STAT_START:
- case STAT_RSTART:
- if (!first)
- return -EAGAIN;
- reset_how = 0;
- return 0;
- case STAT_RXADDR_ACK:
- if (first)
- return -EAGAIN;
- return start_unstick(i2c);
- /*
- * case STAT_IDLE:
- * case STAT_ERROR:
- */
- default:
- if (!first)
- return -EAGAIN;
- start_unstick(i2c);
- }
- }
- return 0;
-}
-
-/**
- * octeon_i2c_read - receive data from the bus via low-level controller
- * @i2c: The struct octeon_i2c
- * @target: Target address
- * @data: Pointer to the location to store the data
- * @rlength: Length of the data
- * @phase: which phase of a combined operation.
- * @recv_len: flag for length byte
- *
- * The address is sent over the bus, then the data is read.
- *
- * Returns 0 on success, otherwise a negative errno.
- */
-static int octeon_i2c_read(struct octeon_i2c *i2c, int target, u8 *data,
- u16 *rlength, bool first, bool last, bool recv_len)
-{
- u8 ctl = TWSI_CTL_ENAB | TWSI_CTL_AAK;
- int i, result, length = *rlength;
- u8 tmp;
-
- if (length < 1)
- return -EINVAL;
-
- result = octeon_i2c_start(i2c, first);
- if (result)
- return result;
-
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) | 1);
-
- for (i = 0; i < length; ) {
- tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
- result = octeon_i2c_lost_arb(tmp, !(ctl & TWSI_CTL_AAK));
- if (result)
- return result;
-
- switch (tmp) {
- case STAT_RXDATA_ACK:
- case STAT_RXDATA_NAK:
- data[i++] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
- }
-
- /* NAK last recv'd byte, as a no-more-please */
- if (last && i == length - 1)
- ctl &= ~TWSI_CTL_AAK;
-
- /* clr iflg to allow next event */
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, ctl);
- result = octeon_i2c_wait(i2c);
- if (result)
- return result;
-
- if (recv_len && i == 0) {
- if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) {
- dev_err(i2c->dev,
- "%s: read len > I2C_SMBUS_BLOCK_MAX %d\n",
- __func__, data[i]);
- return -EPROTO;
- }
- length += data[i];
- }
- }
- *rlength = length;
- return 0;
-}
-
-/**
- * octeon_i2c_write - send data to the bus via low-level controller
- * @i2c: The struct octeon_i2c
- * @target: Target address
- * @data: Pointer to the data to be sent
- * @length: Length of the data
- * @last: is last msg in combined operation?
- *
- * The address is sent over the bus, then the data.
- *
- * Returns 0 on success, otherwise a negative errno.
- */
-static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
- const u8 *data, int length, int first, int last)
-{
- int i, result;
-
- result = octeon_i2c_start(i2c, first);
- if (result)
- return result;
-
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
-
- result = octeon_i2c_wait(i2c);
- if (result)
- return result;
-
- for (i = 0; i < length; i++) {
- result = check_arb(i2c, false);
- if (result)
- return result;
-
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
-
- result = octeon_i2c_wait(i2c);
- if (result)
- return result;
- result = check_arb(i2c, false);
- if (result)
- return result;
- }
-
- return 0;
-}
-
-/**
- * octeon_i2c_xfer - The driver's master_xfer function
- * @adap: Pointer to the i2c_adapter structure
- * @msgs: Pointer to the messages to be processed
- * @num: Length of the MSGS array
- *
- * Returns the number of messages processed, or a negative errno on failure.
- */
-static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
- int num)
-{
- struct octeon_i2c *i2c = i2c_get_adapdata(adap);
- int i, ret = 0;
-
- if (num == 1) {
- if (msgs[0].len > 0 && msgs[0].len <= 8) {
- if (msgs[0].flags & I2C_M_RD)
- ret = octeon_i2c_simple_read(i2c, msgs);
- else
- ret = octeon_i2c_simple_write(i2c, msgs);
- goto out;
- }
- } else if (num == 2) {
- if ((msgs[0].flags & I2C_M_RD) == 0 &&
- (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
- msgs[0].len > 0 && msgs[0].len <= 2 &&
- msgs[1].len > 0 && msgs[1].len <= 8 &&
- msgs[0].addr == msgs[1].addr) {
- if (msgs[1].flags & I2C_M_RD)
- ret = octeon_i2c_ia_read(i2c, msgs);
- else
- ret = octeon_i2c_ia_write(i2c, msgs);
- goto out;
- }
- }
-
- for (i = 0; ret == 0 && i < num; i++) {
- struct i2c_msg *pmsg = &msgs[i];
- bool last = (i == (num - 1));
-
- dev_dbg(i2c->dev,
- "Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
- pmsg->flags & I2C_M_RD ? "read" : "write",
- pmsg->len, pmsg->addr, i + 1, num);
- if (pmsg->flags & I2C_M_RD)
- ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
- &pmsg->len, !i, last,
- pmsg->flags & I2C_M_RECV_LEN);
- else
- ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
- pmsg->len, !i, last);
- }
- octeon_i2c_stop(i2c);
-out:
- return (ret != 0) ? ret : num;
-}
-
static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
--
1.9.1

2016-03-31 10:28:56

by Jan Glauber

Subject: [PATCH v5 11/14] i2c: octeon: Rename driver to prepare for split

This is just an intermediate commit in preparation of
the driver split. The module rename in this commit
will be reverted in the next patch, this is just done
to make the series bisectible.

Signed-off-by: Jan Glauber <[email protected]>
---
drivers/i2c/busses/Makefile | 2 +-
drivers/i2c/busses/{i2c-octeon.c => i2c-octeon-core.c} | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename drivers/i2c/busses/{i2c-octeon.c => i2c-octeon-core.c} (100%)

diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 37f2819..3405286 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -91,7 +91,7 @@ obj-$(CONFIG_I2C_UNIPHIER) += i2c-uniphier.o
obj-$(CONFIG_I2C_UNIPHIER_F) += i2c-uniphier-f.o
obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
obj-$(CONFIG_I2C_WMT) += i2c-wmt.o
-obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
+obj-$(CONFIG_I2C_OCTEON) += i2c-octeon-core.o
obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o
diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon-core.c
similarity index 100%
rename from drivers/i2c/busses/i2c-octeon.c
rename to drivers/i2c/busses/i2c-octeon-core.c
--
1.9.1

2016-03-31 10:29:35

by Jan Glauber

Subject: [PATCH v5 14/14] i2c: thunderx: Add smbus alert support

Add smbus alert interrupt support.

Signed-off-by: Jan Glauber <[email protected]>
---
drivers/i2c/busses/i2c-cavium.h | 6 ++++++
drivers/i2c/busses/i2c-thunderx-core.c | 35 ++++++++++++++++++++++++++++++++++
2 files changed, 41 insertions(+)

diff --git a/drivers/i2c/busses/i2c-cavium.h b/drivers/i2c/busses/i2c-cavium.h
index 31608c4..f934624 100644
--- a/drivers/i2c/busses/i2c-cavium.h
+++ b/drivers/i2c/busses/i2c-cavium.h
@@ -3,6 +3,7 @@
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/i2c.h>
+#include <linux/i2c-smbus.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/pci.h>
@@ -118,6 +119,11 @@ struct octeon_i2c {
#if IS_ENABLED(CONFIG_I2C_THUNDERX)
struct msix_entry i2c_msix;
#endif
+
+#if IS_ENABLED(CONFIG_I2C_SMBUS)
+ struct i2c_smbus_alert_setup alert_data;
+ struct i2c_client *ara;
+#endif
};

static inline void writeqflush(u64 val, void __iomem *addr)
diff --git a/drivers/i2c/busses/i2c-thunderx-core.c b/drivers/i2c/busses/i2c-thunderx-core.c
index 2ce985b..339378a 100644
--- a/drivers/i2c/busses/i2c-thunderx-core.c
+++ b/drivers/i2c/busses/i2c-thunderx-core.c
@@ -9,9 +9,11 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/i2c.h>
+#include <linux/i2c-smbus.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/of_irq.h>
#include <linux/pci.h>

#include "i2c-cavium.h"
@@ -108,6 +110,35 @@ static void thunder_i2c_clock_disable(struct device *dev, struct clk *clk)
devm_clk_put(dev, clk);
}

+static int thunder_i2c_smbus_setup(struct octeon_i2c *i2c,
+ struct device_node *node)
+{
+#if IS_ENABLED(CONFIG_I2C_SMBUS)
+ u32 type;
+
+ i2c->alert_data.irq = irq_of_parse_and_map(node, 0);
+ if (!i2c->alert_data.irq)
+ return -EINVAL;
+
+ type = irqd_get_trigger_type(irq_get_irq_data(i2c->alert_data.irq));
+ i2c->alert_data.alert_edge_triggered =
+ (type & IRQ_TYPE_LEVEL_MASK) ? 1 : 0;
+
+ i2c->ara = i2c_setup_smbus_alert(&i2c->adap, &i2c->alert_data);
+ if (!i2c->ara)
+ return -ENODEV;
+#endif
+ return 0;
+}
+
+static void thunder_i2c_smbus_remove(struct octeon_i2c *i2c)
+{
+#if IS_ENABLED(CONFIG_I2C_SMBUS)
+ if (i2c->ara)
+ i2c_unregister_device(i2c->ara);
+#endif
+}
+
static void thunder_i2c_set_name(struct pci_dev *pdev, struct octeon_i2c *i2c,
char *name)
{
@@ -207,6 +238,9 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev,
goto out_irq;
}

+ ret = thunder_i2c_smbus_setup(i2c, node);
+ if (ret < 0)
+ dev_err(dev, "Failed to setup smbus alert\n");
dev_info(i2c->dev, "probed\n");
return 0;

@@ -237,6 +271,7 @@ static void thunder_i2c_remove_pci(struct pci_dev *pdev)

dev = i2c->dev;
thunder_i2c_clock_disable(dev, i2c->clk);
+ thunder_i2c_smbus_remove(i2c);
i2c_del_adapter(&i2c->adap);
devm_free_irq(dev, i2c->i2c_msix.vector, i2c);
pci_disable_msix(pdev);
--
1.9.1

2016-03-31 10:30:03

by Jan Glauber

Subject: [PATCH v5 10/14] i2c: octeon: Move read function before write

Just sorting the functions to be consistent with the other
read/write variants.

Signed-off-by: Jan Glauber <[email protected]>
---
drivers/i2c/busses/i2c-octeon.c | 94 ++++++++++++++++++++---------------------
1 file changed, 47 insertions(+), 47 deletions(-)

diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c
index 9621b66..95cd301 100644
--- a/drivers/i2c/busses/i2c-octeon.c
+++ b/drivers/i2c/busses/i2c-octeon.c
@@ -928,53 +928,6 @@ static int octeon_i2c_start(struct octeon_i2c *i2c, int first)
}

/**
- * octeon_i2c_write - send data to the bus via low-level controller
- * @i2c: The struct octeon_i2c
- * @target: Target address
- * @data: Pointer to the data to be sent
- * @length: Length of the data
- * @last: is last msg in combined operation?
- *
- * The address is sent over the bus, then the data.
- *
- * Returns 0 on success, otherwise a negative errno.
- */
-static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
- const u8 *data, int length, int first, int last)
-{
- int i, result;
-
- result = octeon_i2c_start(i2c, first);
- if (result)
- return result;
-
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
-
- result = octeon_i2c_wait(i2c);
- if (result)
- return result;
-
- for (i = 0; i < length; i++) {
- result = check_arb(i2c, false);
- if (result)
- return result;
-
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
-
- result = octeon_i2c_wait(i2c);
- if (result)
- return result;
- result = check_arb(i2c, false);
- if (result)
- return result;
- }
-
- return 0;
-}
-
-/**
* octeon_i2c_read - receive data from the bus via low-level controller
* @i2c: The struct octeon_i2c
* @target: Target address
@@ -1040,6 +993,53 @@ static int octeon_i2c_read(struct octeon_i2c *i2c, int target, u8 *data,
}

/**
+ * octeon_i2c_write - send data to the bus via low-level controller
+ * @i2c: The struct octeon_i2c
+ * @target: Target address
+ * @data: Pointer to the data to be sent
+ * @length: Length of the data
+ * @last: is last msg in combined operation?
+ *
+ * The address is sent over the bus, then the data.
+ *
+ * Returns 0 on success, otherwise a negative errno.
+ */
+static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
+ const u8 *data, int length, int first, int last)
+{
+ int i, result;
+
+ result = octeon_i2c_start(i2c, first);
+ if (result)
+ return result;
+
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
+
+ result = octeon_i2c_wait(i2c);
+ if (result)
+ return result;
+
+ for (i = 0; i < length; i++) {
+ result = check_arb(i2c, false);
+ if (result)
+ return result;
+
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
+
+ result = octeon_i2c_wait(i2c);
+ if (result)
+ return result;
+ result = check_arb(i2c, false);
+ if (result)
+ return result;
+ }
+
+ return 0;
+}
+
+/**
* octeon_i2c_xfer - The driver's master_xfer function
* @adap: Pointer to the i2c_adapter structure
* @msgs: Pointer to the messages to be processed
--
1.9.1

2016-03-31 10:30:48

by Jan Glauber

Subject: [PATCH v5 09/14] i2c: octeon: Add workaround for broken irqs on CN3860

From: David Daney <[email protected]>

CN3860 does not interrupt the CPU when the i2c status changes. If
we get a timeout, and see the status has in fact changed, we know we
have this problem, and drop back to polling.

Signed-off-by: David Daney <[email protected]>
Signed-off-by: Jan Glauber <[email protected]>
---
drivers/i2c/busses/i2c-octeon.c | 55 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 53 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c
index cc1fe51..9621b66 100644
--- a/drivers/i2c/busses/i2c-octeon.c
+++ b/drivers/i2c/busses/i2c-octeon.c
@@ -119,6 +119,8 @@ struct octeon_i2c {
void __iomem *twsi_base;
struct device *dev;
bool hlc_enabled;
+ bool broken_irq_mode;
+ bool broken_irq_check;
void (*int_en)(struct octeon_i2c *);
void (*int_dis)(struct octeon_i2c *);
void (*hlc_int_en)(struct octeon_i2c *);
@@ -375,10 +377,33 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c)
long time_left;
int first = 1;

+ if (i2c->broken_irq_mode) {
+ /*
+ * Some chip revisions seem to not assert the irq in
+ * the interrupt controller. So we must poll for the
+ * IFLG change.
+ */
+ u64 end = get_jiffies_64() + i2c->adap.timeout;
+
+ while (!octeon_i2c_test_iflg(i2c) &&
+ time_before64(get_jiffies_64(), end))
+ udelay(50);
+
+ return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT;
+ }
+
i2c->int_en(i2c);
time_left = wait_event_timeout(i2c->queue, poll_iflg(i2c, &first),
i2c->adap.timeout);
i2c->int_dis(i2c);
+
+ if (time_left <= 0 && i2c->broken_irq_check &&
+ octeon_i2c_test_iflg(i2c)) {
+ dev_err(i2c->dev,
+ "broken irq connection detected, switching to polling mode.\n");
+ i2c->broken_irq_mode = true;
+ return 0;
+ }
if (!time_left) {
dev_dbg(i2c->dev, "%s: timeout\n", __func__);
return -ETIMEDOUT;
@@ -512,17 +537,40 @@ static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
{
int time_left;

+ if (i2c->broken_irq_mode) {
+ /*
+ * Some cn38xx boards did not assert the irq in
+ * the interrupt controller. So we must poll for the
+ * IFLG change.
+ */
+ u64 end = get_jiffies_64() + i2c->adap.timeout;
+
+ while (!octeon_i2c_hlc_test_ready(i2c) &&
+ time_before64(get_jiffies_64(), end))
+ udelay(50);
+
+ return octeon_i2c_hlc_test_ready(i2c) ? 0 : -ETIMEDOUT;
+ }
+
i2c->hlc_int_en(i2c);
time_left = wait_event_interruptible_timeout(i2c->queue,
octeon_i2c_hlc_test_ready(i2c),
i2c->adap.timeout);
i2c->hlc_int_dis(i2c);
- if (!time_left) {
+ if (!time_left)
octeon_i2c_hlc_int_clear(i2c);
+
+ if (time_left <= 0 && i2c->broken_irq_check &&
+ octeon_i2c_hlc_test_ready(i2c)) {
+ dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");
+ i2c->broken_irq_mode = true;
+ return 0;
+ }
+
+ if (!time_left) {
dev_dbg(i2c->dev, "%s: timeout\n", __func__);
return -ETIMEDOUT;
}
-
if (time_left < 0) {
dev_dbg(i2c->dev, "%s: wait interrupted\n", __func__);
return time_left;
@@ -1154,6 +1202,9 @@ static int octeon_i2c_probe(struct platform_device *pdev)
goto out;
}

+ if (OCTEON_IS_MODEL(OCTEON_CN38XX))
+ i2c->broken_irq_check = true;
+
result = octeon_i2c_init_lowlevel(i2c);
if (result) {
dev_err(i2c->dev, "init low level failed\n");
--
1.9.1

2016-03-31 10:31:03

by Jan Glauber

Subject: [PATCH v5 06/14] i2c: octeon: Add support for cn78xx chips

From: David Daney <[email protected]>

cn78xx has a different interrupt architecture, so we have to manage
the interrupts differently.

Signed-off-by: David Daney <[email protected]>
Signed-off-by: Jan Glauber <[email protected]>
---
drivers/i2c/busses/i2c-octeon.c | 131 ++++++++++++++++++++++++++++++++++++----
1 file changed, 120 insertions(+), 11 deletions(-)

diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c
index bc0ed20..bd5915d 100644
--- a/drivers/i2c/busses/i2c-octeon.c
+++ b/drivers/i2c/busses/i2c-octeon.c
@@ -11,6 +11,7 @@
* warranty of any kind, whether express or implied.
*/

+#include <linux/atomic.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
@@ -112,11 +113,18 @@ struct octeon_i2c {
wait_queue_head_t queue;
struct i2c_adapter adap;
int irq;
+ int hlc_irq; /* For cn7890 only */
u32 twsi_freq;
int sys_freq;
void __iomem *twsi_base;
struct device *dev;
bool hlc_enabled;
+ void (*int_en)(struct octeon_i2c *);
+ void (*int_dis)(struct octeon_i2c *);
+ void (*hlc_int_en)(struct octeon_i2c *);
+ void (*hlc_int_dis)(struct octeon_i2c *);
+ atomic_t int_en_cnt;
+ atomic_t hlc_int_en_cnt;
};

static int reset_how;
@@ -214,6 +222,58 @@ static void octeon_i2c_disable_hlc(struct octeon_i2c *i2c)
}

/**
+ * octeon_i2c_int_enable78 - enable the CORE interrupt
+ * @i2c: The struct octeon_i2c
+ *
+ * The interrupt will be asserted when there is non-STAT_IDLE state in the
+ * SW_TWSI_EOP_TWSI_STAT register.
+ */
+static void octeon_i2c_int_enable78(struct octeon_i2c *i2c)
+{
+ atomic_inc_return(&i2c->int_en_cnt);
+ enable_irq(i2c->irq);
+}
+
+static void __octeon_i2c_irq_disable(atomic_t *cnt, int irq)
+{
+ int count;
+
+ /*
+ * The interrupt can be disabled in two places, but we only
+ * want to make the disable_irq_nosync() call once, so keep
+ * track with the atomic variable.
+ */
+ count = atomic_dec_if_positive(cnt);
+ if (count >= 0)
+ disable_irq_nosync(irq);
+}
+
+/* disable the CORE interrupt */
+static void octeon_i2c_int_disable78(struct octeon_i2c *i2c)
+{
+ __octeon_i2c_irq_disable(&i2c->int_en_cnt, i2c->irq);
+}
+
+/**
+ * octeon_i2c_hlc_int_enable78 - enable the ST interrupt
+ * @i2c: The struct octeon_i2c
+ *
+ * The interrupt will be asserted when there is non-STAT_IDLE state in
+ * the SW_TWSI_EOP_TWSI_STAT register.
+ */
+static void octeon_i2c_hlc_int_enable78(struct octeon_i2c *i2c)
+{
+ atomic_inc_return(&i2c->hlc_int_en_cnt);
+ enable_irq(i2c->hlc_irq);
+}
+
+/* disable the ST interrupt */
+static void octeon_i2c_hlc_int_disable78(struct octeon_i2c *i2c)
+{
+ __octeon_i2c_irq_disable(&i2c->hlc_int_en_cnt, i2c->hlc_irq);
+}
+
+/**
* octeon_i2c_unblock - unblock the bus
* @i2c: The struct octeon_i2c
*
@@ -250,7 +310,18 @@ static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
{
struct octeon_i2c *i2c = dev_id;

- octeon_i2c_int_disable(i2c);
+ i2c->int_dis(i2c);
+ wake_up(&i2c->queue);
+
+ return IRQ_HANDLED;
+}
+
+/* HLC interrupt service routine */
+static irqreturn_t octeon_i2c_hlc_isr78(int irq, void *dev_id)
+{
+ struct octeon_i2c *i2c = dev_id;
+
+ i2c->hlc_int_dis(i2c);
wake_up(&i2c->queue);

return IRQ_HANDLED;
@@ -276,10 +347,10 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c)
{
long time_left;

- octeon_i2c_int_enable(i2c);
+ i2c->int_en(i2c);
time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),
i2c->adap.timeout);
- octeon_i2c_int_disable(i2c);
+ i2c->int_dis(i2c);
if (!time_left) {
dev_dbg(i2c->dev, "%s: timeout\n", __func__);
return -ETIMEDOUT;
@@ -413,11 +484,11 @@ static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)
{
int time_left;

- octeon_i2c_hlc_int_enable(i2c);
+ i2c->hlc_int_en(i2c);
time_left = wait_event_interruptible_timeout(i2c->queue,
octeon_i2c_hlc_test_ready(i2c),
i2c->adap.timeout);
- octeon_i2c_int_disable(i2c);
+ i2c->hlc_int_dis(i2c);
if (!time_left) {
octeon_i2c_hlc_int_clear(i2c);
dev_dbg(i2c->dev, "%s: timeout\n", __func__);
@@ -969,14 +1040,26 @@ static struct i2c_adapter octeon_i2c_ops = {
static int octeon_i2c_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
+ int irq, result = 0, hlc_irq = 0;
struct resource *res_mem;
struct octeon_i2c *i2c;
- int irq, result = 0;
-
- /* All adaptors have an irq. */
- irq = platform_get_irq(pdev, 0);
- if (irq < 0)
- return irq;
+ bool cn78xx_style;
+
+ cn78xx_style = of_device_is_compatible(node, "cavium,octeon-7890-twsi");
+ if (cn78xx_style) {
+ hlc_irq = platform_get_irq(pdev, 0);
+ if (hlc_irq < 0)
+ return hlc_irq;
+
+ irq = platform_get_irq(pdev, 2);
+ if (irq < 0)
+ return irq;
+ } else {
+ /* All adaptors have an irq. */
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+ }

i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
if (!i2c) {
@@ -1011,6 +1094,31 @@ static int octeon_i2c_probe(struct platform_device *pdev)

i2c->irq = irq;

+ if (cn78xx_style) {
+ i2c->hlc_irq = hlc_irq;
+
+ i2c->int_en = octeon_i2c_int_enable78;
+ i2c->int_dis = octeon_i2c_int_disable78;
+ i2c->hlc_int_en = octeon_i2c_hlc_int_enable78;
+ i2c->hlc_int_dis = octeon_i2c_hlc_int_disable78;
+
+ irq_set_status_flags(i2c->irq, IRQ_NOAUTOEN);
+ irq_set_status_flags(i2c->hlc_irq, IRQ_NOAUTOEN);
+
+ result = devm_request_irq(&pdev->dev, i2c->hlc_irq,
+ octeon_i2c_hlc_isr78, 0,
+ DRV_NAME, i2c);
+ if (result < 0) {
+ dev_err(i2c->dev, "failed to attach interrupt\n");
+ goto out;
+ }
+ } else {
+ i2c->int_en = octeon_i2c_int_enable;
+ i2c->int_dis = octeon_i2c_int_disable;
+ i2c->hlc_int_en = octeon_i2c_hlc_int_enable;
+ i2c->hlc_int_dis = octeon_i2c_int_disable;
+ }
+
result = devm_request_irq(&pdev->dev, i2c->irq,
octeon_i2c_isr, 0, DRV_NAME, i2c);
if (result < 0) {
@@ -1056,6 +1164,7 @@ static int octeon_i2c_remove(struct platform_device *pdev)

static const struct of_device_id octeon_i2c_match[] = {
{ .compatible = "cavium,octeon-3860-twsi", },
+ { .compatible = "cavium,octeon-7890-twsi", },
{},
};
MODULE_DEVICE_TABLE(of, octeon_i2c_match);
--
1.9.1

2016-03-31 10:31:02

by Jan Glauber

Subject: [PATCH v5 07/14] i2c: octeon: Flush TWSI writes with readback

From: Peter Swain <[email protected]>

Signed-off-by: Peter Swain <[email protected]>
Signed-off-by: Jan Glauber <[email protected]>
Acked-by: David Daney <[email protected]>
---
drivers/i2c/busses/i2c-octeon.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c
index bd5915d..44ce9d4 100644
--- a/drivers/i2c/busses/i2c-octeon.c
+++ b/drivers/i2c/busses/i2c-octeon.c
@@ -129,6 +129,12 @@ struct octeon_i2c {

static int reset_how;

+static void writeqflush(u64 val, void __iomem *addr)
+{
+ __raw_writeq(val, addr);
+ __raw_readq(addr); /* wait for write to land */
+}
+
/**
* octeon_i2c_write_sw - write an I2C core register
* @i2c: The struct octeon_i2c
@@ -189,8 +195,7 @@ static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
*/
static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
{
- __raw_writeq(data, i2c->twsi_base + TWSI_INT);
- __raw_readq(i2c->twsi_base + TWSI_INT);
+ writeqflush(data, i2c->twsi_base + TWSI_INT);
}

/**
@@ -576,10 +581,10 @@ static int octeon_i2c_simple_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)

for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)
ext |= (u64) msgs[0].buf[j] << (8 * i);
- __raw_writeq(ext, i2c->twsi_base + SW_TWSI_EXT);
+ writeqflush(ext, i2c->twsi_base + SW_TWSI_EXT);
}

- __raw_writeq(cmd, i2c->twsi_base + SW_TWSI);
+ writeqflush(cmd, i2c->twsi_base + SW_TWSI);

ret = octeon_i2c_hlc_wait(i2c);
if (ret)
@@ -625,7 +630,7 @@ static int octeon_i2c_ia_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)
cmd |= (u64) msgs[0].buf[0] << SW_TWSI_IA_SHIFT;

octeon_i2c_hlc_int_clear(i2c);
- __raw_writeq(cmd, i2c->twsi_base + SW_TWSI);
+ writeqflush(cmd, i2c->twsi_base + SW_TWSI);

ret = octeon_i2c_hlc_wait(i2c);
if (ret)
@@ -685,10 +690,10 @@ static int octeon_i2c_ia_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)
set_ext = true;
}
if (set_ext)
- __raw_writeq(ext, i2c->twsi_base + SW_TWSI_EXT);
+ writeqflush(ext, i2c->twsi_base + SW_TWSI_EXT);

octeon_i2c_hlc_int_clear(i2c);
- __raw_writeq(cmd, i2c->twsi_base + SW_TWSI);
+ writeqflush(cmd, i2c->twsi_base + SW_TWSI);

ret = octeon_i2c_hlc_wait(i2c);
if (ret)
--
1.9.1

2016-03-31 10:28:46

by Jan Glauber

Subject: [PATCH v5 02/14] i2c: octeon: Move set-clock and init-lowlevel upward

No functional change, just moving the functions upward in
preparation of improving the recovery.

Signed-off-by: Jan Glauber <[email protected]>
---
drivers/i2c/busses/i2c-octeon.c | 126 ++++++++++++++++++++--------------------
1 file changed, 63 insertions(+), 63 deletions(-)

diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c
index c4abf16..f647667 100644
--- a/drivers/i2c/busses/i2c-octeon.c
+++ b/drivers/i2c/busses/i2c-octeon.c
@@ -214,6 +214,69 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c)
return 0;
}

+/* calculate and set clock divisors */
+static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
+{
+ int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
+ int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
+
+ for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
+ /*
+ * An mdiv value of less than 2 seems to not work well
+ * with ds1337 RTCs, so we constrain it to larger values.
+ */
+ for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
+ /*
+ * For given ndiv and mdiv values check the
+ * two closest thp values.
+ */
+ tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
+ tclk *= (1 << ndiv_idx);
+ thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
+
+ for (inc = 0; inc <= 1; inc++) {
+ thp_idx = thp_base + inc;
+ if (thp_idx < 5 || thp_idx > 0xff)
+ continue;
+
+ foscl = i2c->sys_freq / (2 * (thp_idx + 1));
+ foscl = foscl / (1 << ndiv_idx);
+ foscl = foscl / (mdiv_idx + 1) / 10;
+ diff = abs(foscl - i2c->twsi_freq);
+ if (diff < delta_hz) {
+ delta_hz = diff;
+ thp = thp_idx;
+ mdiv = mdiv_idx;
+ ndiv = ndiv_idx;
+ }
+ }
+ }
+ }
+ octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
+}
+
+static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
+{
+ u8 status;
+ int tries;
+
+ /* disable high level controller, enable bus access */
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
+
+ /* reset controller */
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);
+
+ for (tries = 10; tries; tries--) {
+ udelay(1);
+ status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
+ if (status == STAT_IDLE)
+ return 0;
+ }
+ dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
+ return -EIO;
+}
+
/**
* octeon_i2c_start - send START to the bus
* @i2c: The struct octeon_i2c
@@ -428,69 +491,6 @@ static struct i2c_adapter octeon_i2c_ops = {
.algo = &octeon_i2c_algo,
};

-/* calculate and set clock divisors */
-static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
-{
- int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
- int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
-
- for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
- /*
- * An mdiv value of less than 2 seems to not work well
- * with ds1337 RTCs, so we constrain it to larger values.
- */
- for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
- /*
- * For given ndiv and mdiv values check the
- * two closest thp values.
- */
- tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
- tclk *= (1 << ndiv_idx);
- thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
-
- for (inc = 0; inc <= 1; inc++) {
- thp_idx = thp_base + inc;
- if (thp_idx < 5 || thp_idx > 0xff)
- continue;
-
- foscl = i2c->sys_freq / (2 * (thp_idx + 1));
- foscl = foscl / (1 << ndiv_idx);
- foscl = foscl / (mdiv_idx + 1) / 10;
- diff = abs(foscl - i2c->twsi_freq);
- if (diff < delta_hz) {
- delta_hz = diff;
- thp = thp_idx;
- mdiv = mdiv_idx;
- ndiv = ndiv_idx;
- }
- }
- }
- }
- octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
-}
-
-static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
-{
- u8 status;
- int tries;
-
- /* disable high level controller, enable bus access */
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
-
- /* reset controller */
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);
-
- for (tries = 10; tries; tries--) {
- udelay(1);
- status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
- if (status == STAT_IDLE)
- return 0;
- }
- dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
- return -EIO;
-}
-
static int octeon_i2c_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
--
1.9.1

2016-03-31 10:31:41

by Jan Glauber

Subject: [PATCH v5 05/14] dt-bindings: i2c: Add Octeon cn78xx TWSI

Add compatible string for Cavium Octeon cn78XX SOCs TWSI.

Cc: Rob Herring <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Ian Campbell <[email protected]>
Cc: Kumar Gala <[email protected]>

Signed-off-by: Jan Glauber <[email protected]>
Acked-by: David Daney <[email protected]>
---
Documentation/devicetree/bindings/i2c/i2c-octeon.txt | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-octeon.txt b/Documentation/devicetree/bindings/i2c/i2c-octeon.txt
index dced82e..872d485 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-octeon.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-octeon.txt
@@ -4,6 +4,12 @@

Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.

+ or
+
+ compatible: "cavium,octeon-7890-twsi"
+
+ Compatibility with cn78XX SOCs.
+
- reg: The base address of the TWSI/I2C bus controller register bank.

- #address-cells: Must be <1>.
--
1.9.1

2016-03-31 10:32:03

by Jan Glauber

Subject: [PATCH v5 03/14] i2c: octeon: Improve error handling

From: Peter Swain <[email protected]>

Consider more status codes and improve error handling.
Distinguish handling for first and last part of a message.

TODO: Convert to use the i2c recovery framework.

Signed-off-by: Peter Swain <[email protected]>
Signed-off-by: Jan Glauber <[email protected]>
---
drivers/i2c/busses/i2c-octeon.c | 244 +++++++++++++++++++++++++++++-----------
1 file changed, 178 insertions(+), 66 deletions(-)

diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c
index f647667..a037245 100644
--- a/drivers/i2c/busses/i2c-octeon.c
+++ b/drivers/i2c/busses/i2c-octeon.c
@@ -56,12 +56,34 @@
#define TWSI_CTL_AAK 0x04 /* Assert ACK */

/* Some status values */
+#define STAT_ERROR 0x00
#define STAT_START 0x08
#define STAT_RSTART 0x10
#define STAT_TXADDR_ACK 0x18
+#define STAT_TXADDR_NAK 0x20
#define STAT_TXDATA_ACK 0x28
+#define STAT_TXDATA_NAK 0x30
+#define STAT_LOST_ARB_38 0x38
#define STAT_RXADDR_ACK 0x40
+#define STAT_RXADDR_NAK 0x48
#define STAT_RXDATA_ACK 0x50
+#define STAT_RXDATA_NAK 0x58
+#define STAT_SLAVE_60 0x60
+#define STAT_LOST_ARB_68 0x68
+#define STAT_SLAVE_70 0x70
+#define STAT_LOST_ARB_78 0x78
+#define STAT_SLAVE_80 0x80
+#define STAT_SLAVE_88 0x88
+#define STAT_GENDATA_ACK 0x90
+#define STAT_GENDATA_NAK 0x98
+#define STAT_SLAVE_A0 0xA0
+#define STAT_SLAVE_A8 0xA8
+#define STAT_LOST_ARB_B0 0xB0
+#define STAT_SLAVE_LOST 0xB8
+#define STAT_SLAVE_NAK 0xC0
+#define STAT_SLAVE_ACK 0xC8
+#define STAT_AD2W_ACK 0xD0
+#define STAT_AD2W_NAK 0xD8
#define STAT_IDLE 0xF8

/* TWSI_INT values */
@@ -79,6 +101,8 @@ struct octeon_i2c {
struct device *dev;
};

+static int reset_how;
+
/**
* octeon_i2c_write_sw - write an I2C core register
* @i2c: The struct octeon_i2c
@@ -186,7 +210,6 @@ static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
return IRQ_HANDLED;
}

-
static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
{
return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
@@ -214,6 +237,66 @@ static int octeon_i2c_wait(struct octeon_i2c *i2c)
return 0;
}

+static int octeon_i2c_lost_arb(u8 code, int final_read)
+{
+ switch (code) {
+ /* Arbitration lost */
+ case STAT_LOST_ARB_38:
+ case STAT_LOST_ARB_68:
+ case STAT_LOST_ARB_78:
+ case STAT_LOST_ARB_B0:
+ return -EAGAIN;
+
+ /* Being addressed as slave, should back off & listen */
+ case STAT_SLAVE_60:
+ case STAT_SLAVE_70:
+ case STAT_GENDATA_ACK:
+ case STAT_GENDATA_NAK:
+ return -EIO;
+
+ /* Core busy as slave */
+ case STAT_SLAVE_80:
+ case STAT_SLAVE_88:
+ case STAT_SLAVE_A0:
+ case STAT_SLAVE_A8:
+ case STAT_SLAVE_LOST:
+ case STAT_SLAVE_NAK:
+ case STAT_SLAVE_ACK:
+ return -EIO;
+
+ /* ACK allowed on pre-terminal bytes only */
+ case STAT_RXDATA_ACK:
+ if (!final_read)
+ return 0;
+ return -EAGAIN;
+
+ /* NAK allowed on terminal byte only */
+ case STAT_RXDATA_NAK:
+ if (final_read)
+ return 0;
+ return -EAGAIN;
+ case STAT_TXDATA_NAK:
+ case STAT_TXADDR_NAK:
+ case STAT_RXADDR_NAK:
+ case STAT_AD2W_NAK:
+ return -EAGAIN;
+ }
+ return 0;
+}
+
+static int check_arb(struct octeon_i2c *i2c, int final_read)
+{
+ return octeon_i2c_lost_arb(octeon_i2c_read_sw(i2c,
+ SW_TWSI_EOP_TWSI_STAT), final_read);
+}
+
+/* send STOP to the bus */
+static void octeon_i2c_stop(struct octeon_i2c *i2c)
+{
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
+ TWSI_CTL_ENAB | TWSI_CTL_STP);
+}
+
/* calculate and set clock divisors */
static void octeon_i2c_set_clock(struct octeon_i2c *i2c)
{
@@ -277,71 +360,103 @@ static int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)
return -EIO;
}

+/*
+ * TWSI state seems stuck. Not sure if it's TWSI-engine state or something
+ * else on bus. The initial _stop() is always harmless, it just resets state
+ * machine, does not _transmit_ STOP unless engine was active.
+ */
+static int start_unstick(struct octeon_i2c *i2c)
+{
+ octeon_i2c_stop(i2c);
+
+ /*
+ * Response is escalated over successive calls,
+ * as EAGAIN provokes retries from i2c/core.
+ */
+ switch (reset_how++ % 4) {
+ case 0:
+ /* just the stop above */
+ break;
+ case 1:
+ /*
+ * Controller refused to send start flag. May be a
+ * client is holding SDA low? Let's try to free it.
+ */
+ octeon_i2c_unblock(i2c);
+ break;
+ case 2:
+ /* re-init our TWSI hardware */
+ octeon_i2c_init_lowlevel(i2c);
+ break;
+ default:
+ /* retry in caller */
+ reset_how = 0;
+ return -EAGAIN;
+ }
+ return 0;
+}
+
/**
* octeon_i2c_start - send START to the bus
* @i2c: The struct octeon_i2c
+ * @first: first msg in combined operation?
*
* Returns 0 on success, otherwise a negative errno.
*/
-static int octeon_i2c_start(struct octeon_i2c *i2c)
+static int octeon_i2c_start(struct octeon_i2c *i2c, int first)
{
int result;
u8 data;

- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
- TWSI_CTL_ENAB | TWSI_CTL_STA);
+ while (1) {
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
+ TWSI_CTL_ENAB | TWSI_CTL_STA);

- result = octeon_i2c_wait(i2c);
- if (result) {
- if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
- /*
- * Controller refused to send start flag May
- * be a client is holding SDA low - let's try
- * to free it.
- */
- octeon_i2c_unblock(i2c);
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
- TWSI_CTL_ENAB | TWSI_CTL_STA);
- result = octeon_i2c_wait(i2c);
+ result = octeon_i2c_wait(i2c);
+ data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
+
+ switch (data) {
+ case STAT_START:
+ case STAT_RSTART:
+ if (!first)
+ return -EAGAIN;
+ reset_how = 0;
+ return 0;
+ case STAT_RXADDR_ACK:
+ if (first)
+ return -EAGAIN;
+ return start_unstick(i2c);
+ /*
+ * case STAT_IDLE:
+ * case STAT_ERROR:
+ */
+ default:
+ if (!first)
+ return -EAGAIN;
+ start_unstick(i2c);
}
- if (result)
- return result;
}
-
- data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
- if ((data != STAT_START) && (data != STAT_RSTART)) {
- dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
- return -EIO;
- }
-
return 0;
}

-/* send STOP to the bus */
-static void octeon_i2c_stop(struct octeon_i2c *i2c)
-{
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
- TWSI_CTL_ENAB | TWSI_CTL_STP);
-}
-
/**
* octeon_i2c_write - send data to the bus via low-level controller
* @i2c: The struct octeon_i2c
* @target: Target address
* @data: Pointer to the data to be sent
* @length: Length of the data
+ * @last: is last msg in combined operation?
*
* The address is sent over the bus, then the data.
*
* Returns 0 on success, otherwise a negative errno.
*/
static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
- const u8 *data, int length)
+ const u8 *data, int length, int first, int last)
{
int i, result;
- u8 tmp;

- result = octeon_i2c_start(i2c);
+ result = octeon_i2c_start(i2c, first);
if (result)
return result;

@@ -353,14 +468,9 @@ static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
return result;

for (i = 0; i < length; i++) {
- tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
-
- if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
- dev_err(i2c->dev,
- "%s: bad status before write (0x%x)\n",
- __func__, tmp);
- return -EIO;
- }
+ result = check_arb(i2c, false);
+ if (result)
+ return result;

octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
@@ -368,6 +478,9 @@ static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
result = octeon_i2c_wait(i2c);
if (result)
return result;
+ result = check_arb(i2c, false);
+ if (result)
+ return result;
}

return 0;
@@ -379,54 +492,51 @@ static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
* @target: Target address
* @data: Pointer to the location to store the data
* @rlength: Length of the data
+ * @phase: which phase of a combined operation.
* @recv_len: flag for length byte
*
* The address is sent over the bus, then the data is read.
*
* Returns 0 on success, otherwise a negative errno.
*/
-static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
- u8 *data, u16 *rlength, bool recv_len)
+static int octeon_i2c_read(struct octeon_i2c *i2c, int target, u8 *data,
+ u16 *rlength, bool first, bool last, bool recv_len)
{
+ u8 ctl = TWSI_CTL_ENAB | TWSI_CTL_AAK;
int i, result, length = *rlength;
u8 tmp;

if (length < 1)
return -EINVAL;

- result = octeon_i2c_start(i2c);
+ result = octeon_i2c_start(i2c, first);
if (result)
return result;

octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target << 1) | 1);
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
-
- result = octeon_i2c_wait(i2c);
- if (result)
- return result;

- for (i = 0; i < length; i++) {
+ for (i = 0; i < length; ) {
tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
+ result = octeon_i2c_lost_arb(tmp, !(ctl & TWSI_CTL_AAK));
+ if (result)
+ return result;

- if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
- dev_err(i2c->dev,
- "%s: bad status before read (0x%x)\n",
- __func__, tmp);
- return -EIO;
+ switch (tmp) {
+ case STAT_RXDATA_ACK:
+ case STAT_RXDATA_NAK:
+ data[i++] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
}

- if (i + 1 < length)
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
- TWSI_CTL_ENAB | TWSI_CTL_AAK);
- else
- octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
- TWSI_CTL_ENAB);
+ /* NAK last recv'd byte, as a no-more-please */
+ if (last && i == length - 1)
+ ctl &= ~TWSI_CTL_AAK;

+ /* clr iflg to allow next event */
+ octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, ctl);
result = octeon_i2c_wait(i2c);
if (result)
return result;

- data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
if (recv_len && i == 0) {
if (data[i] > I2C_SMBUS_BLOCK_MAX + 1) {
dev_err(i2c->dev,
@@ -457,6 +567,7 @@ static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,

for (i = 0; ret == 0 && i < num; i++) {
struct i2c_msg *pmsg = &msgs[i];
+ bool last = (i == (num - 1));

dev_dbg(i2c->dev,
"Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
@@ -464,10 +575,11 @@ static int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
pmsg->len, pmsg->addr, i + 1, num);
if (pmsg->flags & I2C_M_RD)
ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
- &pmsg->len, pmsg->flags & I2C_M_RECV_LEN);
+ &pmsg->len, !i, last,
+ pmsg->flags & I2C_M_RECV_LEN);
else
ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
- pmsg->len);
+ pmsg->len, !i, last);
}
octeon_i2c_stop(i2c);

--
1.9.1

2016-03-31 10:32:52

by Jan Glauber

Subject: [PATCH v5 01/14] i2c: octeon: Increase retry default and use fixed timeout value

Convert the adapter timeout to 2 ms independently of depending on CONFIG_HZ.
CONFIG_HZ is 100 for MIPS Cavium-Octeon so the timeout value is not changed.

Also set retries to 5 to improve robustness.

Signed-off-by: Jan Glauber <[email protected]>
---
drivers/i2c/busses/i2c-octeon.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c
index 46fb6c4..c4abf16 100644
--- a/drivers/i2c/busses/i2c-octeon.c
+++ b/drivers/i2c/busses/i2c-octeon.c
@@ -426,7 +426,6 @@ static struct i2c_adapter octeon_i2c_ops = {
.owner = THIS_MODULE,
.name = "OCTEON adapter",
.algo = &octeon_i2c_algo,
- .timeout = HZ / 50,
};

/* calculate and set clock divisors */
@@ -553,6 +552,8 @@ static int octeon_i2c_probe(struct platform_device *pdev)
octeon_i2c_set_clock(i2c);

i2c->adap = octeon_i2c_ops;
+ i2c->adap.timeout = msecs_to_jiffies(2);
+ i2c->adap.retries = 5;
i2c->adap.dev.parent = &pdev->dev;
i2c->adap.dev.of_node = node;
i2c_set_adapdata(&i2c->adap, i2c);
--
1.9.1