2022-03-17 07:00:39

by Sandipan Das

Subject: [PATCH 4/7] perf/x86/amd/core: Detect available counters

If AMD Performance Monitoring Version 2 (PerfMonV2) is
supported, use CPUID Fn80000022[EBX] to detect the number
of Core PMCs. This offers more flexibility if the counts
change across processor families.

Signed-off-by: Sandipan Das <[email protected]>
---
arch/x86/events/amd/core.c | 5 +++++
arch/x86/include/asm/perf_event.h | 8 ++++++++
2 files changed, 13 insertions(+)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index a074af97faa9..05d79afe5173 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -980,9 +980,14 @@ static int __init amd_core_pmu_init(void)

/* Check for Performance Monitoring v2 support */
if (boot_cpu_has(X86_FEATURE_PERFMON_V2)) {
+ int ebx = cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES);
+
/* Update PMU version for later usage */
x86_pmu.version = 2;

+ /* Find the number of available Core PMCs */
+ x86_pmu.num_counters = EXT_PERFMON_DEBUG_NUM_CORE_PMC(ebx);
+
amd_pmu_global_cntr_mask = (1ULL << x86_pmu.num_counters) - 1;
}

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 8fc1b5003713..d7dfef3e998d 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -365,6 +365,14 @@ struct pebs_xmm {
u64 xmm[16*2]; /* two entries for each register */
};

+/*
+ * AMD Extended Performance Monitoring and Debug cpuid feature detection
+ */
+#define EXT_PERFMON_DEBUG_FEATURES 0x80000022
+
+/* Extended Performance Monitoring and Debug EBX feature bits */
+#define EXT_PERFMON_DEBUG_NUM_CORE_PMC(ebx) ((ebx) & GENMASK(3, 0))
+
/*
* IBS cpuid feature detection
*/
--
2.32.0

2022-03-17 16:14:31

by Peter Zijlstra

Subject: Re: [PATCH 4/7] perf/x86/amd/core: Detect available counters

On Thu, Mar 17, 2022 at 11:58:33AM +0530, Sandipan Das wrote:
> If AMD Performance Monitoring Version 2 (PerfMonV2) is
> supported, use CPUID Fn80000022[EBX] to detect the number
> of Core PMCs. This offers more flexibility if the counts
> change across processor families.
>
> Signed-off-by: Sandipan Das <[email protected]>
> ---
> arch/x86/events/amd/core.c | 5 +++++
> arch/x86/include/asm/perf_event.h | 8 ++++++++
> 2 files changed, 13 insertions(+)
>
> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
> index a074af97faa9..05d79afe5173 100644
> --- a/arch/x86/events/amd/core.c
> +++ b/arch/x86/events/amd/core.c
> @@ -980,9 +980,14 @@ static int __init amd_core_pmu_init(void)
>
> /* Check for Performance Monitoring v2 support */
> if (boot_cpu_has(X86_FEATURE_PERFMON_V2)) {
> + int ebx = cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES);
> +
> /* Update PMU version for later usage */
> x86_pmu.version = 2;
>
> + /* Find the number of available Core PMCs */
> + x86_pmu.num_counters = EXT_PERFMON_DEBUG_NUM_CORE_PMC(ebx);
> +
> amd_pmu_global_cntr_mask = (1ULL << x86_pmu.num_counters) - 1;
> }

I prefer using unions like cpuid10_ebx. Such much easier to read than
all this shouting.