LinuxLists.cc - arch/arm64/kvm/sys_regs.c:2108:5-25: duplicated argument to & or

2023-12-05 14:31:39

Subject: arch/arm64/kvm/sys_regs.c:2108:5-25: duplicated argument to & or | (fwd)

Hello,

Lines 2108 and 2110
julia

---------- Forwarded Date: Tue, 5 Dec 2023 From: kernel test To: BCC: :::::: branch date: 16 hours ago
:::::: commit date: 9 weeks ago
config: arm64-randconfig-r061-20231203 compiler: aarch64-linux-gcc reproduce: ( cocci warnings: (new >> arch/arm64/kvm/sys
vim +2108 arch/arm64/kvm/sys_regs.c
9da117eec9243f Jintack Lim 7c8c5e6a9101ea Marc Zyngier 7c8c5e6a9101ea Marc Zyngier 7c8c5e6a9101ea Marc Zyngier 7609c1251f9d8b Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 7dabf02f43a167 Oliver Upton 7dabf02f43a167 Oliver Upton 7dabf02f43a167 Oliver Upton 7c8c5e6a9101ea Marc Zyngier 7c8c5e6a9101ea Marc Zyngier 7606e07856e014 Mark Rutland d282fa3c5ccb7a Marc Zyngier d282fa3c5ccb7a Marc Zyngier 7606e07856e014 Mark Rutland d282fa3c5ccb7a Marc Zyngier d282fa3c5ccb7a Marc Zyngier 7606e07856e014 Mark Rutland d282fa3c5ccb7a Marc Zyngier d282fa3c5ccb7a Marc Zyngier 7c8c5e6a9101ea Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier ee1b64e6ccddbd Mark Rutland ee1b64e6ccddbd Mark Rutland 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier 0c557ed4983b7a Marc Zyngier ee1b64e6ccddbd Mark Rutland f24adc65c5568a Oliver Upton d42e26716d038d Oliver Upton 187de7c2aad86c Mark Brown ee1b64e6ccddbd Mark Rutland ee1b64e6ccddbd Mark Rutland ee1b64e6ccddbd Mark Rutland ee1b64e6ccddbd Mark Rutland ee1b64e6ccddbd Mark Rutland ee1b64e6ccddbd Mark Rutland ee1b64e6ccddbd Mark Rutland ee1b64e6ccddbd Mark Rutland ee1b64e6ccddbd Mark Rutland ee1b64e6ccddbd Mark Rutland ee1b64e6ccddbd Mark Rutland ee1b64e6ccddbd Mark Rutland 62a89c44954f09 Marc Zyngier 851050a573e1d2 Mark Rutland 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin d5efec7ed826b3 Oliver Upton d5efec7ed826b3 Oliver Upton c118cead07a762 Jing Zhang c118cead07a762 Jing Zhang c118cead07a762 Jing Zhang c118cead07a762 Jing Zhang c118cead07a762 Jing Zhang c118cead07a762 Jing Zhang 9f9917bc71b083 Oliver Upton 9f9917bc71b083 Oliver Upton 93390c0a1b20b9 Dave Martin d5efec7ed826b3 Oliver Upton d5efec7ed826b3 Oliver Upton d5efec7ed826b3 Oliver Upton d5efec7ed826b3 Oliver Upton 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin d5efec7ed826b3 Oliver Upton d5efec7ed826b3 Oliver Upton d5efec7ed826b3 Oliver Upton d5efec7ed826b3 Oliver Upton d5efec7ed826b3 Oliver Upton d5efec7ed826b3 Oliver Upton d5efec7ed826b3 Oliver Upton d5efec7ed826b3 Oliver Upton 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin d5efec7ed826b3 Oliver Upton d5efec7ed826b3 Oliver Upton d5efec7ed826b3 Oliver Upton 93390c0a1b20b9 Dave Martin d5efec7ed826b3 Oliver Upton dd35ec07045753 Anshuman d5efec7ed826b3 Oliver Upton 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin c39f5974d38f72 Jing Zhang c39f5974d38f72 Jing Zhang c39f5974d38f72 Jing Zhang 686672407e6eaf Oliver Upton c39f5974d38f72 Jing Zhang c39f5974d38f72 Jing Zhang 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin c512298eed0360 Andrew Jones 90807748ca3ac4 Mark Brown 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin c118cead07a762 Jing Zhang c118cead07a762 Jing Zhang c118cead07a762 Jing Zhang c118cead07a762 Jing Zhang c118cead07a762 Jing Zhang 9f9917bc71b083 Oliver Upton 9f9917bc71b083 Oliver Upton 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 56d77aa8bdf527 Oliver Upton 56d77aa8bdf527 Oliver Upton 56d77aa8bdf527 Oliver Upton 56d77aa8bdf527 Oliver Upton 56d77aa8bdf527 Oliver Upton 56d77aa8bdf527 Oliver Upton 56d77aa8bdf527 Oliver Upton 56d77aa8bdf527 Oliver Upton 56d77aa8bdf527 Oliver Upton 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang d5a32b60dc184c Jing Zhang 8ef67c67e63780 Joey Gouly 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 93390c0a1b20b9 Dave Martin 851050a573e1d2 Mark Rutland af4738290d9dfe James Morse 851050a573e1d2 Mark Rutland 2ac638fc5724f0 Catalin Marinas e1f358b5046479 Steven Price e1f358b5046479 Steven Price 2ac638fc5724f0 Catalin Marinas 73433762fcaeb9 Dave Martin cc427cbb15375f Suzuki K Poulose 90807748ca3ac4 Mark Brown 90807748ca3ac4 Mark Brown 851050a573e1d2 Mark Rutland 851050a573e1d2 Mark Rutland 851050a573e1d2 Mark Rutland fbff560682323d Joey Gouly 851050a573e1d2 Mark Rutland 384b40caa8afae Mark Rutland 384b40caa8afae Mark Rutland 384b40caa8afae Mark Rutland 384b40caa8afae Mark Rutland 384b40caa8afae Mark Rutland 384b40caa8afae Mark Rutland 9da117eec9243f Jintack Lim 9da117eec9243f Jintack Lim 9da117eec9243f Jintack Lim 851050a573e1d2 Mark Rutland 851050a573e1d2 Mark Rutland 851050a573e1d2 Mark Rutland 558daf693e0c7e Dongjiu Geng 558daf693e0c7e Dongjiu Geng 558daf693e0c7e Dongjiu Geng 558daf693e0c7e Dongjiu Geng 558daf693e0c7e Dongjiu Geng 558daf693e0c7e Dongjiu Geng 558daf693e0c7e Dongjiu Geng 558daf693e0c7e Dongjiu Geng 558daf693e0c7e Dongjiu Geng 558daf693e0c7e Dongjiu Geng e1f358b5046479 Steven Price e1f358b5046479 Steven Price 2ac638fc5724f0 Catalin Marinas 851050a573e1d2 Mark Rutland 851050a573e1d2 Mark Rutland 7c8c5e6a9101ea Marc Zyngier 13611bc80d3da1 Alexandru Elisei 13611bc80d3da1 Alexandru Elisei 13611bc80d3da1 Alexandru Elisei 13611bc80d3da1 Alexandru Elisei 13611bc80d3da1 Alexandru Elisei 13611bc80d3da1 Alexandru Elisei 13611bc80d3da1 Alexandru Elisei 13611bc80d3da1 Alexandru Elisei 13611bc80d3da1 Alexandru Elisei 13611bc80d3da1 Alexandru Elisei 13611bc80d3da1 Alexandru Elisei 13611bc80d3da1 Alexandru Elisei 13611bc80d3da1 Alexandru Elisei 9d2a55b403eea2 Xiang Chen 11663111cd49b4 Marc Zyngier 9d2a55b403eea2 Xiang Chen 11663111cd49b4 Marc Zyngier 46081078feb451 Marc Zyngier 7c8c5e6a9101ea Marc Zyngier 851050a573e1d2 Mark Rutland 86f9de9db1783b Joey Gouly 86f9de9db1783b Joey Gouly 851050a573e1d2 Mark Rutland 7c8c5e6a9101ea Marc Zyngier 2292552102b059 Marc Zyngier 2292552102b059 Marc Zyngier 2292552102b059 Marc Zyngier 2292552102b059 Marc Zyngier 2292552102b059 Marc Zyngier cc33c4e20185a3 Mark Rutland 9da117eec9243f Jintack Lim c773ae2b34760a James Morse db7dedd0de714a Christoffer Dall 7b1dba1f732562 Marc Zyngier e7f1d1eef48215 Marc Zyngier 7b1dba1f732562 Marc Zyngier e7f1d1eef48215 Marc Zyngier 7b1dba1f732562 Marc Zyngier e804d208979db6 Mark Rutland 03bd646d863d1e Marc Zyngier 03bd646d863d1e Marc Zyngier 7b1dba1f732562 Marc Zyngier e7f1d1eef48215 Marc Zyngier 7b1dba1f732562 Marc Zyngier e804d208979db6 Mark Rutland db7dedd0de714a Christoffer Dall 851050a573e1d2 Mark Rutland 851050a573e1d2 Mark Rutland 7c8c5e6a9101ea Marc Zyngier 484f86824a3d94 Marc Zyngier 484f86824a3d94 Marc Zyngier ed4ffaf49bf9ce Marc Zyngier ed4ffaf49bf9ce Marc Zyngier 851050a573e1d2 Mark Rutland 7c8c5e6a9101ea Marc Zyngier f7f2b15c3d42fa Ard Biesheuvel 7af0c2534f4c57 Akihiko Odaki 7af0c2534f4c57 Akihiko Odaki bf48040cd9b0c4 Akihiko Odaki 90807748ca3ac4 Mark Brown f7f2b15c3d42fa Ard Biesheuvel f7f2b15c3d42fa Ard Biesheuvel ec0067a63e5a37 Mark Brown 7c8c5e6a9101ea Marc Zyngier 9d2a55b403eea2 Xiang Chen 11663111cd49b4 Marc Zyngier 9d2a55b403eea2 Xiang Chen 11663111cd49b4 Marc Zyngier 9d2a55b403eea2 Xiang Chen 11663111cd49b4 Marc Zyngier 9d2a55b403eea2 Xiang Chen 11663111cd49b4 Marc Zyngier 7a3ba3095a32f9 Marc Zyngier 7a3ba3095a32f9 Marc Zyngier 7a3ba3095a32f9 Marc Zyngier 7a3ba3095a32f9 Marc Zyngier 9d2a55b403eea2 Xiang Chen 5a4309762356f0 Alexandru Elisei 7a3ba3095a32f9 Marc Zyngier 9d2a55b403eea2 Xiang Chen 0ab410a93d627a Marc Zyngier 9d2a55b403eea2 Xiang Chen 11663111cd49b4 Marc Zyngier 9d2a55b403eea2 Xiang Chen 11663111cd49b4 Marc Zyngier 9d2a55b403eea2 Xiang Chen 9228b26194d1cc Reiji Watanabe 9228b26194d1cc Reiji Watanabe 9d2a55b403eea2 Xiang Chen 11663111cd49b4 Marc Zyngier 9d2a55b403eea2 Xiang Chen 11663111cd49b4 Marc Zyngier 174ed3e47591d5 Mark Rutland 174ed3e47591d5 Mark Rutland d692b8ad6ec481 Shannon Zhao d692b8ad6ec481 Shannon Zhao 9d2a55b403eea2 Xiang Chen 11663111cd49b4 Marc Zyngier 9d2a55b403eea2 Xiang Chen 11663111cd49b4 Marc Zyngier 7c8c5e6a9101ea Marc Zyngier 851050a573e1d2 Mark Rutland 851050a573e1d2 Mark Rutland 90807748ca3ac4 Mark Brown 4fcdf106a4330b Ionela Voinescu ed4ffaf49bf9ce Marc Zyngier ed4ffaf49bf9ce Marc Zyngier 338b17933a6077 Marc Zyngier 338b17933a6077 Marc Zyngier 338b17933a6077 Marc Zyngier 338b17933a6077 Marc Zyngier 338b17933a6077 Marc Zyngier 338b17933a6077 Marc Zyngier 338b17933a6077 Marc Zyngier 338b17933a6077 Marc Zyngier 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 4fcdf106a4330b Ionela Voinescu 493cf9b723bcc8 Vladimir Murzin 493cf9b723bcc8 Vladimir Murzin 493cf9b723bcc8 Vladimir Murzin 493cf9b723bcc8 Vladimir Murzin 493cf9b723bcc8 Vladimir Murzin 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493cf9b723bcc8 Vladimir Murzin 493cf9b723bcc8 Vladimir Murzin 493cf9b723bcc8 Vladimir Murzin 493cf9b723bcc8 Vladimir Murzin 493cf9b723bcc8 Vladimir Murzin 493cf9b723bcc8 Vladimir Murzin 493cf9b723bcc8 Vladimir Murzin 493cf9b723bcc8 Vladimir Murzin 493cf9b723bcc8 Vladimir Murzin 493cf9b723bcc8 Vladimir Murzin 493cf9b723bcc8 Vladimir Murzin 62a89c44954f09 Marc Zyngier c605ee245097d0 Marc Zyngier c605ee245097d0 Marc Zyngier 84135d3d18da2f Andre Przywara 84135d3d18da2f Andre Przywara 84135d3d18da2f Andre Przywara c9a3c58f01fb0a Jintack Lim 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 051ff581ce70e8 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 174ed3e47591d5 Mark Rutland 174ed3e47591d5 Mark Rutland 9feb21ac57d530 Shannon Zhao 9feb21ac57d530 Shannon Zhao 9d2a55b403eea2 Xiang Chen 11663111cd49b4 Marc Zyngier 051ff581ce70e8 Shannon Zhao 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 75c76ab5a641b6 Marc Zyngier 6ff9dc238a53f4 Jintack Lim 50d2fe4648c50e Marc Zyngier 50d2fe4648c50e Marc Zyngier 50d2fe4648c50e Marc Zyngier 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 03fb54d0aa73cc Marc Zyngier 03fb54d0aa73cc Marc Zyngier 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 851050a573e1d2 Mark Rutland 50d2fe4648c50e Marc Zyngier 50d2fe4648c50e Marc Zyngier 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 851050a573e1d2 Mark Rutland 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim c88b093693ccbe Dave Martin 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 6ff9dc238a53f4 Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 280b748e871e5a Jintack Lim 6ff9dc238a53f4 Jintack Lim 62a89c44954f09 Marc Zyngier 62a89c44954f09 Marc Zyngier
--
0-DAY CI Kernel Test Service
<[email protected]>
il-protection#4b242e6620293e22272f0b2722383f38652722253e33652f2e3d">[email protected]
il-protection#5e32352e1e37302a3b32703d3133">[email protected], Julia Lawall <[email protected]>
_regs.c:2108:5-25: duplicated argument to & or |
ail-protection#036f6873436a6d77666f2d606c6e">[email protected]
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it.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git">https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
f5245c040fcc36ef2bde8
f83648a368b94d91c797f KVM: arm64: Allow userspace to change ID_AA64MMFR{0-2}_EL1
(https://download.01.org/0day-ci/archive/20231205/[email protected]/config)
(GCC) 13.2.0
://download.01.org/0day-ci/archive/20231205/202312052139.JHPX7I2z-lkp@intel.com/reproduce)">https://download.01.org/0day-ci/archive/20231205/[email protected]/reproduce)
in a separate patch/commit (i.e. not just a new version of
kindly add following tags
test robot <[email protected]>
Lawall <[email protected]>
/lore.kernel.org/r/202312052139.JHPX7I2z-lkp@intel.com/">https://lore.kernel.org/r/[email protected]/
ones prefixed by >>)
_regs.c:2108:5-25: duplicated argument to & or |
/> 2023-02-09 1949
2012-12-10 1950 /*
2012-12-10 1951 * Architected system registers.
2012-12-10 1952 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
2014-04-24 1953 *
2014-04-24 1954 * Debug handling: We do trap most, if not all debug related system
2014-04-24 1955 * registers. The implementation is good enough to ensure that a guest
2014-04-24 1956 * can use these with minimal performance degradation. The drawback is
2022-02-03 1957 * that we don't implement any of the external debug architecture.
2022-02-03 1958 * This should be revisited if we ever encounter a more demanding
2022-02-03 1959 * guest...
2012-12-10 1960 */
2012-12-10 1961 static const struct sys_reg_desc sys_reg_descs[] = {
2017-01-13 1962 { SYS_DESC(SYS_DC_ISW), access_dcsw },
2023-05-15 1963 { SYS_DESC(SYS_DC_IGSW), access_dcgsw },
2023-05-15 1964 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw },
2017-01-13 1965 { SYS_DESC(SYS_DC_CSW), access_dcsw },
2023-05-15 1966 { SYS_DESC(SYS_DC_CGSW), access_dcgsw },
2023-05-15 1967 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw },
2017-01-13 1968 { SYS_DESC(SYS_DC_CISW), access_dcsw },
2023-05-15 1969 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw },
2023-05-15 1970 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw },
2012-12-10 1971
2014-04-24 1972 DBG_BCR_BVR_WCR_WVR_EL1(0),
2014-04-24 1973 DBG_BCR_BVR_WCR_WVR_EL1(1),
2017-01-13 1974 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
2017-01-13 1975 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
2014-04-24 1976 DBG_BCR_BVR_WCR_WVR_EL1(2),
2014-04-24 1977 DBG_BCR_BVR_WCR_WVR_EL1(3),
2014-04-24 1978 DBG_BCR_BVR_WCR_WVR_EL1(4),
2014-04-24 1979 DBG_BCR_BVR_WCR_WVR_EL1(5),
2014-04-24 1980 DBG_BCR_BVR_WCR_WVR_EL1(6),
2014-04-24 1981 DBG_BCR_BVR_WCR_WVR_EL1(7),
2014-04-24 1982 DBG_BCR_BVR_WCR_WVR_EL1(8),
2014-04-24 1983 DBG_BCR_BVR_WCR_WVR_EL1(9),
2014-04-24 1984 DBG_BCR_BVR_WCR_WVR_EL1(10),
2014-04-24 1985 DBG_BCR_BVR_WCR_WVR_EL1(11),
2014-04-24 1986 DBG_BCR_BVR_WCR_WVR_EL1(12),
2014-04-24 1987 DBG_BCR_BVR_WCR_WVR_EL1(13),
2014-04-24 1988 DBG_BCR_BVR_WCR_WVR_EL1(14),
2014-04-24 1989 DBG_BCR_BVR_WCR_WVR_EL1(15),
2014-04-24 1990
2017-01-13 1991 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
2022-02-03 1992 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 },
2022-02-03 1993 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
2023-05-23 1994 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, },
2017-01-13 1995 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
2017-01-13 1996 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
2017-01-13 1997 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
2017-01-13 1998 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
2017-01-13 1999 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
2017-01-13 2000
2017-01-13 2001 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
2017-01-13 2002 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
2017-01-13 2003 // DBGDTR[TR]X_EL0 share the same encoding
2017-01-13 2004 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
2017-01-13 2005
2017-01-13 2006 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
2013-02-07 2007
2017-01-19 2008 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
2017-10-31 2009
2017-10-31 2010 /*
2017-10-31 2011 * ID regs: all ID_SANITISED() entries here must have corresponding
2017-10-31 2012 * entries in arm64_ftr_regs[].
2017-10-31 2013 */
2017-10-31 2014
2017-10-31 2015 /* AArch64 mappings of the AArch32 ID registers */
2017-10-31 2016 /* CRm=1 */
2022-09-13 2017 AA32_ID_SANITISED(ID_PFR0_EL1),
2022-09-13 2018 AA32_ID_SANITISED(ID_PFR1_EL1),
2023-06-09 2019 { SYS_DESC(SYS_ID_DFR0_EL1),
2023-06-09 2020 .access = access_id_reg,
2023-06-09 2021 .get_user = get_id_reg,
2023-06-09 2022 .set_user = set_id_dfr0_el1,
2023-06-09 2023 .visibility = aa32_id_visibility,
2023-06-09 2024 .reset = read_sanitised_id_dfr0_el1,
2023-10-03 2025 .val = ID_DFR0_EL1_PerfMon_MASK |
2023-10-03 2026 ID_DFR0_EL1_CopDbg_MASK, },
2017-10-31 2027 ID_HIDDEN(ID_AFR0_EL1),
2022-09-13 2028 AA32_ID_SANITISED(ID_MMFR0_EL1),
2022-09-13 2029 AA32_ID_SANITISED(ID_MMFR1_EL1),
2022-09-13 2030 AA32_ID_SANITISED(ID_MMFR2_EL1),
2022-09-13 2031 AA32_ID_SANITISED(ID_MMFR3_EL1),
2017-10-31 2032
2017-10-31 2033 /* CRm=2 */
2022-09-13 2034 AA32_ID_SANITISED(ID_ISAR0_EL1),
2022-09-13 2035 AA32_ID_SANITISED(ID_ISAR1_EL1),
2022-09-13 2036 AA32_ID_SANITISED(ID_ISAR2_EL1),
2022-09-13 2037 AA32_ID_SANITISED(ID_ISAR3_EL1),
2022-09-13 2038 AA32_ID_SANITISED(ID_ISAR4_EL1),
2022-09-13 2039 AA32_ID_SANITISED(ID_ISAR5_EL1),
2022-09-13 2040 AA32_ID_SANITISED(ID_MMFR4_EL1),
2022-09-13 2041 AA32_ID_SANITISED(ID_ISAR6_EL1),
2017-10-31 2042
2017-10-31 2043 /* CRm=3 */
2022-09-13 2044 AA32_ID_SANITISED(MVFR0_EL1),
2022-09-13 2045 AA32_ID_SANITISED(MVFR1_EL1),
2022-09-13 2046 AA32_ID_SANITISED(MVFR2_EL1),
2017-10-31 2047 ID_UNALLOCATED(3,3),
2022-09-13 2048 AA32_ID_SANITISED(ID_PFR2_EL1),
Khandual 2020-05-19 2049 ID_HIDDEN(ID_DFR1_EL1),
2022-09-13 2050 AA32_ID_SANITISED(ID_MMFR5_EL1),
2017-10-31 2051 ID_UNALLOCATED(3,7),
2017-10-31 2052
2017-10-31 2053 /* AArch64 ID registers */
2017-10-31 2054 /* CRm=4 */
2023-06-09 2055 { SYS_DESC(SYS_ID_AA64PFR0_EL1),
2023-06-09 2056 .access = access_id_reg,
2023-06-09 2057 .get_user = get_id_reg,
2023-06-09 2058 .set_user = set_id_reg,
2023-06-09 2059 .reset = read_sanitised_id_aa64pfr0_el1,
2023-06-09 2060 .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, },
2017-10-31 2061 ID_SANITISED(ID_AA64PFR1_EL1),
2017-10-31 2062 ID_UNALLOCATED(4,2),
2017-10-31 2063 ID_UNALLOCATED(4,3),
2020-11-05 2064 ID_SANITISED(ID_AA64ZFR0_EL1),
2022-04-19 2065 ID_HIDDEN(ID_AA64SMFR0_EL1),
2017-10-31 2066 ID_UNALLOCATED(4,6),
2017-10-31 2067 ID_UNALLOCATED(4,7),
2017-10-31 2068
2017-10-31 2069 /* CRm=5 */
2023-06-09 2070 { SYS_DESC(SYS_ID_AA64DFR0_EL1),
2023-06-09 2071 .access = access_id_reg,
2023-06-09 2072 .get_user = get_id_reg,
2023-06-09 2073 .set_user = set_id_aa64dfr0_el1,
2023-06-09 2074 .reset = read_sanitised_id_aa64dfr0_el1,
2023-10-03 2075 .val = ID_AA64DFR0_EL1_PMUVer_MASK |
2023-10-03 2076 ID_AA64DFR0_EL1_DebugVer_MASK, },
2017-10-31 2077 ID_SANITISED(ID_AA64DFR1_EL1),
2017-10-31 2078 ID_UNALLOCATED(5,2),
2017-10-31 2079 ID_UNALLOCATED(5,3),
2017-10-31 2080 ID_HIDDEN(ID_AA64AFR0_EL1),
2017-10-31 2081 ID_HIDDEN(ID_AA64AFR1_EL1),
2017-10-31 2082 ID_UNALLOCATED(5,6),
2017-10-31 2083 ID_UNALLOCATED(5,7),
2017-10-31 2084
2017-10-31 2085 /* CRm=6 */
2023-10-03 2086 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0),
2023-10-03 2087 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI |
2023-10-03 2088 ID_AA64ISAR1_EL1_GPA |
2023-10-03 2089 ID_AA64ISAR1_EL1_API |
2023-10-03 2090 ID_AA64ISAR1_EL1_APA)),
2023-10-03 2091 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 |
2023-10-03 2092 ID_AA64ISAR2_EL1_MOPS |
2023-10-03 2093 ID_AA64ISAR2_EL1_APA3 |
2023-10-03 2094 ID_AA64ISAR2_EL1_GPA3)),
2017-10-31 2095 ID_UNALLOCATED(6,3),
2017-10-31 2096 ID_UNALLOCATED(6,4),
2017-10-31 2097 ID_UNALLOCATED(6,5),
2017-10-31 2098 ID_UNALLOCATED(6,6),
2017-10-31 2099 ID_UNALLOCATED(6,7),
2017-10-31 2100
2017-10-31 2101 /* CRm=7 */
2023-10-03 2102 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 |
2023-10-03 2103 ID_AA64MMFR0_EL1_TGRAN4_2 |
2023-10-03 2104 ID_AA64MMFR0_EL1_TGRAN64_2 |
2023-10-03 2105 ID_AA64MMFR0_EL1_TGRAN16_2)),
2023-10-03 2106 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 |
2023-10-03 2107 ID_AA64MMFR1_EL1_HCX |
2023-10-03 @2108 ID_AA64MMFR1_EL1_XNX |
2023-10-03 2109 ID_AA64MMFR1_EL1_TWED |
2023-10-03 2110 ID_AA64MMFR1_EL1_XNX |
2023-10-03 2111 ID_AA64MMFR1_EL1_VH |
2023-10-03 2112 ID_AA64MMFR1_EL1_VMIDBits)),
2023-10-03 2113 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 |
2023-10-03 2114 ID_AA64MMFR2_EL1_EVT |
2023-10-03 2115 ID_AA64MMFR2_EL1_FWB |
2023-10-03 2116 ID_AA64MMFR2_EL1_IDS |
2023-10-03 2117 ID_AA64MMFR2_EL1_NV |
2023-10-03 2118 ID_AA64MMFR2_EL1_CCIDX)),
2023-06-06 2119 ID_SANITISED(ID_AA64MMFR3_EL1),
2017-10-31 2120 ID_UNALLOCATED(7,4),
2017-10-31 2121 ID_UNALLOCATED(7,5),
2017-10-31 2122 ID_UNALLOCATED(7,6),
2017-10-31 2123 ID_UNALLOCATED(7,7),
2017-10-31 2124
2017-01-19 2125 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
2020-06-22 2126 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
2017-01-19 2127 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
2020-08-26 2128
2021-06-21 2129 MTE_REG(RGSR_EL1),
2021-06-21 2130 MTE_REG(GCR_EL1),
2020-08-26 2131
2018-09-28 2132 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
2021-04-05 2133 { SYS_DESC(SYS_TRFCR_EL1), undef_access },
2022-04-19 2134 { SYS_DESC(SYS_SMPRI_EL1), undef_access },
2022-04-19 2135 { SYS_DESC(SYS_SMCR_EL1), undef_access },
2017-01-19 2136 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
2017-01-19 2137 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
2017-01-19 2138 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
2023-06-06 2139 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 },
2017-01-19 2140
2019-04-23 2141 PTRAUTH_KEY(APIA),
2019-04-23 2142 PTRAUTH_KEY(APIB),
2019-04-23 2143 PTRAUTH_KEY(APDA),
2019-04-23 2144 PTRAUTH_KEY(APDB),
2019-04-23 2145 PTRAUTH_KEY(APGA),
2019-04-23 2146
2023-02-09 2147 { SYS_DESC(SYS_SPSR_EL1), access_spsr},
2023-02-09 2148 { SYS_DESC(SYS_ELR_EL1), access_elr},
2023-02-09 2149
2017-01-19 2150 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
2017-01-19 2151 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
2017-01-19 2152 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
2018-01-15 2153
2018-01-15 2154 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
2018-01-15 2155 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
2018-01-15 2156 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
2018-01-15 2157 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
2018-01-15 2158 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
2018-01-15 2159 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
2018-01-15 2160 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
2018-01-15 2161 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
2018-01-15 2162
2021-06-21 2163 MTE_REG(TFSR_EL1),
2021-06-21 2164 MTE_REG(TFSRE0_EL1),
2020-08-26 2165
2017-01-19 2166 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
2017-01-19 2167 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
2012-12-10 2168
2021-04-09 2169 { SYS_DESC(SYS_PMSCR_EL1), undef_access },
2021-04-09 2170 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
2021-04-09 2171 { SYS_DESC(SYS_PMSICR_EL1), undef_access },
2021-04-09 2172 { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
2021-04-09 2173 { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
2021-04-09 2174 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
2021-04-09 2175 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
2021-04-09 2176 { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
2021-04-09 2177 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
2021-04-09 2178 { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
2021-04-09 2179 { SYS_DESC(SYS_PMBSR_EL1), undef_access },
2021-04-09 2180 /* PMBIDR_EL1 is not trapped */
2021-04-09 2181
2023-07-14 2182 { PMU_SYS_REG(PMINTENSET_EL1),
2021-01-06 2183 .access = access_pminten, .reg = PMINTENSET_EL1 },
2023-07-14 2184 { PMU_SYS_REG(PMINTENCLR_EL1),
2021-01-06 2185 .access = access_pminten, .reg = PMINTENSET_EL1 },
2020-02-16 2186 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
2012-12-10 2187
2017-01-19 2188 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
2023-06-06 2189 { SYS_DESC(SYS_PIRE0_EL1), access_vm_reg, reset_unknown, PIRE0_EL1 },
2023-06-06 2190 { SYS_DESC(SYS_PIR_EL1), access_vm_reg, reset_unknown, PIR_EL1 },
2017-01-19 2191 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
2012-12-10 2192
2018-11-05 2193 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
2018-11-05 2194 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
2018-11-05 2195 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
2018-11-05 2196 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
2018-11-05 2197 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
2018-02-13 2198
2023-02-09 2199 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },
2018-01-15 2200 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
2014-11-19 2201
2017-06-09 2202 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
2017-06-09 2203 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
2017-06-09 2204 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
2017-06-09 2205 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
2017-06-09 2206 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
2017-01-20 2207 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
2018-08-06 2208 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
2018-08-06 2209 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
2017-06-09 2210 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
2017-06-09 2211 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
2017-06-09 2212 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
2017-01-20 2213 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
2014-11-19 2214
2017-01-19 2215 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
2017-01-19 2216 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
2012-12-10 2217
2023-08-15 2218 { SYS_DESC(SYS_ACCDATA_EL1), undef_access },
2023-08-15 2219
2020-11-10 2220 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
2020-11-10 2221
2017-01-19 2222 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
2012-12-10 2223
2019-01-31 2224 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
2023-01-12 2225 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1,
2023-01-12 2226 .set_user = set_clidr },
2023-01-12 2227 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access },
2022-04-19 2228 { SYS_DESC(SYS_SMIDR_EL1), undef_access },
2019-01-31 2229 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
2019-01-31 2230 { SYS_DESC(SYS_CTR_EL0), access_ctr },
2022-05-10 2231 { SYS_DESC(SYS_SVCR), undef_access },
2012-12-10 2232
2023-07-14 2233 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr,
2021-01-06 2234 .reset = reset_pmcr, .reg = PMCR_EL0 },
2023-07-14 2235 { PMU_SYS_REG(PMCNTENSET_EL0),
2021-01-06 2236 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
2023-07-14 2237 { PMU_SYS_REG(PMCNTENCLR_EL0),
2021-01-06 2238 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
2023-07-14 2239 { PMU_SYS_REG(PMOVSCLR_EL0),
2021-01-06 2240 .access = access_pmovs, .reg = PMOVSSET_EL0 },
2021-07-19 2241 /*
2021-07-19 2242 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
2021-07-19 2243 * previously (and pointlessly) advertised in the past...
2021-07-19 2244 */
2023-07-14 2245 { PMU_SYS_REG(PMSWINC_EL0),
2021-10-11 2246 .get_user = get_raz_reg, .set_user = set_wi_reg,
2021-07-19 2247 .access = access_pmswinc, .reset = NULL },
2023-07-14 2248 { PMU_SYS_REG(PMSELR_EL0),
2021-07-19 2249 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
2023-07-14 2250 { PMU_SYS_REG(PMCEID0_EL0),
2021-01-06 2251 .access = access_pmceid, .reset = NULL },
2023-07-14 2252 { PMU_SYS_REG(PMCEID1_EL0),
2021-01-06 2253 .access = access_pmceid, .reset = NULL },
2023-07-14 2254 { PMU_SYS_REG(PMCCNTR_EL0),
2023-03-12 2255 .access = access_pmu_evcntr, .reset = reset_unknown,
2023-03-12 2256 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr},
2023-07-14 2257 { PMU_SYS_REG(PMXEVTYPER_EL0),
2021-01-06 2258 .access = access_pmu_evtyper, .reset = NULL },
2023-07-14 2259 { PMU_SYS_REG(PMXEVCNTR_EL0),
2021-01-06 2260 .access = access_pmu_evcntr, .reset = NULL },
2017-01-20 2261 /*
2017-01-20 2262 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
2015-09-08 2263 * in 32bit mode. Here we choose to reset it as zero for consistency.
2015-09-08 2264 */
2023-07-14 2265 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr,
2021-01-06 2266 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
2023-07-14 2267 { PMU_SYS_REG(PMOVSSET_EL0),
2021-01-06 2268 .access = access_pmovs, .reg = PMOVSSET_EL0 },
2012-12-10 2269
2017-01-19 2270 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
2017-01-19 2271 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
2022-04-19 2272 { SYS_DESC(SYS_TPIDR2_EL0), undef_access },
2020-03-05 2273
2020-11-10 2274 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
2020-11-10 2275
2020-11-10 2276 { SYS_DESC(SYS_AMCR_EL0), undef_access },
2020-11-10 2277 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
2020-11-10 2278 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
2020-11-10 2279 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
2020-11-10 2280 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
2020-11-10 2281 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
2020-11-10 2282 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
2020-11-10 2283 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
2020-03-05 2284 AMU_AMEVCNTR0_EL0(0),
2020-03-05 2285 AMU_AMEVCNTR0_EL0(1),
2020-03-05 2286 AMU_AMEVCNTR0_EL0(2),
2020-03-05 2287 AMU_AMEVCNTR0_EL0(3),
2020-03-05 2288 AMU_AMEVCNTR0_EL0(4),
2020-03-05 2289 AMU_AMEVCNTR0_EL0(5),
2020-03-05 2290 AMU_AMEVCNTR0_EL0(6),
2020-03-05 2291 AMU_AMEVCNTR0_EL0(7),
2020-03-05 2292 AMU_AMEVCNTR0_EL0(8),
2020-03-05 2293 AMU_AMEVCNTR0_EL0(9),
2020-03-05 2294 AMU_AMEVCNTR0_EL0(10),
2020-03-05 2295 AMU_AMEVCNTR0_EL0(11),
2020-03-05 2296 AMU_AMEVCNTR0_EL0(12),
2020-03-05 2297 AMU_AMEVCNTR0_EL0(13),
2020-03-05 2298 AMU_AMEVCNTR0_EL0(14),
2020-03-05 2299 AMU_AMEVCNTR0_EL0(15),
2020-07-21 2300 AMU_AMEVTYPER0_EL0(0),
2020-07-21 2301 AMU_AMEVTYPER0_EL0(1),
2020-07-21 2302 AMU_AMEVTYPER0_EL0(2),
2020-07-21 2303 AMU_AMEVTYPER0_EL0(3),
2020-07-21 2304 AMU_AMEVTYPER0_EL0(4),
2020-07-21 2305 AMU_AMEVTYPER0_EL0(5),
2020-07-21 2306 AMU_AMEVTYPER0_EL0(6),
2020-07-21 2307 AMU_AMEVTYPER0_EL0(7),
2020-07-21 2308 AMU_AMEVTYPER0_EL0(8),
2020-07-21 2309 AMU_AMEVTYPER0_EL0(9),
2020-07-21 2310 AMU_AMEVTYPER0_EL0(10),
2020-07-21 2311 AMU_AMEVTYPER0_EL0(11),
2020-07-21 2312 AMU_AMEVTYPER0_EL0(12),
2020-07-21 2313 AMU_AMEVTYPER0_EL0(13),
2020-07-21 2314 AMU_AMEVTYPER0_EL0(14),
2020-07-21 2315 AMU_AMEVTYPER0_EL0(15),
2020-03-05 2316 AMU_AMEVCNTR1_EL0(0),
2020-03-05 2317 AMU_AMEVCNTR1_EL0(1),
2020-03-05 2318 AMU_AMEVCNTR1_EL0(2),
2020-03-05 2319 AMU_AMEVCNTR1_EL0(3),
2020-03-05 2320 AMU_AMEVCNTR1_EL0(4),
2020-03-05 2321 AMU_AMEVCNTR1_EL0(5),
2020-03-05 2322 AMU_AMEVCNTR1_EL0(6),
2020-03-05 2323 AMU_AMEVCNTR1_EL0(7),
2020-03-05 2324 AMU_AMEVCNTR1_EL0(8),
2020-03-05 2325 AMU_AMEVCNTR1_EL0(9),
2020-03-05 2326 AMU_AMEVCNTR1_EL0(10),
2020-03-05 2327 AMU_AMEVCNTR1_EL0(11),
2020-03-05 2328 AMU_AMEVCNTR1_EL0(12),
2020-03-05 2329 AMU_AMEVCNTR1_EL0(13),
2020-03-05 2330 AMU_AMEVCNTR1_EL0(14),
2020-03-05 2331 AMU_AMEVCNTR1_EL0(15),
2020-07-21 2332 AMU_AMEVTYPER1_EL0(0),
2020-07-21 2333 AMU_AMEVTYPER1_EL0(1),
2020-07-21 2334 AMU_AMEVTYPER1_EL0(2),
2020-07-21 2335 AMU_AMEVTYPER1_EL0(3),
2020-07-21 2336 AMU_AMEVTYPER1_EL0(4),
2020-07-21 2337 AMU_AMEVTYPER1_EL0(5),
2020-07-21 2338 AMU_AMEVTYPER1_EL0(6),
2020-07-21 2339 AMU_AMEVTYPER1_EL0(7),
2020-07-21 2340 AMU_AMEVTYPER1_EL0(8),
2020-07-21 2341 AMU_AMEVTYPER1_EL0(9),
2020-07-21 2342 AMU_AMEVTYPER1_EL0(10),
2020-07-21 2343 AMU_AMEVTYPER1_EL0(11),
2020-07-21 2344 AMU_AMEVTYPER1_EL0(12),
2020-07-21 2345 AMU_AMEVTYPER1_EL0(13),
2020-07-21 2346 AMU_AMEVTYPER1_EL0(14),
2020-07-21 2347 AMU_AMEVTYPER1_EL0(15),
2013-02-07 2348
2023-03-30 2349 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer },
2023-03-30 2350 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer },
2018-07-05 2351 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
2018-07-05 2352 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
2018-07-05 2353 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
2017-02-03 2354
2015-12-08 2355 /* PMEVCNTRn_EL0 */
2015-12-08 2356 PMU_PMEVCNTR_EL0(0),
2015-12-08 2357 PMU_PMEVCNTR_EL0(1),
2015-12-08 2358 PMU_PMEVCNTR_EL0(2),
2015-12-08 2359 PMU_PMEVCNTR_EL0(3),
2015-12-08 2360 PMU_PMEVCNTR_EL0(4),
2015-12-08 2361 PMU_PMEVCNTR_EL0(5),
2015-12-08 2362 PMU_PMEVCNTR_EL0(6),
2015-12-08 2363 PMU_PMEVCNTR_EL0(7),
2015-12-08 2364 PMU_PMEVCNTR_EL0(8),
2015-12-08 2365 PMU_PMEVCNTR_EL0(9),
2015-12-08 2366 PMU_PMEVCNTR_EL0(10),
2015-12-08 2367 PMU_PMEVCNTR_EL0(11),
2015-12-08 2368 PMU_PMEVCNTR_EL0(12),
2015-12-08 2369 PMU_PMEVCNTR_EL0(13),
2015-12-08 2370 PMU_PMEVCNTR_EL0(14),
2015-12-08 2371 PMU_PMEVCNTR_EL0(15),
2015-12-08 2372 PMU_PMEVCNTR_EL0(16),
2015-12-08 2373 PMU_PMEVCNTR_EL0(17),
2015-12-08 2374 PMU_PMEVCNTR_EL0(18),
2015-12-08 2375 PMU_PMEVCNTR_EL0(19),
2015-12-08 2376 PMU_PMEVCNTR_EL0(20),
2015-12-08 2377 PMU_PMEVCNTR_EL0(21),
2015-12-08 2378 PMU_PMEVCNTR_EL0(22),
2015-12-08 2379 PMU_PMEVCNTR_EL0(23),
2015-12-08 2380 PMU_PMEVCNTR_EL0(24),
2015-12-08 2381 PMU_PMEVCNTR_EL0(25),
2015-12-08 2382 PMU_PMEVCNTR_EL0(26),
2015-12-08 2383 PMU_PMEVCNTR_EL0(27),
2015-12-08 2384 PMU_PMEVCNTR_EL0(28),
2015-12-08 2385 PMU_PMEVCNTR_EL0(29),
2015-12-08 2386 PMU_PMEVCNTR_EL0(30),
2016-02-23 2387 /* PMEVTYPERn_EL0 */
2016-02-23 2388 PMU_PMEVTYPER_EL0(0),
2016-02-23 2389 PMU_PMEVTYPER_EL0(1),
2016-02-23 2390 PMU_PMEVTYPER_EL0(2),
2016-02-23 2391 PMU_PMEVTYPER_EL0(3),
2016-02-23 2392 PMU_PMEVTYPER_EL0(4),
2016-02-23 2393 PMU_PMEVTYPER_EL0(5),
2016-02-23 2394 PMU_PMEVTYPER_EL0(6),
2016-02-23 2395 PMU_PMEVTYPER_EL0(7),
2016-02-23 2396 PMU_PMEVTYPER_EL0(8),
2016-02-23 2397 PMU_PMEVTYPER_EL0(9),
2016-02-23 2398 PMU_PMEVTYPER_EL0(10),
2016-02-23 2399 PMU_PMEVTYPER_EL0(11),
2016-02-23 2400 PMU_PMEVTYPER_EL0(12),
2016-02-23 2401 PMU_PMEVTYPER_EL0(13),
2016-02-23 2402 PMU_PMEVTYPER_EL0(14),
2016-02-23 2403 PMU_PMEVTYPER_EL0(15),
2016-02-23 2404 PMU_PMEVTYPER_EL0(16),
2016-02-23 2405 PMU_PMEVTYPER_EL0(17),
2016-02-23 2406 PMU_PMEVTYPER_EL0(18),
2016-02-23 2407 PMU_PMEVTYPER_EL0(19),
2016-02-23 2408 PMU_PMEVTYPER_EL0(20),
2016-02-23 2409 PMU_PMEVTYPER_EL0(21),
2016-02-23 2410 PMU_PMEVTYPER_EL0(22),
2016-02-23 2411 PMU_PMEVTYPER_EL0(23),
2016-02-23 2412 PMU_PMEVTYPER_EL0(24),
2016-02-23 2413 PMU_PMEVTYPER_EL0(25),
2016-02-23 2414 PMU_PMEVTYPER_EL0(26),
2016-02-23 2415 PMU_PMEVTYPER_EL0(27),
2016-02-23 2416 PMU_PMEVTYPER_EL0(28),
2016-02-23 2417 PMU_PMEVTYPER_EL0(29),
2016-02-23 2418 PMU_PMEVTYPER_EL0(30),
2017-01-20 2419 /*
2017-01-20 2420 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
2016-02-23 2421 * in 32bit mode. Here we choose to reset it as zero for consistency.
2016-02-23 2422 */
2023-07-14 2423 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper,
2021-01-06 2424 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
2015-12-08 2425
2023-02-09 2426 EL2_REG(VPIDR_EL2, access_rw, reset_unknown, 0),
2023-02-09 2427 EL2_REG(VMPIDR_EL2, access_rw, reset_unknown, 0),
2023-02-09 2428 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),
2023-02-09 2429 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),
2023-02-09 2430 EL2_REG(HCR_EL2, access_rw, reset_val, 0),
2023-02-09 2431 EL2_REG(MDCR_EL2, access_rw, reset_val, 0),
2023-06-09 2432 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),
2023-02-09 2433 EL2_REG(HSTR_EL2, access_rw, reset_val, 0),
2023-08-15 2434 EL2_REG(HFGRTR_EL2, access_rw, reset_val, 0),
2023-08-15 2435 EL2_REG(HFGWTR_EL2, access_rw, reset_val, 0),
2023-08-15 2436 EL2_REG(HFGITR_EL2, access_rw, reset_val, 0),
2023-02-09 2437 EL2_REG(HACR_EL2, access_rw, reset_val, 0),
2023-02-09 2438
2023-08-15 2439 EL2_REG(HCRX_EL2, access_rw, reset_val, 0),
2023-08-15 2440
2023-02-09 2441 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
2023-02-09 2442 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
2023-02-09 2443 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
2023-02-09 2444 EL2_REG(VTTBR_EL2, access_rw, reset_val, 0),
2023-02-09 2445 EL2_REG(VTCR_EL2, access_rw, reset_val, 0),
2023-02-09 2446
2017-01-19 2447 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
2023-08-15 2448 EL2_REG(HDFGRTR_EL2, access_rw, reset_val, 0),
2023-08-15 2449 EL2_REG(HDFGWTR_EL2, access_rw, reset_val, 0),
2023-02-09 2450 EL2_REG(SPSR_EL2, access_rw, reset_val, 0),
2023-02-09 2451 EL2_REG(ELR_EL2, access_rw, reset_val, 0),
2023-02-09 2452 { SYS_DESC(SYS_SP_EL1), access_sp_el1},
2023-02-09 2453
2017-01-19 2454 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
2023-02-09 2455 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),
2023-02-09 2456 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),
2023-02-09 2457 EL2_REG(ESR_EL2, access_rw, reset_val, 0),
2019-02-21 2458 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
2023-02-09 2459
2023-02-09 2460 EL2_REG(FAR_EL2, access_rw, reset_val, 0),
2023-02-09 2461 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
2023-02-09 2462
2023-02-09 2463 EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
2023-02-09 2464 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
2023-02-09 2465
2023-02-09 2466 EL2_REG(VBAR_EL2, access_rw, reset_val, 0),
2023-02-09 2467 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0),
2023-02-09 2468 { SYS_DESC(SYS_RMR_EL2), trap_undef },
2023-02-09 2469
2023-02-09 2470 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0),
2023-02-09 2471 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0),
2023-02-09 2472
2023-02-09 2473 EL2_REG(CNTVOFF_EL2, access_rw, reset_val, 0),
2023-02-09 2474 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0),
2023-02-09 2475
2023-02-09 2476 EL12_REG(SCTLR, access_vm_reg, reset_val, 0x00C50078),
2023-02-09 2477 EL12_REG(CPACR, access_rw, reset_val, 0),
2023-02-09 2478 EL12_REG(TTBR0, access_vm_reg, reset_unknown, 0),
2023-02-09 2479 EL12_REG(TTBR1, access_vm_reg, reset_unknown, 0),
2023-02-09 2480 EL12_REG(TCR, access_vm_reg, reset_val, 0),
2023-02-09 2481 { SYS_DESC(SYS_SPSR_EL12), access_spsr},
2023-02-09 2482 { SYS_DESC(SYS_ELR_EL12), access_elr},
2023-02-09 2483 EL12_REG(AFSR0, access_vm_reg, reset_unknown, 0),
2023-02-09 2484 EL12_REG(AFSR1, access_vm_reg, reset_unknown, 0),
2023-02-09 2485 EL12_REG(ESR, access_vm_reg, reset_unknown, 0),
2023-02-09 2486 EL12_REG(FAR, access_vm_reg, reset_unknown, 0),
2023-02-09 2487 EL12_REG(MAIR, access_vm_reg, reset_unknown, 0),
2023-02-09 2488 EL12_REG(AMAIR, access_vm_reg, reset_amair_el1, 0),
2023-02-09 2489 EL12_REG(VBAR, access_rw, reset_val, 0),
2023-02-09 2490 EL12_REG(CONTEXTIDR, access_vm_reg, reset_val, 0),
2023-02-09 2491 EL12_REG(CNTKCTL, access_rw, reset_val, 0),
2023-02-09 2492
2023-02-09 2493 EL2_REG(SP_EL2, NULL, reset_unknown, 0),
2013-02-07 2494 };
2013-02-07 2495
m/intel/lkp-tests/wiki">https://github.com/intel/lkp-tests/wiki