2021-06-18 12:45:01

by Odelu Kukatla

Subject: [V4 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
SoCs.

Signed-off-by: Odelu Kukatla <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 38a7f55..7690d7e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1153,6 +1153,15 @@
};
};

+ epss_l3: interconnect@18590000 {
+ compatible = "qcom,sc7280-epss-l3";
+ reg = <0 0x18590000 0 1000>, <0 0x18591000 0 0x100>,
+ <0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
clk_virt: interconnect {
compatible = "qcom,sc7280-clk-virt";
#interconnect-cells = <2>;
--
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2021-07-08 23:06:37

by Stephen Boyd

Subject: Re: [V4 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

Quoting Odelu Kukatla (2021-06-18 04:28:54)
> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
> SoCs.
>
> Signed-off-by: Odelu Kukatla <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 38a7f55..7690d7e 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1153,6 +1153,15 @@
> };
> };
>
> + epss_l3: interconnect@18590000 {
> + compatible = "qcom,sc7280-epss-l3";
> + reg = <0 0x18590000 0 1000>, <0 0x18591000 0 0x100>,
> + <0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> + clock-names = "xo", "alternate";
> + #interconnect-cells = <1>;
> + };

Is this inside the soc node? Because it should be but then the next node
is called 'interconnect' and has no address so that is probably outside
the soc node. Please put nodes with a reg property like this into the
soc node.

> +
> clk_virt: interconnect {
> compatible = "qcom,sc7280-clk-virt";
> #interconnect-cells = <2>;

2021-08-09 20:16:19

by Odelu Kukatla

Subject: Re: [V4 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

On 2021-07-09 04:34, Stephen Boyd wrote:
> Quoting Odelu Kukatla (2021-06-18 04:28:54)
>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
>> SoCs.
>>
>> Signed-off-by: Odelu Kukatla <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 38a7f55..7690d7e 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -1153,6 +1153,15 @@
>> };
>> };
>>
>> + epss_l3: interconnect@18590000 {
>> + compatible = "qcom,sc7280-epss-l3";
>> + reg = <0 0x18590000 0 1000>, <0 0x18591000 0
>> 0x100>,
>> + <0 0x18592000 0 0x100>, <0 0x18593000
>> 0 0x100>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc
>> GCC_GPLL0>;
>> + clock-names = "xo", "alternate";
>> + #interconnect-cells = <1>;
>> + };
>
> Is this inside the soc node? Because it should be but then the next
> node
> is called 'interconnect' and has no address so that is probably outside
> the soc node. Please put nodes with a reg property like this into the
> soc node.
>
no, will move this into soc node in v5.
>> +
>> clk_virt: interconnect {
>> compatible = "qcom,sc7280-clk-virt";
>> #interconnect-cells = <2>;