2022-11-01 06:41:48

by Gaosheng Cui

Subject: [PATCH] x86/cpu: replacing the open-coded shift with BIT(x)

Replace the open-coded shift with BIT(x) for x86_power to make the
code a bit more self-documenting, and we will get a UBSAN issue in
arch/x86/kernel/cpu/proc.c, fix it.

The UBSAN warning calltrace like below:

UBSAN: shift-out-of-bounds in arch/x86/kernel/cpu/proc.c:138:25
left shift of 1 by 31 places cannot be represented in type 'int'
Call Trace:
<TASK>
dump_stack_lvl+0x7d/0xa5
dump_stack+0x15/0x1b
ubsan_epilogue+0xe/0x4e
__ubsan_handle_shift_out_of_bounds+0x1e7/0x20c
show_cpuinfo+0x5ff/0x6d0
seq_read_iter+0x116/0x5b0
proc_reg_read_iter+0x45/0xc0
vfs_read+0x2ee/0x3c0
ksys_read+0xe1/0x130
__x64_sys_read+0x23/0x30
do_syscall_64+0x58/0x80
entry_SYSCALL_64_after_hwframe+0x63/0xcd
</TASK>

Signed-off-by: Gaosheng Cui <[email protected]>
---
arch/x86/kernel/cpu/amd.c | 2 +-
arch/x86/kernel/cpu/centaur.c | 2 +-
arch/x86/kernel/cpu/hygon.c | 2 +-
arch/x86/kernel/cpu/intel.c | 2 +-
arch/x86/kernel/cpu/proc.c | 2 +-
arch/x86/kernel/cpu/zhaoxin.c | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 860b60273df3..75d82cad323a 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -613,7 +613,7 @@ static void early_init_amd(struct cpuinfo_x86 *c)
* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
* with P/T states and does not stop in deep C-states
*/
- if (c->x86_power & (1 << 8)) {
+ if (c->x86_power & BIT(8)) {
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
}
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 345f7d905db6..9910bb1d90fd 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -105,7 +105,7 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
#ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_SYSENTER32);
#endif
- if (c->x86_power & (1 << 8)) {
+ if (c->x86_power & BIT(8)) {
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
}
diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c
index 21fd425088fe..dc473bfbf1b5 100644
--- a/arch/x86/kernel/cpu/hygon.c
+++ b/arch/x86/kernel/cpu/hygon.c
@@ -251,7 +251,7 @@ static void early_init_hygon(struct cpuinfo_x86 *c)
* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
* with P/T states and does not stop in deep C-states
*/
- if (c->x86_power & (1 << 8)) {
+ if (c->x86_power & BIT(8)) {
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
}
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 121c1c38162a..bbe86a2f3a43 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -286,7 +286,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
* It is also reliable across cores and sockets. (but not across
* cabinets - we turn it off in that case explicitly.)
*/
- if (c->x86_power & (1 << 8)) {
+ if (c->x86_power & BIT(8)) {
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
}
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 099b6f0d96bd..efa1d39c4f25 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -135,7 +135,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)

seq_puts(m, "power management:");
for (i = 0; i < 32; i++) {
- if (c->x86_power & (1 << i)) {
+ if (c->x86_power & BIT(i)) {
if (i < ARRAY_SIZE(x86_power_flags) &&
x86_power_flags[i])
seq_printf(m, "%s%s",
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index 05fa4ef63490..34a8a460f8f4 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -61,7 +61,7 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c)
#ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_SYSENTER32);
#endif
- if (c->x86_power & (1 << 8)) {
+ if (c->x86_power & BIT(8)) {
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
}
--
2.25.1

2022-11-01 09:30:24

by Peter Zijlstra

Subject: Re: [PATCH] x86/cpu: replacing the open-coded shift with BIT(x)

On Tue, Nov 01, 2022 at 02:09:45PM +0800, Gaosheng Cui wrote:
> Replace the open-coded shift with BIT(x) for x86_power to make the
> code a bit more self-documenting, and we will get a UBSAN issue in
> arch/x86/kernel/cpu/proc.c, fix it.
>
> The UBSAN warning calltrace like below:
>
> UBSAN: shift-out-of-bounds in arch/x86/kernel/cpu/proc.c:138:25
> left shift of 1 by 31 places cannot be represented in type 'int'

Same as to the other case; UBSAN is broken garbage, stop quoting it.

2022-11-01 11:49:49

by Gaosheng Cui

Subject: Re: [PATCH] x86/cpu: replacing the open-coded shift with BIT(x)

> Same as to the other case; UBSAN is broken garbage, stop quoting it.

I have made patch v2 and submitted it, removed the UBSAN warning calltrace,
and merged the patch "x86/cpu: fix undefined behavior in bit shift for intel_detect_tlb"
with it. Thanks!

On 2022/11/1 16:48, Peter Zijlstra wrote:
> On Tue, Nov 01, 2022 at 02:09:45PM +0800, Gaosheng Cui wrote:
>> Replace the open-coded shift with BIT(x) for x86_power to make the
>> code a bit more self-documenting, and we will get a UBSAN issue in
>> arch/x86/kernel/cpu/proc.c, fix it.
>>
>> The UBSAN warning calltrace like below:
>>
>> UBSAN: shift-out-of-bounds in arch/x86/kernel/cpu/proc.c:138:25
>> left shift of 1 by 31 places cannot be represented in type 'int'
> Same as to the other case; UBSAN is broken garbage, stop quoting it.
>
> .