There is a new product which reuses Lantiq serial controller IP. Patch 1 in this
series converts existing lantiq dt bindings to YAML schema and Patch 2 updates
it to support newer product.
These patches are baselined upon Linux 5.3-rc4 at below Git tree:
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git
v2:
* Update license to GPL-2.0-only.
* Fix trailing whitespace error.
Rahul Tanwar (2):
dt-bindings: serial: lantiq: Convert to YAML schema
dt-bindings: lantiq: Update for new SoC
.../devicetree/bindings/serial/lantiq_asc.txt | 31 --------
.../devicetree/bindings/serial/lantiq_asc.yaml | 87 ++++++++++++++++++++++
2 files changed, 87 insertions(+), 31 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/serial/lantiq_asc.txt
create mode 100644 Documentation/devicetree/bindings/serial/lantiq_asc.yaml
--
2.11.0
Convert the existing DT binding document for Lantiq SoC ASC serial controller
from txt format to YAML format.
Signed-off-by: Rahul Tanwar <[email protected]>
---
.../devicetree/bindings/serial/lantiq_asc.txt | 31 ----------
.../devicetree/bindings/serial/lantiq_asc.yaml | 70 ++++++++++++++++++++++
2 files changed, 70 insertions(+), 31 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/serial/lantiq_asc.txt
create mode 100644 Documentation/devicetree/bindings/serial/lantiq_asc.yaml
diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.txt b/Documentation/devicetree/bindings/serial/lantiq_asc.txt
deleted file mode 100644
index 40e81a5818f6..000000000000
--- a/Documentation/devicetree/bindings/serial/lantiq_asc.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-Lantiq SoC ASC serial controller
-
-Required properties:
-- compatible : Should be "lantiq,asc"
-- reg : Address and length of the register set for the device
-- interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier
- depends on the interrupt-parent interrupt controller.
-
-Optional properties:
-- clocks: Should contain frequency clock and gate clock
-- clock-names: Should be "freq" and "asc"
-
-Example:
-
-asc0: serial@16600000 {
- compatible = "lantiq,asc";
- reg = <0x16600000 0x100000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>;
- clock-names = "freq", "asc";
-};
-
-asc1: serial@e100c00 {
- compatible = "lantiq,asc";
- reg = <0xE100C00 0x400>;
- interrupt-parent = <&icu0>;
- interrupts = <112 113 114>;
-};
diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
new file mode 100644
index 000000000000..54b90490f4fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/lantiq_asc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq SoC ASC serial controller
+
+maintainers:
+ - Rahul Tanwar <[email protected]>
+
+allOf:
+ - $ref: /schemas/serial.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ items:
+ - const: lantiq,asc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 3
+ items:
+ - description: tx or combined interrupt
+ - description: rx interrupt
+ - description: err interrupt
+
+ clocks:
+ description:
+ When present, first entry listed should contain phandle
+ to the frequency clock and second entry should contain
+ phandle to the gate clock.
+
+ clock-names:
+ items:
+ - const: freq
+ - const: asc
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+
+examples:
+ - |
+ asc0: serial@16600000 {
+ compatible = "lantiq,asc";
+ reg = <0x16600000 0x100000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>;
+ clock-names = "freq", "asc";
+ };
+
+ - |
+ asc1: serial@e100c00 {
+ compatible = "lantiq,asc";
+ reg = <0xE100C00 0x400>;
+ interrupt-parent = <&icu0>;
+ interrupts = <112 113 114>;
+ };
+
+...
--
2.11.0
Intel Lightning Mountain(LGM) SoC reuses Lantiq ASC serial controller IP.
Update the dt bindings to support LGM as well.
Signed-off-by: Rahul Tanwar <[email protected]>
---
.../devicetree/bindings/serial/lantiq_asc.yaml | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
index 54b90490f4fb..92807b59b024 100644
--- a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
+++ b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
@@ -17,6 +17,7 @@ properties:
oneOf:
items:
- const: lantiq,asc
+ - const: intel,lgm-asc
reg:
maxItems: 1
@@ -28,6 +29,12 @@ properties:
- description: tx or combined interrupt
- description: rx interrupt
- description: err interrupt
+ description:
+ For lantiq,asc compatible, it supports 3 separate
+ interrupts for tx rx & err. Whereas, for intel,lgm-asc
+ compatible, it supports combined single interrupt for
+ all of tx, rx & err interrupts.
+
clocks:
description:
@@ -67,4 +74,14 @@ examples:
interrupts = <112 113 114>;
};
+ - |
+ asc0: serial@e0a00000 {
+ compatible = "intel,lgm-asc";
+ reg = <0xe0a00000 0x1000>;
+ interrupt-parent = <&ioapic1>;
+ interrupts = <128 1>;
+ clocks = <&cgu0 LGM_CLK_NOC4>, <&cgu0 LGM_GCLK_ASC0>;
+ clock-names = "freq", "asc";
+ };
+
...
--
2.11.0
On Tue, Aug 20, 2019 at 3:29 AM Rahul Tanwar
<[email protected]> wrote:
>
> Intel Lightning Mountain(LGM) SoC reuses Lantiq ASC serial controller IP.
> Update the dt bindings to support LGM as well.
>
> Signed-off-by: Rahul Tanwar <[email protected]>
> ---
> .../devicetree/bindings/serial/lantiq_asc.yaml | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
> index 54b90490f4fb..92807b59b024 100644
> --- a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
> +++ b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
> @@ -17,6 +17,7 @@ properties:
> oneOf:
> items:
> - const: lantiq,asc
> + - const: intel,lgm-asc
Better expressed as:
compatible:
enum:
- intel,lgm-asc
- lantiq,asc
>
> reg:
> maxItems: 1
> @@ -28,6 +29,12 @@ properties:
> - description: tx or combined interrupt
> - description: rx interrupt
> - description: err interrupt
> + description:
> + For lantiq,asc compatible, it supports 3 separate
> + interrupts for tx rx & err. Whereas, for intel,lgm-asc
> + compatible, it supports combined single interrupt for
> + all of tx, rx & err interrupts.
This can be expressed with an if/then schema. There's some examples in
the tree how to do that.
> +
>
> clocks:
> description:
> @@ -67,4 +74,14 @@ examples:
> interrupts = <112 113 114>;
> };
>
> + - |
> + asc0: serial@e0a00000 {
> + compatible = "intel,lgm-asc";
> + reg = <0xe0a00000 0x1000>;
> + interrupt-parent = <&ioapic1>;
> + interrupts = <128 1>;
> + clocks = <&cgu0 LGM_CLK_NOC4>, <&cgu0 LGM_GCLK_ASC0>;
> + clock-names = "freq", "asc";
> + };
> +
> ...
> --
> 2.11.0
>
On Tue, Aug 20, 2019 at 3:29 AM Rahul Tanwar
<[email protected]> wrote:
>
> Convert the existing DT binding document for Lantiq SoC ASC serial controller
> from txt format to YAML format.
>
> Signed-off-by: Rahul Tanwar <[email protected]>
> ---
> .../devicetree/bindings/serial/lantiq_asc.txt | 31 ----------
> .../devicetree/bindings/serial/lantiq_asc.yaml | 70 ++++++++++++++++++++++
Use the compatible name: lantiq,asc.yaml
Don't forget the $id value too.
> 2 files changed, 70 insertions(+), 31 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/serial/lantiq_asc.txt
> create mode 100644 Documentation/devicetree/bindings/serial/lantiq_asc.yaml
> diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
> new file mode 100644
> index 000000000000..54b90490f4fb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/serial/lantiq_asc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Lantiq SoC ASC serial controller
> +
> +maintainers:
> + - Rahul Tanwar <[email protected]>
> +
> +allOf:
> + - $ref: /schemas/serial.yaml#
> +
> +properties:
> + compatible:
> + oneOf:
> + items:
> + - const: lantiq,asc
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + minItems: 1
Technically, 1 item is not allowed until patch 2 (or the old doc was wrong).
> + maxItems: 3
> + items:
> + - description: tx or combined interrupt
> + - description: rx interrupt
> + - description: err interrupt
> +
> + clocks:
> + description:
> + When present, first entry listed should contain phandle
> + to the frequency clock and second entry should contain
> + phandle to the gate clock.
Schema needs to define how many entries:
items:
- description: ...
- description: ...
> +
> + clock-names:
> + items:
> + - const: freq
> + - const: asc
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +
> +examples:
> + - |
> + asc0: serial@16600000 {
> + compatible = "lantiq,asc";
> + reg = <0x16600000 0x100000>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>;
> + clock-names = "freq", "asc";
> + };
> +
> + - |
> + asc1: serial@e100c00 {
I don't think this 2nd example adds anything.
> + compatible = "lantiq,asc";
> + reg = <0xE100C00 0x400>;
> + interrupt-parent = <&icu0>;
> + interrupts = <112 113 114>;
> + };
> +
> +...
> --
> 2.11.0
>