From: Frieder Schrempf <[email protected]>
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8MM including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
Currently there are two SoM models:
* SL i.MX8MM N8010 with 1GB RAM and 8 GB eMMC
* SL i.MX8MM N8011 with 2GB RAM and 8 GB eMMC
The matching baseboard has the same form factor and similar interfaces
as the other boards from the Kontron "Board-Line" family, including
SD card, 1G Ethernet, 100M Ethernet, USB Host/OTG, digital IOs, RS232,
RS485, CAN, LVDS or HDMI, RTC and much more.
This adds the basic support for the SoMs and boards. Some things to note:
* The SoMs use the PCA9450 PMIC. The driver support is pending: [1].
* Two other patches for the external SPI's spidev compatible and the SPI
NOR support are pending: [2][3].
* The graphics and display peripherals (DSI, LVDS, HDMI, GPU, etc.) are not
supported upstream yet.
* There seems to be an unresolved issue with the upstream SPI driver for
i.MX8MM which breaks SPI devices: [4].
[1] https://patchwork.kernel.org/cover/11557753/
[2] https://patchwork.kernel.org/patch/11639027/
[3] https://patchwork.ozlabs.org/project/linux-mtd/patch/[email protected]/
[4] https://patchwork.kernel.org/patch/11037107/#23227681.
Frieder Schrempf (2):
arm64: dts: Add the Kontron i.MX8M-Mini SoMs and baseboards
dt-bindings: arm: fsl: Add Kontron i.MX8MM SoMs and boards
.../devicetree/bindings/arm/fsl.yaml | 14 +
.../dts/freescale/imx8mm-kontron-n8010-s.dts | 15 +
.../freescale/imx8mm-kontron-n8010-som.dtsi | 16 +
.../dts/freescale/imx8mm-kontron-n8011-s.dts | 15 +
.../freescale/imx8mm-kontron-n8011-som.dtsi | 16 +
.../dts/freescale/imx8mm-kontron-n801x-s.dtsi | 326 ++++++++++++++++++
.../freescale/imx8mm-kontron-n801x-som.dtsi | 281 +++++++++++++++
7 files changed, 683 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-s.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-som.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-s.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-som.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
--
2.17.1
From: Frieder Schrempf <[email protected]>
Kontron Electronics GmbH offers small and powerful SoMs based on the
i.MX8MM including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
The matching baseboards have the same form factor and similar interfaces
as the other boards from the Kontron "Board-Line" family, including
SD card, 1G Ethernet, 100M Ethernet, USB Host/OTG, digital IOs, RS232,
RS485, CAN, LVDS or HDMI, RTC and much more.
Signed-off-by: Frieder Schrempf <[email protected]>
---
.../dts/freescale/imx8mm-kontron-n8010-s.dts | 15 +
.../freescale/imx8mm-kontron-n8010-som.dtsi | 16 +
.../dts/freescale/imx8mm-kontron-n8011-s.dts | 15 +
.../freescale/imx8mm-kontron-n8011-som.dtsi | 16 +
.../dts/freescale/imx8mm-kontron-n801x-s.dtsi | 326 ++++++++++++++++++
.../freescale/imx8mm-kontron-n801x-som.dtsi | 281 +++++++++++++++
6 files changed, 669 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-s.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-som.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-s.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-som.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-s.dts
new file mode 100644
index 000000000000..0911f2d0555b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-s.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx8mm-kontron-n8010-som.dtsi"
+#include "imx8mm-kontron-n801x-s.dtsi"
+
+/ {
+ model = "Kontron i.MX8MM N8010 S";
+ compatible = "kontron,imx8mm-n8010-s", "kontron,imx8mm-n8010-som",
+ "fsl,imx8mm";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-som.dtsi
new file mode 100644
index 000000000000..5b178ce4ce1b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-som.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include "imx8mm-kontron-n801x-som.dtsi"
+
+/ {
+ model = "Kontron i.MX8MM N8010 SoM";
+ compatible = "kontron,imx8mm-n8010-som", "fsl,imx8mm";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-s.dts
new file mode 100644
index 000000000000..5c44bd77ed32
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-s.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+/dts-v1/;
+
+#include "imx8mm-kontron-n8011-som.dtsi"
+#include "imx8mm-kontron-n801x-s.dtsi"
+
+/ {
+ model = "Kontron i.MX8MM N8011 S";
+ compatible = "kontron,imx8mm-n8011-s", "kontron,imx8mm-n8011-som",
+ "fsl,imx8mm";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-som.dtsi
new file mode 100644
index 000000000000..303594867b8f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-som.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include "imx8mm-kontron-n801x-som.dtsi"
+
+/ {
+ model = "Kontron i.MX8MM N8011 SoM";
+ compatible = "kontron,imx8mm-n8011-som", "fsl,imx8mm";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0xC0000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dtsi
new file mode 100644
index 000000000000..d825e52e0beb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dtsi
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+/ {
+ aliases {
+ ethernet1 = &usbnet;
+ };
+
+ /* fixed crystal dedicated to mcp2515 */
+ clk16m: clk16m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_led>;
+
+ led1 {
+ label = "led1";
+ gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led2 {
+ label = "led2";
+ gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ };
+
+ led3 {
+ label = "led3";
+ gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
+ };
+
+ led4 {
+ label = "led4";
+ gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
+ };
+
+ led5 {
+ label = "led5";
+ gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ };
+
+ led6 {
+ label = "led6";
+ gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ pwm-beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm2 0 5000 0>;
+ };
+
+ reg_rst_eth2: regulator-rst-eth2 {
+ compatible = "regulator-fixed";
+ regulator-name = "rst-usb-eth2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_eth2>;
+ gpio = <&gpio3 2 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ };
+
+ vdd_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ status = "okay";
+ };
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ can0: can@0 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can>;
+ clocks = <&clk16m>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <100000>;
+ vdd-supply = <&vdd_3v3>;
+ xceiver-supply = <&vdd_5v>;
+ status = "okay";
+ };
+};
+
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3>;
+ cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ userspi: userspi@0 {
+ compatible = "kontron,user-spi";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+ status = "okay";
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <100>;
+ phy-reset-post-delay = <100>;
+ phy-handle = <ðphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ usb1@1 {
+ compatible = "usb424,9514";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbnet: usbether@1 {
+ compatible = "usb424,ec00";
+ reg = <1>;
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ vmmc-supply = <&vdd_3v3>;
+ vqmmc-supply = <&nvcc_sd>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio>;
+
+ pinctrl_can: cangrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
+ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
+ >;
+ };
+
+ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82
+ MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82
+ MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82
+ MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */
+ MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */
+ >;
+ };
+
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19
+ MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19
+ MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19
+ MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19
+ >;
+ };
+
+ pinctrl_gpio: gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
+ MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
+ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
+ MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
+ MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
+ MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
+ MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
+ >;
+ };
+
+ pinctrl_usb_eth2: usbeth2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
+ >;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
new file mode 100644
index 000000000000..207be37522e5
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Kontron Electronics GmbH
+ */
+
+#include "imx8mm.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart3;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&A53_1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&A53_2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&A53_3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ spi-flash@0 {
+ compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
+ spi-max-frequency = <80000000>;
+ reg = <0>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic: pca9450@25 {
+ compatible = "nxp,pca9450a";
+ reg = <0x25>;
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <0 GPIO_ACTIVE_LOW>;
+
+ regulators {
+ vdd_soc: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ vdd_arm: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <950000>;
+ regulator-boot-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ vdd_dram: BUCK3 {
+ regulator-name = "BUCK3";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_3v3: BUCK4 {
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_1v8: BUCK5 {
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ nvcc_dram: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ nvcc_snvs: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_snvs: LDO2 {
+ regulator-compatible = "ldo2";
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdda: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd_phy: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ nvcc_sd: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+};
+
+&uart3 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ vmmc-supply = <&vdd_3v3>;
+ vqmmc-supply = <&vdd_1v8>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x41
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
+ MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
+ MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
+ MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
+ MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
+ MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
+ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
--
2.17.1
From: Frieder Schrempf <[email protected]>
Add entries for the SoMs and boards based on i.MX8MM from Kontron
Electronics GmbH.
Signed-off-by: Frieder Schrempf <[email protected]>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 05906e291e38..a99b1c3320b7 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -337,6 +337,20 @@ properties:
items:
- enum:
- fsl,imx8mm-evk # i.MX8MM EVK Board
+ - kontron,imx8mm-n8010-som # Kontron N8010 SOM
+ - kontron,imx8mm-n8011-som # Kontron N8011 SOM
+ - const: fsl,imx8mm
+
+ - description: Kontron N8010 S Board
+ items:
+ - const: kontron,imx8mm-n8010-s
+ - const: kontron,imx8mm-n8010-som
+ - const: fsl,imx8mm
+
+ - description: Kontron N8011 S Board
+ items:
+ - const: kontron,imx8mm-n8011-s
+ - const: kontron,imx8mm-n8011-som
- const: fsl,imx8mm
- description: i.MX8MN based Boards
--
2.17.1
Hi Frieder
Nice to see some more i.MX 8M Mini action. Much appreciated!
On Thu, 2020-07-02 at 16:33 +0200, Schrempf Frieder wrote:
> From: Frieder Schrempf <[email protected]>
>
> Kontron Electronics GmbH offers small and powerful SoMs based on the
> i.MX8MM
To avoid much confusion in NXP's nomenclature I would recommend writing this always as i.MX 8M Mini. Of course,
in code, using imx8mm is fine.
> including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
>
> The matching baseboards have the same form factor and similar interfaces
> as the other boards from the Kontron "Board-Line" family, including
> SD card, 1G Ethernet, 100M Ethernet, USB Host/OTG, digital IOs, RS232,
> RS485, CAN, LVDS or HDMI, RTC and much more.
>
> Signed-off-by: Frieder Schrempf <[email protected]>
> ---
> .../dts/freescale/imx8mm-kontron-n8010-s.dts | 15 +
> .../freescale/imx8mm-kontron-n8010-som.dtsi | 16 +
> .../dts/freescale/imx8mm-kontron-n8011-s.dts | 15 +
> .../freescale/imx8mm-kontron-n8011-som.dtsi | 16 +
> .../dts/freescale/imx8mm-kontron-n801x-s.dtsi | 326 ++++++++++++++++++
> .../freescale/imx8mm-kontron-n801x-som.dtsi | 281 +++++++++++++++
> 6 files changed, 669 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-s.dts
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-som.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-s.dts
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-som.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-
> kontron-n8010-s.dts
> new file mode 100644
> index 000000000000..0911f2d0555b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-s.dts
> @@ -0,0 +1,15 @@
> +// SPDX-License-Identifier: GPL-2.0
Don't you want to use the more common GPL-2.0+ OR MIT variant which allows for more freedom? At least NXP's
imx8mm.dtsi also uses that.
> +/*
> + * Copyright (C) 2019 Kontron Electronics GmbH
I know that there is much about 2020 to rather be ignored.
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8mm-kontron-n8010-som.dtsi"
> +#include "imx8mm-kontron-n801x-s.dtsi"
> +
> +/ {
> + model = "Kontron i.MX8MM N8010 S";
> + compatible = "kontron,imx8mm-n8010-s", "kontron,imx8mm-n8010-som",
> + "fsl,imx8mm";
I believe now with Linux having dropped the strict 80-column line length coding style limit we are allowed to
go up to 100 (;-p).
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-som.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-som.dtsi
> new file mode 100644
> index 000000000000..5b178ce4ce1b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-som.dtsi
> @@ -0,0 +1,16 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 Kontron Electronics GmbH
> + */
> +
> +#include "imx8mm-kontron-n801x-som.dtsi"
> +
> +/ {
> + model = "Kontron i.MX8MM N8010 SoM";
> + compatible = "kontron,imx8mm-n8010-som", "fsl,imx8mm";
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0 0x80000000>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-
> kontron-n8011-s.dts
> new file mode 100644
> index 000000000000..5c44bd77ed32
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-s.dts
> @@ -0,0 +1,15 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 Kontron Electronics GmbH
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8mm-kontron-n8011-som.dtsi"
> +#include "imx8mm-kontron-n801x-s.dtsi"
> +
> +/ {
> + model = "Kontron i.MX8MM N8011 S";
> + compatible = "kontron,imx8mm-n8011-s", "kontron,imx8mm-n8011-som",
> + "fsl,imx8mm";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-som.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-som.dtsi
> new file mode 100644
> index 000000000000..303594867b8f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-som.dtsi
> @@ -0,0 +1,16 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 Kontron Electronics GmbH
> + */
> +
> +#include "imx8mm-kontron-n801x-som.dtsi"
> +
> +/ {
> + model = "Kontron i.MX8MM N8011 SoM";
> + compatible = "kontron,imx8mm-n8011-som", "fsl,imx8mm";
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0 0xC0000000>;
> + };
Isn't the boot loader supposed to filling that in?
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dtsi
> new file mode 100644
> index 000000000000..d825e52e0beb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dtsi
> @@ -0,0 +1,326 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 Kontron Electronics GmbH
> + */
> +
> +/ {
> + aliases {
> + ethernet1 = &usbnet;
> + };
> +
> + /* fixed crystal dedicated to mcp2515 */
> + clk16m: clk16m {
I believe a more human readable variant e.g. as follows is preferred:
osc_16m: clock-osc-16m
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <16000000>;
Also the use of the optional property clock-output-names is recommended.
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_led>;
> +
> + led1 {
> + label = "led1";
> + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
> + linux,default-trigger = "heartbeat";
> + };
> +
> + led2 {
> + label = "led2";
> + gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
> + };
> +
> + led3 {
> + label = "led3";
> + gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
> + };
> +
> + led4 {
> + label = "led4";
> + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
> + };
> +
> + led5 {
> + label = "led5";
> + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
> + };
> +
> + led6 {
> + label = "led6";
> + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + pwm-beeper {
> + compatible = "pwm-beeper";
> + pwms = <&pwm2 0 5000 0>;
> + };
> +
> + reg_rst_eth2: regulator-rst-eth2 {
> + compatible = "regulator-fixed";
> + regulator-name = "rst-usb-eth2";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb_eth2>;
> + gpio = <&gpio3 2 GPIO_ACTIVE_LOW>;
> + status = "okay";
> + };
> +
> + vdd_5v: regulator-5v {
I would stick to consistent reg_ pre-fixing.
> + compatible = "regulator-fixed";
> + regulator-name = "vdd_5v";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + status = "okay";
> + };
> +};
> +
> +&ecspi2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi2>;
> + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +
> + can0: can@0 {
> + compatible = "microchip,mcp2515";
> + reg = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_can>;
> + clocks = <&clk16m>;
> + interrupt-parent = <&gpio4>;
> + interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
> + spi-max-frequency = <100000>;
> + vdd-supply = <&vdd_3v3>;
> + xceiver-supply = <&vdd_5v>;
> + status = "okay";
I find the property ordering a little confusing but that might just be me.
> + };
> +};
> +
> +&ecspi3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi3>;
> + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +
> + userspi: userspi@0 {
> + compatible = "kontron,user-spi";
> + reg = <0>;
> + spi-max-frequency = <100000000>;
> + status = "okay";
> + };
I thought from earlier discussions you intended to drop that and either specify it from user-space directly or
use an overlay instead.
> +};
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + phy-mode = "rgmii";
> + phy-reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
> + phy-reset-duration = <100>;
> + phy-reset-post-delay = <100>;
> + phy-handle = <ðphy>;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy: ethernet-phy@0 {
> + reg = <0>;
> + };
> + };
> +};
> +
> +&i2c4 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c4>;
> + status = "okay";
> +
> + rtc@32 {
> + compatible = "epson,rx8900";
> + reg = <0x32>;
> + };
> +};
> +
> +&pwm2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm2>;
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + linux,rs485-enabled-at-boot-time;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&usbotg1 {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usbotg2 {
> + dr_mode = "host";
> + disable-over-current;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + usb1@1 {
> + compatible = "usb424,9514";
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + usbnet: usbether@1 {
> + compatible = "usb424,ec00";
> + reg = <1>;
> + mac-address = [ 00 00 00 00 00 00 ];
> + };
> + };
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + vmmc-supply = <&vdd_3v3>;
> + vqmmc-supply = <&nvcc_sd>;
> + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
> + bus-width = <4>;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio>;
> +
> + pinctrl_can: cangrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
> + >;
> + };
> +
> + pinctrl_ecspi2: ecspi2grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
> + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
> + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
> + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
> + >;
> + };
> +
> + pinctrl_ecspi3: ecspi3grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82
> + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82
> + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82
> + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19
> + >;
> + };
> +
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */
> + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */
> + >;
> + };
> +
> + pinctrl_gpio_led: gpioledgrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
> + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19
> + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19
> + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19
> + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19
> + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19
> + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19
> + >;
> + };
> +
> + pinctrl_gpio: gpiogrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
> + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
> + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
> + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
> + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
> + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
> + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
> + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
> + >;
> + };
> +
> + pinctrl_i2c4: i2c4grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
> + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
> + >;
> + };
> +
> + pinctrl_pwm2: pwm2grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
> + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
> + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
> + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
> + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
> + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
> + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
> + >;
> + };
> +
> + pinctrl_usb_eth2: usbeth2grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
> + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
> + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
> + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
> + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
> + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
> + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
> + >;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
> new file mode 100644
> index 000000000000..207be37522e5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
> @@ -0,0 +1,281 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2019 Kontron Electronics GmbH
> + */
> +
> +#include "imx8mm.dtsi"
> +
> +/ {
> + chosen {
> + stdout-path = &uart3;
> + };
> +};
> +
> +&A53_0 {
> + cpu-supply = <&vdd_arm>;
> +};
> +
> +&A53_1 {
> + cpu-supply = <&vdd_arm>;
> +};
> +
> +&A53_2 {
> + cpu-supply = <&vdd_arm>;
> +};
> +
> +&A53_3 {
> + cpu-supply = <&vdd_arm>;
> +};
> +
> +&ddrc {
> + operating-points-v2 = <&ddrc_opp_table>;
> +
> + ddrc_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-25M {
> + opp-hz = /bits/ 64 <25000000>;
> + };
> +
> + opp-100M {
> + opp-hz = /bits/ 64 <100000000>;
> + };
> +
> + opp-750M {
> + opp-hz = /bits/ 64 <750000000>;
> + };
> + };
> +};
> +
> +&ecspi1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +
> + spi-flash@0 {
> + compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
> + spi-max-frequency = <80000000>;
> + reg = <0>;
> + };
> +};
> +
> +&i2c1 {
> + clock-frequency = <400000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + pmic: pca9450@25 {
> + compatible = "nxp,pca9450a";
> + reg = <0x25>;
> + pinctrl-0 = <&pinctrl_pmic>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <0 GPIO_ACTIVE_LOW>;
> +
> + regulators {
> + vdd_soc: BUCK1 {
> + regulator-name = "BUCK1";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <900000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <3125>;
> + };
> +
> + vdd_arm: BUCK2 {
> + regulator-name = "BUCK2";
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <950000>;
> + regulator-boot-on;
> + regulator-ramp-delay = <3125>;
> + nxp,dvs-run-voltage = <950000>;
> + nxp,dvs-standby-voltage = <850000>;
> + };
> +
> + vdd_dram: BUCK3 {
> + regulator-name = "BUCK3";
> + regulator-min-microvolt = <850000>;
> + regulator-max-microvolt = <900000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vdd_3v3: BUCK4 {
> + regulator-name = "BUCK4";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vdd_1v8: BUCK5 {
> + regulator-name = "BUCK5";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + nvcc_dram: BUCK6 {
> + regulator-name = "BUCK6";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + nvcc_snvs: LDO1 {
> + regulator-name = "LDO1";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vdd_snvs: LDO2 {
> + regulator-compatible = "ldo2";
> + regulator-name = "LDO2";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vdda: LDO3 {
> + regulator-name = "LDO3";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vdd_phy: LDO4 {
> + regulator-name = "LDO4";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + nvcc_sd: LDO5 {
> + regulator-name = "LDO5";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> + };
> + };
> +};
> +
> +&uart3 { /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + status = "okay";
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> + vmmc-supply = <&vdd_3v3>;
> + vqmmc-supply = <&vdd_1v8>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl_ecspi1: ecspi1grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
> + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
> + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
> + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
> + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
> + >;
> + };
> +
> + pinctrl_pmic: pmicgrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x41
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
> + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
> + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
> + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
> + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
> + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
> + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
> + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
> + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
> + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
> + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
> + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
> + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
> + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
> + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
> + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
> + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
> + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
> + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
> + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
> + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
> + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
> + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
> + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
> + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
> + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
> + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
> + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
> + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
> + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
> + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
> + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
> + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
> + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
> + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> + >;
> + };
> +};
Cheers
Marcel
Hi Marcel,
On 03.07.20 09:56, Marcel Ziswiler wrote:
> Hi Frieder
>
> Nice to see some more i.MX 8M Mini action. Much appreciated!
>
> On Thu, 2020-07-02 at 16:33 +0200, Schrempf Frieder wrote:
>> From: Frieder Schrempf <[email protected]>
>>
>> Kontron Electronics GmbH offers small and powerful SoMs based on the
>> i.MX8MM
>
> To avoid much confusion in NXP's nomenclature I would recommend writing this always as i.MX 8M Mini. Of course,
> in code, using imx8mm is fine.
Ok, sounds reasonable.
>
>> including PMIC, LPDDR4-RAM, eMMC and SPI NOR.
>>
>> The matching baseboards have the same form factor and similar interfaces
>> as the other boards from the Kontron "Board-Line" family, including
>> SD card, 1G Ethernet, 100M Ethernet, USB Host/OTG, digital IOs, RS232,
>> RS485, CAN, LVDS or HDMI, RTC and much more.
>>
>> Signed-off-by: Frieder Schrempf <[email protected]>
>> ---
>> .../dts/freescale/imx8mm-kontron-n8010-s.dts | 15 +
>> .../freescale/imx8mm-kontron-n8010-som.dtsi | 16 +
>> .../dts/freescale/imx8mm-kontron-n8011-s.dts | 15 +
>> .../freescale/imx8mm-kontron-n8011-som.dtsi | 16 +
>> .../dts/freescale/imx8mm-kontron-n801x-s.dtsi | 326 ++++++++++++++++++
>> .../freescale/imx8mm-kontron-n801x-som.dtsi | 281 +++++++++++++++
>> 6 files changed, 669 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-s.dts
>> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-som.dtsi
>> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-s.dts
>> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-som.dtsi
>> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dtsi
>> create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-
>> kontron-n8010-s.dts
>> new file mode 100644
>> index 000000000000..0911f2d0555b
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-s.dts
>> @@ -0,0 +1,15 @@
>> +// SPDX-License-Identifier: GPL-2.0
>
> Don't you want to use the more common GPL-2.0+ OR MIT variant which allows for more freedom? At least NXP's
> imx8mm.dtsi also uses that.
That actually sounds like a good idea. I will change that.
>
>> +/*
>> + * Copyright (C) 2019 Kontron Electronics GmbH
>
> I know that there is much about 2020 to rather be ignored.
Indeed, but I also once learned that you don't change the original date
in a copyright notice as it is used to express when the content has been
published or created first (and the original version has been online on
our server publically since 2019).
>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "imx8mm-kontron-n8010-som.dtsi"
>> +#include "imx8mm-kontron-n801x-s.dtsi"
>> +
>> +/ {
>> + model = "Kontron i.MX8MM N8010 S";
>> + compatible = "kontron,imx8mm-n8010-s", "kontron,imx8mm-n8010-som",
>> + "fsl,imx8mm";
>
> I believe now with Linux having dropped the strict 80-column line length coding style limit we are allowed to
> go up to 100 (;-p).
Right, I remember seeing some discussion about extending the column
limit. I will need to update my text editor's config.
>
>> +};
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-som.dtsi
>> b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-som.dtsi
>> new file mode 100644
>> index 000000000000..5b178ce4ce1b
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8010-som.dtsi
>> @@ -0,0 +1,16 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2019 Kontron Electronics GmbH
>> + */
>> +
>> +#include "imx8mm-kontron-n801x-som.dtsi"
>> +
>> +/ {
>> + model = "Kontron i.MX8MM N8010 SoM";
>> + compatible = "kontron,imx8mm-n8010-som", "fsl,imx8mm";
>> +
>> + memory@40000000 {
>> + device_type = "memory";
>> + reg = <0x0 0x40000000 0 0x80000000>;
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-
>> kontron-n8011-s.dts
>> new file mode 100644
>> index 000000000000..5c44bd77ed32
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-s.dts
>> @@ -0,0 +1,15 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2019 Kontron Electronics GmbH
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "imx8mm-kontron-n8011-som.dtsi"
>> +#include "imx8mm-kontron-n801x-s.dtsi"
>> +
>> +/ {
>> + model = "Kontron i.MX8MM N8011 S";
>> + compatible = "kontron,imx8mm-n8011-s", "kontron,imx8mm-n8011-som",
>> + "fsl,imx8mm";
>> +};
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-som.dtsi
>> b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-som.dtsi
>> new file mode 100644
>> index 000000000000..303594867b8f
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n8011-som.dtsi
>> @@ -0,0 +1,16 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2019 Kontron Electronics GmbH
>> + */
>> +
>> +#include "imx8mm-kontron-n801x-som.dtsi"
>> +
>> +/ {
>> + model = "Kontron i.MX8MM N8011 SoM";
>> + compatible = "kontron,imx8mm-n8011-som", "fsl,imx8mm";
>> +
>> + memory@40000000 {
>> + device_type = "memory";
>> + reg = <0x0 0x40000000 0 0xC0000000>;
>> + };
>
> Isn't the boot loader supposed to filling that in?
Hm, probably yes. I thought it would be good to have the upstream DT
fully describe the modules, including the memory size. But if it is more
common or useful, I will fill in the memory size for the smallest
configuration (1GB) only and let U-Boot overwrite the value if it
detects modules with larger DDR.
>
>> +};
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dtsi
>> b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dtsi
>> new file mode 100644
>> index 000000000000..d825e52e0beb
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dtsi
>> @@ -0,0 +1,326 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2019 Kontron Electronics GmbH
>> + */
>> +
>> +/ {
>> + aliases {
>> + ethernet1 = &usbnet;
>> + };
>> +
>> + /* fixed crystal dedicated to mcp2515 */
>> + clk16m: clk16m {
>
> I believe a more human readable variant e.g. as follows is preferred:
>
> osc_16m: clock-osc-16m
Ok.
>
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <16000000>;
>
> Also the use of the optional property clock-output-names is recommended.
Ok.
>
>> + };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_gpio_led>;
>> +
>> + led1 {
>> + label = "led1";
>> + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
>> + linux,default-trigger = "heartbeat";
>> + };
>> +
>> + led2 {
>> + label = "led2";
>> + gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
>> + };
>> +
>> + led3 {
>> + label = "led3";
>> + gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
>> + };
>> +
>> + led4 {
>> + label = "led4";
>> + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
>> + };
>> +
>> + led5 {
>> + label = "led5";
>> + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
>> + };
>> +
>> + led6 {
>> + label = "led6";
>> + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
>> + };
>> + };
>> +
>> + pwm-beeper {
>> + compatible = "pwm-beeper";
>> + pwms = <&pwm2 0 5000 0>;
>> + };
>> +
>> + reg_rst_eth2: regulator-rst-eth2 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "rst-usb-eth2";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usb_eth2>;
>> + gpio = <&gpio3 2 GPIO_ACTIVE_LOW>;
>> + status = "okay";
>> + };
>> +
>> + vdd_5v: regulator-5v {
>
> I would stick to consistent reg_ pre-fixing.
Ok.
>
>> + compatible = "regulator-fixed";
>> + regulator-name = "vdd_5v";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + status = "okay";
>> + };
>> +};
>> +
>> +&ecspi2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_ecspi2>;
>> + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
>> + status = "okay";
>> +
>> + can0: can@0 {
>> + compatible = "microchip,mcp2515";
>> + reg = <0>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_can>;
>> + clocks = <&clk16m>;
>> + interrupt-parent = <&gpio4>;
>> + interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
>> + spi-max-frequency = <100000>;
>> + vdd-supply = <&vdd_3v3>;
>> + xceiver-supply = <&vdd_5v>;
>> + status = "okay";
>
> I find the property ordering a little confusing but that might just be me.
I think it's "compatible", "reg" and "pinctrl" first, then the other
properties in alphabetical order and "status" last. So I'm not really
sure what to improve here.
>
>> + };
>> +};
>> +
>> +&ecspi3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_ecspi3>;
>> + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
>> + status = "okay";
>> +
>> + userspi: userspi@0 {
>> + compatible = "kontron,user-spi";
>> + reg = <0>;
>> + spi-max-frequency = <100000000>;
>> + status = "okay";
>> + };
>
> I thought from earlier discussions you intended to drop that and either specify it from user-space directly or
> use an overlay instead.
Yes, indeed, but when I learned about the possibility to override the
device's driver from userspace, I already had sent out this patch. I
will remove the userspi node in the next version.
Thanks so far for reviewing!
Frieder
On Thu, 02 Jul 2020 16:33:07 +0200, Schrempf Frieder wrote:
> From: Frieder Schrempf <[email protected]>
>
> Add entries for the SoMs and boards based on i.MX8MM from Kontron
> Electronics GmbH.
>
> Signed-off-by: Frieder Schrempf <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
Reviewed-by: Rob Herring <[email protected]>