2023-06-02 17:07:37

by Colton Lewis

Subject: [PATCH 1/3] arm64: Add a capability for FEAT_BBM level 2

From: Ricardo Koller <[email protected]>

Add a new capability to detect "Stage-2 Translation table
break-before-make" (FEAT_BBM) level 2.

Signed-off-by: Ricardo Koller <[email protected]>
---
arch/arm64/kernel/cpufeature.c | 11 +++++++++++
arch/arm64/tools/cpucaps | 1 +
2 files changed, 12 insertions(+)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index c331c49a7d19c..c538060f7f66b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2455,6 +2455,17 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.min_field_value = 1,
.matches = has_cpuid_feature,
},
+ {
+ .desc = "Stage-2 Translation table break-before-make level 2",
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+ .capability = ARM64_HAS_STAGE2_BBM2,
+ .sys_reg = SYS_ID_AA64MMFR2_EL1,
+ .sign = FTR_UNSIGNED,
+ .field_pos = ID_AA64MMFR2_EL1_BBM_SHIFT,
+ .field_width = 4,
+ .min_field_value = 2,
+ .matches = has_cpuid_feature,
+ },
{
.desc = "TLB range maintenance instructions",
.capability = ARM64_HAS_TLB_RANGE,
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 40ba95472594d..010aca1892642 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -41,6 +41,7 @@ HAS_PAN
HAS_RAS_EXTN
HAS_RNG
HAS_SB
+HAS_STAGE2_BBM2
HAS_STAGE2_FWB
HAS_TIDCP1
HAS_TLB_RANGE
--
2.41.0.rc0.172.g3f132b7071-goog

2023-06-05 15:21:04

by Robin Murphy

Subject: Re: [PATCH 1/3] arm64: Add a capability for FEAT_BBM level 2

On 2023-06-02 18:01, Colton Lewis wrote:
> From: Ricardo Koller <[email protected]>
>
> Add a new capability to detect "Stage-2 Translation table
> break-before-make" (FEAT_BBM) level 2.

Why does this patch invent spurious "stage 2" references everywhere? The
full name of FEAT_BBM is "Translation table break-before-make levels",
and it is not specific to one stage of translation.

Thanks,
Robin.

> Signed-off-by: Ricardo Koller <[email protected]>
> ---
> arch/arm64/kernel/cpufeature.c | 11 +++++++++++
> arch/arm64/tools/cpucaps | 1 +
> 2 files changed, 12 insertions(+)
>
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index c331c49a7d19c..c538060f7f66b 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -2455,6 +2455,17 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
> .min_field_value = 1,
> .matches = has_cpuid_feature,
> },
> + {
> + .desc = "Stage-2 Translation table break-before-make level 2",
> + .type = ARM64_CPUCAP_SYSTEM_FEATURE,
> + .capability = ARM64_HAS_STAGE2_BBM2,
> + .sys_reg = SYS_ID_AA64MMFR2_EL1,
> + .sign = FTR_UNSIGNED,
> + .field_pos = ID_AA64MMFR2_EL1_BBM_SHIFT,
> + .field_width = 4,
> + .min_field_value = 2,
> + .matches = has_cpuid_feature,
> + },
> {
> .desc = "TLB range maintenance instructions",
> .capability = ARM64_HAS_TLB_RANGE,
> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
> index 40ba95472594d..010aca1892642 100644
> --- a/arch/arm64/tools/cpucaps
> +++ b/arch/arm64/tools/cpucaps
> @@ -41,6 +41,7 @@ HAS_PAN
> HAS_RAS_EXTN
> HAS_RNG
> HAS_SB
> +HAS_STAGE2_BBM2
> HAS_STAGE2_FWB
> HAS_TIDCP1
> HAS_TLB_RANGE
> --
> 2.41.0.rc0.172.g3f132b7071-goog
>
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