When the RTC divider is changed from reset to an operating time base,
the first update cycle should be 500ms later. But on some Zhaoxin SOCs,
this first update cycle is one second later.
So set RTC time on these Zhaoxin SOCs will causing 500ms delay.
Skip setup RTC divider on these SOCs in mc146818_set_time to fix it.
Signed-off-by: Tony W Wang-oc <[email protected]>
---
drivers/rtc/rtc-mc146818-lib.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/rtc/rtc-mc146818-lib.c b/drivers/rtc/rtc-mc146818-lib.c
index dcfaf09..322f94b 100644
--- a/drivers/rtc/rtc-mc146818-lib.c
+++ b/drivers/rtc/rtc-mc146818-lib.c
@@ -190,8 +190,18 @@ int mc146818_set_time(struct rtc_time *time)
spin_lock_irqsave(&rtc_lock, flags);
save_control = CMOS_READ(RTC_CONTROL);
CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
+
+#ifdef CONFIG_X86
+ if (!((boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) &&
+ (boot_cpu_data.x86 <= 7 && boot_cpu_data.x86_model <= 59))) {
+ save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
+ CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
+ }
+#else
save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
+#endif
#ifdef CONFIG_MACH_DECSTATION
CMOS_WRITE(real_yrs, RTC_DEC_YEAR);
@@ -209,7 +219,15 @@ int mc146818_set_time(struct rtc_time *time)
#endif
CMOS_WRITE(save_control, RTC_CONTROL);
+
+#ifdef CONFIG_X86
+ if (!((boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) &&
+ (boot_cpu_data.x86 <= 7 && boot_cpu_data.x86_model <= 59)))
+ CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
+#else
CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
+#endif
spin_unlock_irqrestore(&rtc_lock, flags);
--
2.7.4
Hello,
On 16/08/2021 21:47:18+0800, Tony W Wang-oc wrote:
> When the RTC divider is changed from reset to an operating time base,
> the first update cycle should be 500ms later. But on some Zhaoxin SOCs,
> this first update cycle is one second later.
>
> So set RTC time on these Zhaoxin SOCs will causing 500ms delay.
>
Can you explain what is the relationship between writing the divider and
the 500ms delay?
Isn't the issue that you are using systohc and set_offset_nsec is set to
NSEC_PER_SEC / 2 ?
> Skip setup RTC divider on these SOCs in mc146818_set_time to fix it.
>
> Signed-off-by: Tony W Wang-oc <[email protected]>
> ---
> drivers/rtc/rtc-mc146818-lib.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/rtc/rtc-mc146818-lib.c b/drivers/rtc/rtc-mc146818-lib.c
> index dcfaf09..322f94b 100644
> --- a/drivers/rtc/rtc-mc146818-lib.c
> +++ b/drivers/rtc/rtc-mc146818-lib.c
> @@ -190,8 +190,18 @@ int mc146818_set_time(struct rtc_time *time)
> spin_lock_irqsave(&rtc_lock, flags);
> save_control = CMOS_READ(RTC_CONTROL);
> CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
> +
> +#ifdef CONFIG_X86
> + if (!((boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR ||
> + boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) &&
> + (boot_cpu_data.x86 <= 7 && boot_cpu_data.x86_model <= 59))) {
> + save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
> + CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
> + }
> +#else
> save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
> CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
> +#endif
>
> #ifdef CONFIG_MACH_DECSTATION
> CMOS_WRITE(real_yrs, RTC_DEC_YEAR);
> @@ -209,7 +219,15 @@ int mc146818_set_time(struct rtc_time *time)
> #endif
>
> CMOS_WRITE(save_control, RTC_CONTROL);
> +
> +#ifdef CONFIG_X86
> + if (!((boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR ||
> + boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) &&
> + (boot_cpu_data.x86 <= 7 && boot_cpu_data.x86_model <= 59)))
> + CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
> +#else
> CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
> +#endif
>
> spin_unlock_irqrestore(&rtc_lock, flags);
>
> --
> 2.7.4
>
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On 16/08/2021 16:24, Alexandre Belloni wrote:
> Hello,
>
> On 16/08/2021 21:47:18+0800, Tony W Wang-oc wrote:
>> When the RTC divider is changed from reset to an operating time base,
>> the first update cycle should be 500ms later. But on some Zhaoxin SOCs,
>> this first update cycle is one second later.
>>
>> So set RTC time on these Zhaoxin SOCs will causing 500ms delay.
>>
>
> Can you explain what is the relationship between writing the divider and
> the 500ms delay?
>> Isn't the issue that you are using systohc and set_offset_nsec is set to
> NSEC_PER_SEC / 2 ?
>
No.
When using #hwclock -s to set RTC time and set_offset_nsec is
NSEC_PER_SEC / 2, the function mc146818_set_time() requires the first
update cycle after RTC divider be changed from reset to an operating
mode is 500ms as the MC146818A spec specified. But on some Zhaoxin SOCs,
the first update cycle of RTC is one second later after RTC divider be
changed from reset to an operating mode. So the first update cycle after
RTC divider be changed from reset to an operation mode on These SOCs
will causing 500ms delay with current mc146818_set_time() implementation.
Sincerely
TonyWWang-oc
>> Skip setup RTC divider on these SOCs in mc146818_set_time to fix it.
>>
>> Signed-off-by: Tony W Wang-oc <[email protected]>
>> ---
>> drivers/rtc/rtc-mc146818-lib.c | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/drivers/rtc/rtc-mc146818-lib.c b/drivers/rtc/rtc-mc146818-lib.c
>> index dcfaf09..322f94b 100644
>> --- a/drivers/rtc/rtc-mc146818-lib.c
>> +++ b/drivers/rtc/rtc-mc146818-lib.c
>> @@ -190,8 +190,18 @@ int mc146818_set_time(struct rtc_time *time)
>> spin_lock_irqsave(&rtc_lock, flags);
>> save_control = CMOS_READ(RTC_CONTROL);
>> CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
>> +
>> +#ifdef CONFIG_X86
>> + if (!((boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR ||
>> + boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) &&
>> + (boot_cpu_data.x86 <= 7 && boot_cpu_data.x86_model <= 59))) {
>> + save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
>> + CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
>> + }
>> +#else
>> save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
>> CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
>> +#endif
>>
>> #ifdef CONFIG_MACH_DECSTATION
>> CMOS_WRITE(real_yrs, RTC_DEC_YEAR);
>> @@ -209,7 +219,15 @@ int mc146818_set_time(struct rtc_time *time)
>> #endif
>>
>> CMOS_WRITE(save_control, RTC_CONTROL);
>> +
>> +#ifdef CONFIG_X86
>> + if (!((boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR ||
>> + boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) &&
>> + (boot_cpu_data.x86 <= 7 && boot_cpu_data.x86_model <= 59)))
>> + CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
>> +#else
>> CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
>> +#endif
>>
>> spin_unlock_irqrestore(&rtc_lock, flags);
>>
>> --
>> 2.7.4
>>
>
On 16/08/2021 18:03:13+0800, Tony W Wang-oc wrote:
>
> On 16/08/2021 16:24, Alexandre Belloni wrote:
> > Hello,
> >
> > On 16/08/2021 21:47:18+0800, Tony W Wang-oc wrote:
> >> When the RTC divider is changed from reset to an operating time base,
> >> the first update cycle should be 500ms later. But on some Zhaoxin SOCs,
> >> this first update cycle is one second later.
> >>
> >> So set RTC time on these Zhaoxin SOCs will causing 500ms delay.
> >>
> >
> > Can you explain what is the relationship between writing the divider and
> > the 500ms delay?
> >> Isn't the issue that you are using systohc and set_offset_nsec is set to
> > NSEC_PER_SEC / 2 ?
> >
> No.
> When using #hwclock -s to set RTC time and set_offset_nsec is
> NSEC_PER_SEC / 2, the function mc146818_set_time() requires the first
> update cycle after RTC divider be changed from reset to an operating
> mode is 500ms as the MC146818A spec specified. But on some Zhaoxin SOCs,
> the first update cycle of RTC is one second later after RTC divider be
> changed from reset to an operating mode. So the first update cycle after
> RTC divider be changed from reset to an operation mode on These SOCs
> will causing 500ms delay with current mc146818_set_time() implementation.
>
What happens with hwclock --delay=0 -s ?
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On August 16, 2021 8:36:48 PM GMT+08:00, Alexandre Belloni <[email protected]> wrote:
>On 16/08/2021 18:03:13+0800, Tony W Wang-oc wrote:
>>
>> On 16/08/2021 16:24, Alexandre Belloni wrote:
>> > Hello,
>> >
>> > On 16/08/2021 21:47:18+0800, Tony W Wang-oc wrote:
>> >> When the RTC divider is changed from reset to an operating time
>base,
>> >> the first update cycle should be 500ms later. But on some Zhaoxin
>SOCs,
>> >> this first update cycle is one second later.
>> >>
>> >> So set RTC time on these Zhaoxin SOCs will causing 500ms delay.
>> >>
>> >
>> > Can you explain what is the relationship between writing the
>divider and
>> > the 500ms delay?
>> >> Isn't the issue that you are using systohc and set_offset_nsec is
>set to
>> > NSEC_PER_SEC / 2 ?
>> >
>> No.
>> When using #hwclock -s to set RTC time and set_offset_nsec is
>> NSEC_PER_SEC / 2, the function mc146818_set_time() requires the first
>> update cycle after RTC divider be changed from reset to an operating
>> mode is 500ms as the MC146818A spec specified. But on some Zhaoxin
>SOCs,
>> the first update cycle of RTC is one second later after RTC divider
>be
>> changed from reset to an operating mode. So the first update cycle
>after
>> RTC divider be changed from reset to an operation mode on These SOCs
>> will causing 500ms delay with current mc146818_set_time()
>implementation.
>>
>
>What happens with hwclock --delay=0 -s ?
With "hwclock --delay=0 -s" still have this problem. Actually, this 500ms delay caused by writing the RTC time on these Zhaoxin SOCs.
As I've tested, with hwclock --delay=0 -w can fix it too.
Sincerely
TonyWWang-oc
On 17/08/2021 19:09:28+0800, [email protected] wrote:
>
>
> On August 16, 2021 8:36:48 PM GMT+08:00, Alexandre Belloni <[email protected]> wrote:
> >On 16/08/2021 18:03:13+0800, Tony W Wang-oc wrote:
> >>
> >> On 16/08/2021 16:24, Alexandre Belloni wrote:
> >> > Hello,
> >> >
> >> > On 16/08/2021 21:47:18+0800, Tony W Wang-oc wrote:
> >> >> When the RTC divider is changed from reset to an operating time
> >base,
> >> >> the first update cycle should be 500ms later. But on some Zhaoxin
> >SOCs,
> >> >> this first update cycle is one second later.
> >> >>
> >> >> So set RTC time on these Zhaoxin SOCs will causing 500ms delay.
> >> >>
> >> >
> >> > Can you explain what is the relationship between writing the
> >divider and
> >> > the 500ms delay?
> >> >> Isn't the issue that you are using systohc and set_offset_nsec is
> >set to
> >> > NSEC_PER_SEC / 2 ?
> >> >
> >> No.
> >> When using #hwclock -s to set RTC time and set_offset_nsec is
> >> NSEC_PER_SEC / 2, the function mc146818_set_time() requires the first
> >> update cycle after RTC divider be changed from reset to an operating
> >> mode is 500ms as the MC146818A spec specified. But on some Zhaoxin
> >SOCs,
> >> the first update cycle of RTC is one second later after RTC divider
> >be
> >> changed from reset to an operating mode. So the first update cycle
> >after
> >> RTC divider be changed from reset to an operation mode on These SOCs
> >> will causing 500ms delay with current mc146818_set_time()
> >implementation.
> >>
> >
> >What happens with hwclock --delay=0 -s ?
>
> With "hwclock --delay=0 -s" still have this problem. Actually, this 500ms delay caused by writing the RTC time on these Zhaoxin SOCs.
> As I've tested, with hwclock --delay=0 -w can fix it too.
>
Both -s and -w end up calling set_hardware_clock_exact() so both should
end up with the correct time. If this is not the case, then hwclock
needs to be fixed.
--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On August 17, 2021 9:21:03 PM GMT+08:00, Alexandre Belloni <[email protected]> wrote:
>On 17/08/2021 19:09:28+0800, [email protected] wrote:
>>
>>
>> On August 16, 2021 8:36:48 PM GMT+08:00, Alexandre Belloni
><[email protected]> wrote:
>> >On 16/08/2021 18:03:13+0800, Tony W Wang-oc wrote:
>> >>
>> >> On 16/08/2021 16:24, Alexandre Belloni wrote:
>> >> > Hello,
>> >> >
>> >> > On 16/08/2021 21:47:18+0800, Tony W Wang-oc wrote:
>> >> >> When the RTC divider is changed from reset to an operating time
>> >base,
>> >> >> the first update cycle should be 500ms later. But on some
>Zhaoxin
>> >SOCs,
>> >> >> this first update cycle is one second later.
>> >> >>
>> >> >> So set RTC time on these Zhaoxin SOCs will causing 500ms delay.
>> >> >>
>> >> >
>> >> > Can you explain what is the relationship between writing the
>> >divider and
>> >> > the 500ms delay?
>> >> >> Isn't the issue that you are using systohc and set_offset_nsec
>is
>> >set to
>> >> > NSEC_PER_SEC / 2 ?
>> >> >
>> >> No.
>> >> When using #hwclock -s to set RTC time and set_offset_nsec is
>> >> NSEC_PER_SEC / 2, the function mc146818_set_time() requires the
>first
>> >> update cycle after RTC divider be changed from reset to an
>operating
>> >> mode is 500ms as the MC146818A spec specified. But on some Zhaoxin
>> >SOCs,
>> >> the first update cycle of RTC is one second later after RTC
>divider
>> >be
>> >> changed from reset to an operating mode. So the first update cycle
>> >after
>> >> RTC divider be changed from reset to an operation mode on These
>SOCs
>> >> will causing 500ms delay with current mc146818_set_time()
>> >implementation.
>> >>
>> >
>> >What happens with hwclock --delay=0 -s ?
>>
>> With "hwclock --delay=0 -s" still have this problem. Actually, this
>500ms delay caused by writing the RTC time on these Zhaoxin SOCs.
>> As I've tested, with hwclock --delay=0 -w can fix it too.
>>
>
>Both -s and -w end up calling set_hardware_clock_exact() so both should
>end up with the correct time. If this is not the case, then hwclock
>needs to be fixed.
I checked Util-linux-2.37.2, hwclock -w will call
set_hardware_clock_exact() and hwclock -s will not.
Please correct me if I'm wrong.
Sincerely
TonyWWang-oc
On August 18, 2021 11:54:20 AM GMT+08:00, [email protected] wrote:
>
>
>On August 17, 2021 9:21:03 PM GMT+08:00, Alexandre Belloni
><[email protected]> wrote:
>>On 17/08/2021 19:09:28+0800, [email protected] wrote:
>>>
>>>
>>> On August 16, 2021 8:36:48 PM GMT+08:00, Alexandre Belloni
>><[email protected]> wrote:
>>> >On 16/08/2021 18:03:13+0800, Tony W Wang-oc wrote:
>>> >>
>>> >> On 16/08/2021 16:24, Alexandre Belloni wrote:
>>> >> > Hello,
>>> >> >
>>> >> > On 16/08/2021 21:47:18+0800, Tony W Wang-oc wrote:
>>> >> >> When the RTC divider is changed from reset to an operating
>time
>>> >base,
>>> >> >> the first update cycle should be 500ms later. But on some
>>Zhaoxin
>>> >SOCs,
>>> >> >> this first update cycle is one second later.
>>> >> >>
>>> >> >> So set RTC time on these Zhaoxin SOCs will causing 500ms
>delay.
>>> >> >>
>>> >> >
>>> >> > Can you explain what is the relationship between writing the
>>> >divider and
>>> >> > the 500ms delay?
>>> >> >> Isn't the issue that you are using systohc and set_offset_nsec
>>is
>>> >set to
>>> >> > NSEC_PER_SEC / 2 ?
>>> >> >
>>> >> No.
>>> >> When using #hwclock -s to set RTC time and set_offset_nsec is
>>> >> NSEC_PER_SEC / 2, the function mc146818_set_time() requires the
>>first
>>> >> update cycle after RTC divider be changed from reset to an
>>operating
>>> >> mode is 500ms as the MC146818A spec specified. But on some
>Zhaoxin
>>> >SOCs,
>>> >> the first update cycle of RTC is one second later after RTC
>>divider
>>> >be
>>> >> changed from reset to an operating mode. So the first update
>cycle
>>> >after
>>> >> RTC divider be changed from reset to an operation mode on These
>>SOCs
>>> >> will causing 500ms delay with current mc146818_set_time()
>>> >implementation.
>>> >>
>>> >
>>> >What happens with hwclock --delay=0 -s ?
>>>
>>> With "hwclock --delay=0 -s" still have this problem. Actually, this
>>500ms delay caused by writing the RTC time on these Zhaoxin SOCs.
>>> As I've tested, with hwclock --delay=0 -w can fix it too.
>>>
>>
>>Both -s and -w end up calling set_hardware_clock_exact() so both
>should
>>end up with the correct time. If this is not the case, then hwclock
>>needs to be fixed.
>
>I checked Util-linux-2.37.2, hwclock -w will call
>set_hardware_clock_exact() and hwclock -s will not.
>Please correct me if I'm wrong.
>
>Sincerely
>TonyWWang-oc
As explained before, the root cause of this problem is: these Zhaoxin SOCs
which belong to X86 architecture do not meet the requirement of
MC146818A compatible RTC about “When the divider is changed from reset
to an operating time base, the first update cycle is one-half second later”.
Actually the first update cycle on these Zhaoxin SOCs is one second later in
this case.
This problem is not only happened when running “hwclock -w”. On X86 platform,
the 0.5s delay is default for both “hwclock –w” and NTP driver’s invoke of
sync_cmos_clock(). So set RTC time caused by NTP driver also has this problem.
As have been test pass, skip operate the RTC_REG_A (which divider-control bits in)
with these Zhaoxin SOCs in function mc146818_set_time() can fix this problem.
I think this patch seems appropriate.
Sincerely
TonyWWang-oc