2020-10-21 10:50:39

by Guru Das Srinagesh

[permalink] [raw]
Subject: [RFC PATCH RESEND v1 0/3] Add support for Qualcomm MFD PMIC register layout

(Re-sending to add devicetree mailing list)

This is a follow-up as promised [1] to the earlier attempts [2] [3] to upstream
the driver that has been hitherto used to handle IRQs for Qualcomm's PMICs that
have multiple on-board peripherals when they are interfaced over the I2C
interface.

This series is a rewrite of that driver while making use of the regmap-irq
framework, which needs some modifications to handle the register layout of
Qualcomm's PMICs. This is an RFC because I would like to get feedback on my
general approach before submitting as a patch per se.

Upon inspection of the regmap-irq framework, it was observed that the
downstream driver was essentially replicating the framework's IRQ handling
logic (such as adding an IRQ domain, and the interrupt handler thread that
reads sub-irqs from a main status register). It was also observed that the
framework could not be used as-is because:
- Qualcomm's PMIC peripheral register layout does not follow a fixed
irq_reg_stride, and
- The "IRQ TYPE" configuration register takes one bit per interrupt, which when
set configures that interrupt as Edge triggered, and when cleared sets it to
Level triggered.
- There are two IRQ configuration registers in addition to "IRQ TYPE" that
further configure the IRQ type as triggered by rising-edge/level high or
alternatively, falling-edge/level low that have no support in the regmap-irq
framework currently.

This patch series has been tested on an internal platform using PM8008 as a
test MFD PMIC chip. PM8008 is a PMIC that contains 7 LDOs, 2 GPIOs, temperature
monitoring, and can be interfaced over I2C.

Both the framework modifications as well as the chip driver
have been submitted here for review. Some details about the specific
differences between the framework and QCOM PMICs' register layout are provided
below using PM8008 as an example.

[PM8008 peripheral register layout]

Of all the peripherals in PM8008, only a few need IRQ support. They are laid
out at the following base addresses (only four are added at the moment for
simplicity):

0x0900, 0x2400, 0xC000, 0xC100

Each peripheral is allocated a uniform size of 0x100 bytes and its IRQs are
configured through a set of registers that are located at fixed offsets from
the above base addresses, uniformly:

Register name Addr regmap-irq equivalent Comment
-----------------------------------------------------------------------
INT_RT_STS_OFFSET 0x10 (no equivalent) See #1 below
INT_SET_TYPE_OFFSET 0x11 type_base See #2 below
INT_POL_HIGH_OFFSET 0x12 (no equivalent) See #3 below
INT_POL_LOW_OFFSET 0x13 (no equivalent) See #3 below
INT_LATCHED_CLR_OFFSET 0x14 ack_base
INT_EN_SET_OFFSET 0x15 unmask_base See #4 below
INT_EN_CLR_OFFSET 0x16 mask_base See #4 below
INT_LATCHED_STS_OFFSET 0x18 status_base

Comments (all registers are one bit per interrupt):
1. INT_RT_STS_OFFSET is not used by the regmap-irq, so it may be ignored.
2. INT_SET_TYPE_OFFSET: 1 for edge trigger, 0 for level trigger.
3. Support needs to be added for writing to INT_POL_HIGH_OFFSET and
INT_POL_LOW_OFFSET correctly in the framework. Set to 1 or 0 to enable or
disable rising-edge/level high or falling-edge/level low.
4. Even though INT_EN_SET_OFFSET and INT_EN_CLR_OFFSET map to unmask_base and
mask_base in the regmap-irq framework conceptually, they are swapped in the
chip driver because `unmask_offset` in the framework expects unmask_base to
be larger than mask_base numerically. This has to be kept in mind while
reviewing the "mfd: Add PM8008 driver" patch below.

[Summary of framework changes]

The main thrust of the changes is to introduce an array of peripheral offset
values, which are to be added to the *_base addresses in order to arrive at the
correct register addresses per peripheral. In order to get at the first
peripheral's addresses, the first element of this array must be zero.

Since there are two new registers (INT_POL_HIGH_OFFSET and INT_POL_LOW_OFFSET),
add support for storing the per-peripheral values and also writing to them.
These will be used only if peripheral offsets are specified.

[1] https://lore.kernel.org/lkml/[email protected]/
[2] https://lore.kernel.org/lkml/[email protected]/
[3] https://lore.kernel.org/lkml/[email protected]/

Guru Das Srinagesh (3):
regmap-irq: Add support for peripheral offsets
dt-bindings: mfd: Add QCOM PM8008 MFD bindings
mfd: Add PM8008 driver

.../bindings/mfd/qcom,pm8008-irqchip.yaml | 103 +++++++++++
drivers/base/regmap/regmap-irq.c | 191 ++++++++++++++++----
drivers/mfd/Kconfig | 14 ++
drivers/mfd/Makefile | 1 +
drivers/mfd/qcom-pm8008.c | 197 +++++++++++++++++++++
include/linux/regmap.h | 6 +
6 files changed, 478 insertions(+), 34 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/qcom,pm8008-irqchip.yaml
create mode 100644 drivers/mfd/qcom-pm8008.c

--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


2020-10-21 19:55:36

by Guru Das Srinagesh

[permalink] [raw]
Subject: [RFC PATCH RESEND v1 2/3] dt-bindings: mfd: Add QCOM PM8008 MFD bindings

Add device tree bindings for the driver for Qualcomm Technology Inc.'s
PM8008 MFD PMIC.

Signed-off-by: Guru Das Srinagesh <[email protected]>
---
.../bindings/mfd/qcom,pm8008-irqchip.yaml | 103 +++++++++++++++++++++
1 file changed, 103 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/qcom,pm8008-irqchip.yaml

diff --git a/Documentation/devicetree/bindings/mfd/qcom,pm8008-irqchip.yaml b/Documentation/devicetree/bindings/mfd/qcom,pm8008-irqchip.yaml
new file mode 100644
index 0000000..296ff85
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qcom,pm8008-irqchip.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/qcom/qcom,pm8008-irqchip.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. PM8008 Multi-Function Device PMIC
+
+maintainers:
+ - Guru Das Srinagesh <[email protected]>
+
+description: |
+ PM8008 is a PMIC that contains 7 LDOs, 2 GPIOs, temperature monitoring, and
+ can be interfaced over I2C.
+
+properties:
+ compatible:
+ const: qcom,pm8008-irqchip
+
+ reg:
+ maxItems: 1
+
+ interrupt-names:
+ const: pm8008
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller:
+ type: boolean
+
+ "#address-cells":
+ const: 1
+ description:
+ Must be specified if child nodes are specified.
+
+ "#size-cells":
+ const: 0
+ description:
+ Must be specified if child nodes are specified.
+
+ "#interrupt-cells":
+ const: 2
+ description:
+ The first cell is the IRQ number, the second cell is the IRQ trigger flag.
+
+patternProperties:
+ "^.*[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
+ type: object
+ # Each peripheral in PM8008 must be represented as a child node with an
+ # optional label for referencing as phandle elsewhere. This is optional.
+ properties:
+ compatible:
+ description:
+ The compatible string for the peripheral's driver.
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - interrupts
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#interrupt-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ &qupv3_se13_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8008i@8 {
+ compatible = "qcom,pm8008-irqchip";
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-names = "pm8008";
+ interrupt-parent = <&tlmm>;
+ interrupts = <32 IRQ_TYPE_EDGE_RISING>;
+
+ pm8008_tz: qcom,temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x5 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+ };
+ };
+
+...
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-10-21 19:55:42

by Guru Das Srinagesh

[permalink] [raw]
Subject: [RFC PATCH RESEND v1 3/3] mfd: Add PM8008 driver

PM8008 is a PMIC that contains 7 LDOs, 2 GPIOs, temperature monitoring,
and can be interfaced over I2C. This driver uses the regmap-irq
framework to handle interrupts, creates a regmap and uses it to
instantiate all the child nodes under it in the device tree.

Only four peripherals have been added at the moment.

Every peripheral that has its TYPE register's hw default value as
zero must have it set to an all-ones mask (to cover all interrupts it
supports) in pm8008_init(). This is as per commit 84267d1b18ab ("regmap:
regmap-irq: Remove default irq type setting from core").

Signed-off-by: Guru Das Srinagesh <[email protected]>
---
drivers/mfd/Kconfig | 14 ++++
drivers/mfd/Makefile | 1 +
drivers/mfd/qcom-pm8008.c | 197 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 212 insertions(+)
create mode 100644 drivers/mfd/qcom-pm8008.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 33df083..3d4e989 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1960,6 +1960,20 @@ config MFD_ROHM_BD70528
10 bits SAR ADC for battery temperature monitor and 1S battery
charger.

+config MFD_QCOM_PM8008
+ tristate "QCOM PM8008 Power Management IC"
+ depends on I2C && OF
+ select REGMAP_I2C
+ select REGMAP_IRQ
+ help
+ Select this option to get support for the PM8008 PMIC chip. PM8008 is
+ a low-cost PMIC that contains 7 LDOs, 2 GPIOs, temperature
+ monitoring, and can be interfaced over I2C. This driver provides
+ common support for accessing the device by instantiating all the
+ child nodes under it in the device tree and, therefore, additional
+ drivers must be enabled in order to use the functionality of the
+ device.
+
config MFD_ROHM_BD71828
tristate "ROHM BD71828 Power Management IC"
depends on I2C=y
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a60e5f8..e316064 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -260,6 +260,7 @@ obj-$(CONFIG_RAVE_SP_CORE) += rave-sp.o
obj-$(CONFIG_MFD_ROHM_BD70528) += rohm-bd70528.o
obj-$(CONFIG_MFD_ROHM_BD71828) += rohm-bd71828.o
obj-$(CONFIG_MFD_ROHM_BD718XX) += rohm-bd718x7.o
+obj-$(CONFIG_MFD_QCOM_PM8008) += qcom-pm8008.o
obj-$(CONFIG_MFD_STMFX) += stmfx.o
obj-$(CONFIG_MFD_KHADAS_MCU) += khadas-mcu.o

diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c
new file mode 100644
index 0000000..56a5951
--- /dev/null
+++ b/drivers/mfd/qcom-pm8008.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+
+#define I2C_INTR_STATUS_BASE 0x0550
+#define INT_RT_STS_OFFSET 0x10
+#define INT_SET_TYPE_OFFSET 0x11
+#define INT_POL_HIGH_OFFSET 0x12
+#define INT_POL_LOW_OFFSET 0x13
+#define INT_LATCHED_CLR_OFFSET 0x14
+#define INT_EN_SET_OFFSET 0x15
+#define INT_EN_CLR_OFFSET 0x16
+#define INT_LATCHED_STS_OFFSET 0x18
+
+#define PM8008_NUM_PERIPHS 4
+
+#define PM8008_PERIPH_0_BASE 0x900
+#define PM8008_PERIPH_1_BASE 0x2400
+#define PM8008_PERIPH_2_BASE 0xC000
+#define PM8008_PERIPH_3_BASE 0xC100
+
+#define PM8008_TEMP_ALARM_ADDR PM8008_PERIPH_1_BASE
+#define PM8008_TEMP_ALARM_EN 0x1
+
+#define PM8008_STATUS_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_STS_OFFSET)
+#define PM8008_MASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_SET_OFFSET)
+#define PM8008_UNMASK_BASE (PM8008_PERIPH_0_BASE | INT_EN_CLR_OFFSET)
+#define PM8008_TYPE_BASE (PM8008_PERIPH_0_BASE | INT_SET_TYPE_OFFSET)
+#define PM8008_ACK_BASE (PM8008_PERIPH_0_BASE | INT_LATCHED_CLR_OFFSET)
+#define PM8008_POLARITY_HI_BASE (PM8008_PERIPH_0_BASE | INT_POL_HIGH_OFFSET)
+#define PM8008_POLARITY_LO_BASE (PM8008_PERIPH_0_BASE | INT_POL_LOW_OFFSET)
+
+#define ADDRESS_OFFSET(paddr, base) (paddr - base)
+
+#define PM8008_PERIPH_OFFSET(paddr) \
+ ADDRESS_OFFSET(paddr, PM8008_PERIPH_0_BASE)
+
+struct pm8008_data {
+ struct device *dev;
+ struct regmap *regmap;
+ int irq;
+ struct regmap_irq_chip_data *irq_data;
+};
+
+unsigned int pm8008_periph_offs[] = {
+ PM8008_PERIPH_OFFSET(PM8008_PERIPH_0_BASE),
+ PM8008_PERIPH_OFFSET(PM8008_PERIPH_1_BASE),
+ PM8008_PERIPH_OFFSET(PM8008_PERIPH_2_BASE),
+ PM8008_PERIPH_OFFSET(PM8008_PERIPH_3_BASE),
+};
+
+/* Need to define enums for the interrupt numbers and masks */
+static struct regmap_irq pm8008_irqs[] = {
+ /* MISC IRQs */
+ REGMAP_IRQ_REG(0, 0, BIT(0)),
+ REGMAP_IRQ_REG(1, 0, BIT(1)),
+ REGMAP_IRQ_REG(2, 0, BIT(2)),
+ REGMAP_IRQ_REG(3, 0, BIT(3)),
+ REGMAP_IRQ_REG(4, 0, BIT(4)),
+ /* TEMP ALARM IRQs */
+ REGMAP_IRQ_REG(5, 1, BIT(0)),
+ /* GPIO1 IRQs */
+ REGMAP_IRQ_REG(6, 2, BIT(0)),
+ /* GPIO2 IRQs */
+ REGMAP_IRQ_REG(7, 3, BIT(0)),
+};
+
+static struct regmap_irq_chip pm8008_irq_chip = {
+ .name = "pm8008_irq",
+ .main_status = I2C_INTR_STATUS_BASE,
+ .num_main_regs = 1,
+ .irqs = pm8008_irqs,
+ .num_irqs = ARRAY_SIZE(pm8008_irqs),
+ .num_regs = PM8008_NUM_PERIPHS,
+ .periph_offs = pm8008_periph_offs,
+ .status_base = PM8008_STATUS_BASE,
+ /*
+ * mask_base and unmask_base are swapped (SET and CLR) because
+ * "unmask_offset" in framework expects unmask_base to be larger than
+ * mask_base.
+ */
+ .mask_base = PM8008_MASK_BASE,
+ .unmask_base = PM8008_UNMASK_BASE,
+ .type_base = PM8008_TYPE_BASE,
+ .ack_base = PM8008_ACK_BASE,
+ .polarity_hi_base = PM8008_POLARITY_HI_BASE,
+ .polarity_lo_base = PM8008_POLARITY_LO_BASE,
+ .num_type_reg = PM8008_NUM_PERIPHS,
+};
+
+static struct regmap_config i2c_pmic_regmap_config = {
+ .reg_bits = 16,
+ .val_bits = 8,
+ .max_register = 0xFFFF,
+};
+
+static int pm8008_init(struct pm8008_data *chip)
+{
+ /*
+ * Set TEMP_ALARM peripheral's TYPE so that the regmap-irq framework
+ * reads this as the default value instead of zero, the HW default.
+ */
+
+ return regmap_write(chip->regmap,
+ (PM8008_TEMP_ALARM_ADDR | INT_SET_TYPE_OFFSET),
+ PM8008_TEMP_ALARM_EN);
+}
+
+static int pm8008_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int rc, i;
+ struct regmap_irq_type *type;
+ struct pm8008_data *chip;
+ struct regmap_irq_chip_data *irq_data;
+
+ chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ chip->dev = &client->dev;
+ chip->regmap = devm_regmap_init_i2c(client, &i2c_pmic_regmap_config);
+ if (!chip->regmap)
+ return -ENODEV;
+
+ i2c_set_clientdata(client, chip);
+
+ rc = pm8008_init(chip);
+ if (rc) {
+ dev_err(chip->dev, "Init failed: %d\n", rc);
+ return rc;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(pm8008_irqs); i++) {
+ type = &pm8008_irqs[i].type;
+
+ /* All IRQs support both edge and level triggers */
+ type->types_supported = (IRQ_TYPE_EDGE_BOTH |
+ IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW);
+
+ type->type_reg_offset = pm8008_irqs[i].reg_offset;
+ type->type_rising_val = pm8008_irqs[i].mask;
+ type->type_falling_val = pm8008_irqs[i].mask;
+ type->type_level_high_val = pm8008_irqs[i].mask;
+ type->type_level_low_val = pm8008_irqs[i].mask;
+ }
+
+ rc = devm_regmap_add_irq_chip(chip->dev, chip->regmap, client->irq,
+ IRQF_SHARED, 0, &pm8008_irq_chip, &irq_data);
+ if (rc) {
+ dev_err(chip->dev, "Failed to add IRQ chip: %d\n", rc);
+ return rc;
+ }
+
+ return devm_of_platform_populate(chip->dev);
+}
+
+static int pm8008_remove(struct i2c_client *client)
+{
+ i2c_set_clientdata(client, NULL);
+
+ return 0;
+}
+
+static const struct of_device_id pm8008_match[] = {
+ { .compatible = "qcom,pm8008-irqchip", },
+ { },
+};
+
+static const struct i2c_device_id i2c_pmic_id[] = {
+ { "qcom-i2c-pmic", 0 },
+ { },
+};
+MODULE_DEVICE_TABLE(i2c, i2c_pmic_id);
+
+static struct i2c_driver pm8008_irq_driver = {
+ .driver = {
+ .name = "pm8008-irqchip",
+ .of_match_table = pm8008_match,
+ },
+ .probe = pm8008_probe,
+ .remove = pm8008_remove,
+ .id_table = i2c_pmic_id,
+};
+module_i2c_driver(pm8008_irq_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("i2c:qcom-pm8008");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

2020-10-22 03:43:55

by Rob Herring (Arm)

[permalink] [raw]
Subject: Re: [RFC PATCH RESEND v1 2/3] dt-bindings: mfd: Add QCOM PM8008 MFD bindings

On Tue, 20 Oct 2020 15:33:42 -0700, Guru Das Srinagesh wrote:
> Add device tree bindings for the driver for Qualcomm Technology Inc.'s
> PM8008 MFD PMIC.
>
> Signed-off-by: Guru Das Srinagesh <[email protected]>
> ---
> .../bindings/mfd/qcom,pm8008-irqchip.yaml | 103 +++++++++++++++++++++
> 1 file changed, 103 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/qcom,pm8008-irqchip.yaml
>


My bot found errors running 'make dt_binding_check' on your patch:

Traceback (most recent call last):
File "/usr/local/bin/dt-extract-example", line 45, in <module>
binding = yaml.load(open(args.yamlfile, encoding='utf-8').read())
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 343, in load
return constructor.get_single_data()
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 111, in get_single_data
node = self.composer.get_single_node()
File "_ruamel_yaml.pyx", line 706, in _ruamel_yaml.CParser.get_single_node
File "_ruamel_yaml.pyx", line 724, in _ruamel_yaml.CParser._compose_document
File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
File "_ruamel_yaml.pyx", line 773, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 852, in _ruamel_yaml.CParser._compose_sequence_node
File "_ruamel_yaml.pyx", line 904, in _ruamel_yaml.CParser._parse_next_event
ruamel.yaml.parser.ParserError: while parsing a block collection
in "<unicode string>", line 77, column 3
did not find expected '-' indicator
in "<unicode string>", line 101, column 4
make[1]: *** [Documentation/devicetree/bindings/Makefile:20: Documentation/devicetree/bindings/mfd/qcom,pm8008-irqchip.example.dts] Error 1
make[1]: *** Deleting file 'Documentation/devicetree/bindings/mfd/qcom,pm8008-irqchip.example.dts'
make[1]: *** Waiting for unfinished jobs....
Traceback (most recent call last):
File "/usr/bin/yamllint", line 11, in <module>
load_entry_point('yamllint==1.20.0', 'console_scripts', 'yamllint')()
File "/usr/lib/python3/dist-packages/yamllint/cli.py", line 184, in run
prob_level = show_problems(problems, file, args_format=args.format,
File "/usr/lib/python3/dist-packages/yamllint/cli.py", line 91, in show_problems
for problem in problems:
File "/usr/lib/python3/dist-packages/yamllint/linter.py", line 200, in _run
for problem in get_cosmetic_problems(buffer, conf, filepath):
File "/usr/lib/python3/dist-packages/yamllint/linter.py", line 137, in get_cosmetic_problems
for problem in rule.check(rule_conf,
File "/usr/lib/python3/dist-packages/yamllint/rules/indentation.py", line 570, in check
for problem in _check(conf, token, prev, next, nextnext, context):
File "/usr/lib/python3/dist-packages/yamllint/rules/indentation.py", line 336, in _check
'wrong indentation: expected %d but found %d' %
TypeError: %d format: a number is required, not NoneType
make[1]: *** [Documentation/devicetree/bindings/Makefile:59: Documentation/devicetree/bindings/processed-schema-examples.json] Error 123
make: *** [Makefile:1366: dt_binding_check] Error 2


See https://patchwork.ozlabs.org/patch/1385253

The base for the patch is generally the last rc1. Any dependencies
should be noted.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.