qca8xxx is 4 * 2.5GBaseT ports chip, working as switch mode
named by qca8386, or working as PHY mode named by qca8084,
clock hardware reigster is accessed by MDIO bus.
This patch series add the clock controller of qca8363/qca8084,
and add the clock ops clk_branch2_prepare_ops to avoid spin lock
used during the clock operation of qca8k clock controller where
the sleep happens when accessing clock control register by MDIO
bus.
Changes in v2:
* remove clock flag CLK_ENABLE_MUTEX_LOCK.
* add clock ops clk_branch2_qca8k_ops.
* improve yaml file for fixing dtschema warnings.
* enable clock controller driver in defconfig.
Changes in v3:
* rename clk_branch2_qca8k_ops to clk_branch2_mdio_ops.
* fix review comments on yaml file.
* use dev_err_probe on driver probe error.
* only use the compatible "qcom,qca8084-nsscc".
* remove enable clock controller driver patch.
Changes in v4:
* add _qcom_cc_really_probe function.
* commonizing the probe function.
* remove flag CLK_IS_CRITICAL from clocks only needed
to be enabled in switch device.
* update device tree property reg to 0x10.
Changes in v5:
* commonize qcom_cc_really_probe.
* add halt_check for the branch clocks.
* fix the review comments on nsscc-qca8k.c.
Changes in v6:
* rename clk_branch2_mdio_ops to clk_branch2_prepare_ops.
Changes in v7:
* remove the clock flag CLK_IS_CRITICAL.
* optimize the file nsscc-qca8k.c.
* identify & fix the comments from Stephen.
Changes in v8:
* add dependency on ARM in Kconfig.
Changes in v9:
* take the clk_ops clk_rcg2_mux_closest_ops to remove the
redundant freq_tbls.
Changes in v10:
* fix the patch CHECK and improve the comments.
Changes in v11:
* update the clock names to reflect hardware connecton.
NSS_CC_MAC4_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC ->
NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_DIV_CLK_SRC
NSS_CC_MAC4_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC ->
NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_DIV_CLK_SRC
* resolve the qcom_cc_really_probe merge conflict based
on the latest code.
Changes in v12:
* Fix the compile error caused by the parameter of
qcom_cc_really_probe updated from pdev to &pdev->dev in the
new merged clock driver gcc-sm4450.c and camcc-sm8550.c.
Luo Jie (4):
clk: qcom: branch: Add clk_branch2_prepare_ops
dt-bindings: clock: add qca8386/qca8084 clock and reset definitions
clk: qcom: common: commonize qcom_cc_really_probe
clk: qcom: add clock controller driver for qca8386/qca8084
.../bindings/clock/qcom,qca8k-nsscc.yaml | 79 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apss-ipq6018.c | 2 +-
drivers/clk/qcom/camcc-sc7180.c | 2 +-
drivers/clk/qcom/camcc-sc7280.c | 2 +-
drivers/clk/qcom/camcc-sdm845.c | 2 +-
drivers/clk/qcom/camcc-sm6350.c | 2 +-
drivers/clk/qcom/camcc-sm8250.c | 2 +-
drivers/clk/qcom/camcc-sm8450.c | 2 +-
drivers/clk/qcom/camcc-sm8550.c | 2 +-
drivers/clk/qcom/clk-branch.c | 7 +
drivers/clk/qcom/clk-branch.h | 1 +
drivers/clk/qcom/common.c | 7 +-
drivers/clk/qcom/common.h | 2 +-
drivers/clk/qcom/dispcc-qcm2290.c | 2 +-
drivers/clk/qcom/dispcc-sc7180.c | 2 +-
drivers/clk/qcom/dispcc-sc7280.c | 2 +-
drivers/clk/qcom/dispcc-sc8280xp.c | 2 +-
drivers/clk/qcom/dispcc-sdm845.c | 2 +-
drivers/clk/qcom/dispcc-sm6115.c | 2 +-
drivers/clk/qcom/dispcc-sm6125.c | 2 +-
drivers/clk/qcom/dispcc-sm6350.c | 2 +-
drivers/clk/qcom/dispcc-sm6375.c | 2 +-
drivers/clk/qcom/dispcc-sm8250.c | 2 +-
drivers/clk/qcom/dispcc-sm8450.c | 2 +-
drivers/clk/qcom/dispcc-sm8550.c | 2 +-
drivers/clk/qcom/gcc-ipq5018.c | 2 +-
drivers/clk/qcom/gcc-ipq6018.c | 2 +-
drivers/clk/qcom/gcc-ipq8074.c | 2 +-
drivers/clk/qcom/gcc-mdm9607.c | 2 +-
drivers/clk/qcom/gcc-mdm9615.c | 2 +-
drivers/clk/qcom/gcc-msm8917.c | 2 +-
drivers/clk/qcom/gcc-msm8939.c | 2 +-
drivers/clk/qcom/gcc-msm8953.c | 2 +-
drivers/clk/qcom/gcc-msm8976.c | 2 +-
drivers/clk/qcom/gcc-msm8996.c | 2 +-
drivers/clk/qcom/gcc-msm8998.c | 2 +-
drivers/clk/qcom/gcc-qcm2290.c | 2 +-
drivers/clk/qcom/gcc-qcs404.c | 2 +-
drivers/clk/qcom/gcc-qdu1000.c | 2 +-
drivers/clk/qcom/gcc-sa8775p.c | 2 +-
drivers/clk/qcom/gcc-sc7180.c | 2 +-
drivers/clk/qcom/gcc-sc7280.c | 2 +-
drivers/clk/qcom/gcc-sc8180x.c | 2 +-
drivers/clk/qcom/gcc-sc8280xp.c | 2 +-
drivers/clk/qcom/gcc-sdm660.c | 2 +-
drivers/clk/qcom/gcc-sdm845.c | 2 +-
drivers/clk/qcom/gcc-sdx55.c | 2 +-
drivers/clk/qcom/gcc-sdx65.c | 2 +-
drivers/clk/qcom/gcc-sdx75.c | 2 +-
drivers/clk/qcom/gcc-sm4450.c | 2 +-
drivers/clk/qcom/gcc-sm6115.c | 2 +-
drivers/clk/qcom/gcc-sm6125.c | 2 +-
drivers/clk/qcom/gcc-sm6350.c | 2 +-
drivers/clk/qcom/gcc-sm6375.c | 2 +-
drivers/clk/qcom/gcc-sm7150.c | 2 +-
drivers/clk/qcom/gcc-sm8150.c | 2 +-
drivers/clk/qcom/gcc-sm8250.c | 2 +-
drivers/clk/qcom/gcc-sm8350.c | 2 +-
drivers/clk/qcom/gcc-sm8450.c | 2 +-
drivers/clk/qcom/gcc-sm8550.c | 2 +-
drivers/clk/qcom/gpucc-msm8998.c | 2 +-
drivers/clk/qcom/gpucc-sa8775p.c | 2 +-
drivers/clk/qcom/gpucc-sc7180.c | 2 +-
drivers/clk/qcom/gpucc-sc7280.c | 2 +-
drivers/clk/qcom/gpucc-sc8280xp.c | 2 +-
drivers/clk/qcom/gpucc-sdm660.c | 2 +-
drivers/clk/qcom/gpucc-sdm845.c | 2 +-
drivers/clk/qcom/gpucc-sm6115.c | 2 +-
drivers/clk/qcom/gpucc-sm6125.c | 2 +-
drivers/clk/qcom/gpucc-sm6350.c | 2 +-
drivers/clk/qcom/gpucc-sm6375.c | 2 +-
drivers/clk/qcom/gpucc-sm8150.c | 2 +-
drivers/clk/qcom/gpucc-sm8250.c | 2 +-
drivers/clk/qcom/gpucc-sm8350.c | 2 +-
drivers/clk/qcom/gpucc-sm8450.c | 2 +-
drivers/clk/qcom/gpucc-sm8550.c | 2 +-
drivers/clk/qcom/lcc-ipq806x.c | 2 +-
drivers/clk/qcom/lcc-msm8960.c | 2 +-
drivers/clk/qcom/lpassaudiocc-sc7280.c | 4 +-
drivers/clk/qcom/lpasscorecc-sc7180.c | 2 +-
drivers/clk/qcom/lpasscorecc-sc7280.c | 2 +-
drivers/clk/qcom/mmcc-msm8960.c | 2 +-
drivers/clk/qcom/mmcc-msm8974.c | 2 +-
drivers/clk/qcom/mmcc-msm8994.c | 2 +-
drivers/clk/qcom/mmcc-msm8996.c | 2 +-
drivers/clk/qcom/mmcc-msm8998.c | 2 +-
drivers/clk/qcom/mmcc-sdm660.c | 2 +-
drivers/clk/qcom/nsscc-qca8k.c | 2139 +++++++++++++++++
drivers/clk/qcom/tcsrcc-sm8550.c | 2 +-
drivers/clk/qcom/videocc-sc7180.c | 2 +-
drivers/clk/qcom/videocc-sc7280.c | 2 +-
drivers/clk/qcom/videocc-sdm845.c | 2 +-
drivers/clk/qcom/videocc-sm8150.c | 2 +-
drivers/clk/qcom/videocc-sm8250.c | 2 +-
drivers/clk/qcom/videocc-sm8350.c | 2 +-
drivers/clk/qcom/videocc-sm8450.c | 2 +-
drivers/clk/qcom/videocc-sm8550.c | 2 +-
include/dt-bindings/clock/qcom,qca8k-nsscc.h | 101 +
include/dt-bindings/reset/qcom,qca8k-nsscc.h | 75 +
101 files changed, 2508 insertions(+), 97 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml
create mode 100644 drivers/clk/qcom/nsscc-qca8k.c
create mode 100644 include/dt-bindings/clock/qcom,qca8k-nsscc.h
create mode 100644 include/dt-bindings/reset/qcom,qca8k-nsscc.h
base-commit: ff269e2cd5adce4ae14f883fc9c8803bc43ee1e9
--
2.42.0
QCA8386/QCA8084 includes the clock & reset controller that is
accessed by MDIO bus. Two work modes are supported, qca8386 works
as switch mode, qca8084 works as PHY mode.
Signed-off-by: Luo Jie <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/clock/qcom,qca8k-nsscc.yaml | 79 ++++++++++++++
include/dt-bindings/clock/qcom,qca8k-nsscc.h | 101 ++++++++++++++++++
include/dt-bindings/reset/qcom,qca8k-nsscc.h | 75 +++++++++++++
3 files changed, 255 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml
create mode 100644 include/dt-bindings/clock/qcom,qca8k-nsscc.h
create mode 100644 include/dt-bindings/reset/qcom,qca8k-nsscc.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml
new file mode 100644
index 000000000000..21e7c4150b6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+ - Luo Jie <[email protected]>
+
+description: |
+ Qualcomm NSS clock control module provides the clocks and resets
+ on QCA8386(switch mode)/QCA8084(PHY mode)
+
+ See also::
+ include/dt-bindings/clock/qcom,qca8k-nsscc.h
+ include/dt-bindings/reset/qcom,qca8k-nsscc.h
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,qca8084-nsscc
+ - items:
+ - enum:
+ - qcom,qca8082-nsscc
+ - qcom,qca8085-nsscc
+ - qcom,qca8384-nsscc
+ - qcom,qca8385-nsscc
+ - qcom,qca8386-nsscc
+ - const: qcom,qca8084-nsscc
+
+ clocks:
+ items:
+ - description: Chip XO source
+ - description: UNIPHY0 RX 312P5M/125M clock source
+ - description: UNIPHY0 TX 312P5M/125M clock source
+ - description: UNIPHY1 RX 312P5M/125M clock source
+ - description: UNIPHY1 TX 312P5M/125M clock source
+ - description: UNIPHY1 RX 312P5M clock source
+ - description: UNIPHY1 TX 312P5M clock source
+
+ reg:
+ items:
+ - description: MDIO bus address for Clock & Reset Controller register
+
+required:
+ - compatible
+ - clocks
+ - reg
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clock-controller@18 {
+ compatible = "qcom,qca8084-nsscc";
+ reg = <0x18>;
+ clocks = <&qca8k_xo>,
+ <&qca8k_uniphy0_rx>,
+ <&qca8k_uniphy0_tx>,
+ <&qca8k_uniphy1_rx>,
+ <&qca8k_uniphy1_tx>,
+ <&qca8k_uniphy1_rx312p5m>,
+ <&qca8k_uniphy1_tx312p5m>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,qca8k-nsscc.h b/include/dt-bindings/clock/qcom,qca8k-nsscc.h
new file mode 100644
index 000000000000..0ac3e4c69a1a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,qca8k-nsscc.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H
+#define _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H
+
+#define NSS_CC_SWITCH_CORE_CLK_SRC 0
+#define NSS_CC_SWITCH_CORE_CLK 1
+#define NSS_CC_APB_BRIDGE_CLK 2
+#define NSS_CC_MAC0_TX_CLK_SRC 3
+#define NSS_CC_MAC0_TX_DIV_CLK_SRC 4
+#define NSS_CC_MAC0_TX_CLK 5
+#define NSS_CC_MAC0_TX_SRDS1_CLK 6
+#define NSS_CC_MAC0_RX_CLK_SRC 7
+#define NSS_CC_MAC0_RX_DIV_CLK_SRC 8
+#define NSS_CC_MAC0_RX_CLK 9
+#define NSS_CC_MAC0_RX_SRDS1_CLK 10
+#define NSS_CC_MAC1_TX_CLK_SRC 11
+#define NSS_CC_MAC1_TX_DIV_CLK_SRC 12
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_DIV_CLK_SRC 13
+#define NSS_CC_MAC1_SRDS1_CH0_RX_CLK 14
+#define NSS_CC_MAC1_TX_CLK 15
+#define NSS_CC_MAC1_GEPHY0_TX_CLK 16
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_CLK 17
+#define NSS_CC_MAC1_RX_CLK_SRC 18
+#define NSS_CC_MAC1_RX_DIV_CLK_SRC 19
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_DIV_CLK_SRC 20
+#define NSS_CC_MAC1_SRDS1_CH0_TX_CLK 21
+#define NSS_CC_MAC1_RX_CLK 22
+#define NSS_CC_MAC1_GEPHY0_RX_CLK 23
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_CLK 24
+#define NSS_CC_MAC2_TX_CLK_SRC 25
+#define NSS_CC_MAC2_TX_DIV_CLK_SRC 26
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_DIV_CLK_SRC 27
+#define NSS_CC_MAC2_SRDS1_CH1_RX_CLK 28
+#define NSS_CC_MAC2_TX_CLK 29
+#define NSS_CC_MAC2_GEPHY1_TX_CLK 30
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_CLK 31
+#define NSS_CC_MAC2_RX_CLK_SRC 32
+#define NSS_CC_MAC2_RX_DIV_CLK_SRC 33
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_DIV_CLK_SRC 34
+#define NSS_CC_MAC2_SRDS1_CH1_TX_CLK 35
+#define NSS_CC_MAC2_RX_CLK 36
+#define NSS_CC_MAC2_GEPHY1_RX_CLK 37
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_CLK 38
+#define NSS_CC_MAC3_TX_CLK_SRC 39
+#define NSS_CC_MAC3_TX_DIV_CLK_SRC 40
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC 41
+#define NSS_CC_MAC3_SRDS1_CH2_RX_CLK 42
+#define NSS_CC_MAC3_TX_CLK 43
+#define NSS_CC_MAC3_GEPHY2_TX_CLK 44
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_CLK 45
+#define NSS_CC_MAC3_RX_CLK_SRC 46
+#define NSS_CC_MAC3_RX_DIV_CLK_SRC 47
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC 48
+#define NSS_CC_MAC3_SRDS1_CH2_TX_CLK 49
+#define NSS_CC_MAC3_RX_CLK 50
+#define NSS_CC_MAC3_GEPHY2_RX_CLK 51
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_CLK 52
+#define NSS_CC_MAC4_TX_CLK_SRC 53
+#define NSS_CC_MAC4_TX_DIV_CLK_SRC 54
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_DIV_CLK_SRC 55
+#define NSS_CC_MAC4_SRDS1_CH3_RX_CLK 56
+#define NSS_CC_MAC4_TX_CLK 57
+#define NSS_CC_MAC4_GEPHY3_TX_CLK 58
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_CLK 59
+#define NSS_CC_MAC4_RX_CLK_SRC 60
+#define NSS_CC_MAC4_RX_DIV_CLK_SRC 61
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_DIV_CLK_SRC 62
+#define NSS_CC_MAC4_SRDS1_CH3_TX_CLK 63
+#define NSS_CC_MAC4_RX_CLK 64
+#define NSS_CC_MAC4_GEPHY3_RX_CLK 65
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_CLK 66
+#define NSS_CC_MAC5_TX_CLK_SRC 67
+#define NSS_CC_MAC5_TX_DIV_CLK_SRC 68
+#define NSS_CC_MAC5_TX_SRDS0_CLK 69
+#define NSS_CC_MAC5_TX_CLK 70
+#define NSS_CC_MAC5_RX_CLK_SRC 71
+#define NSS_CC_MAC5_RX_DIV_CLK_SRC 72
+#define NSS_CC_MAC5_RX_SRDS0_CLK 73
+#define NSS_CC_MAC5_RX_CLK 74
+#define NSS_CC_MAC5_TX_SRDS0_CLK_SRC 75
+#define NSS_CC_MAC5_RX_SRDS0_CLK_SRC 76
+#define NSS_CC_AHB_CLK_SRC 77
+#define NSS_CC_AHB_CLK 78
+#define NSS_CC_SEC_CTRL_AHB_CLK 79
+#define NSS_CC_TLMM_CLK 80
+#define NSS_CC_TLMM_AHB_CLK 81
+#define NSS_CC_CNOC_AHB_CLK 82
+#define NSS_CC_MDIO_AHB_CLK 83
+#define NSS_CC_MDIO_MASTER_AHB_CLK 84
+#define NSS_CC_SYS_CLK_SRC 85
+#define NSS_CC_SRDS0_SYS_CLK 86
+#define NSS_CC_SRDS1_SYS_CLK 87
+#define NSS_CC_GEPHY0_SYS_CLK 88
+#define NSS_CC_GEPHY1_SYS_CLK 89
+#define NSS_CC_GEPHY2_SYS_CLK 90
+#define NSS_CC_GEPHY3_SYS_CLK 91
+#endif
diff --git a/include/dt-bindings/reset/qcom,qca8k-nsscc.h b/include/dt-bindings/reset/qcom,qca8k-nsscc.h
new file mode 100644
index 000000000000..79121a513823
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,qca8k-nsscc.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H
+#define _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H
+
+#define NSS_CC_SWITCH_CORE_ARES 1
+#define NSS_CC_APB_BRIDGE_ARES 2
+#define NSS_CC_MAC0_TX_ARES 3
+#define NSS_CC_MAC0_TX_SRDS1_ARES 4
+#define NSS_CC_MAC0_RX_ARES 5
+#define NSS_CC_MAC0_RX_SRDS1_ARES 6
+#define NSS_CC_MAC1_SRDS1_CH0_RX_ARES 7
+#define NSS_CC_MAC1_TX_ARES 8
+#define NSS_CC_MAC1_GEPHY0_TX_ARES 9
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES 10
+#define NSS_CC_MAC1_SRDS1_CH0_TX_ARES 11
+#define NSS_CC_MAC1_RX_ARES 12
+#define NSS_CC_MAC1_GEPHY0_RX_ARES 13
+#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES 14
+#define NSS_CC_MAC2_SRDS1_CH1_RX_ARES 15
+#define NSS_CC_MAC2_TX_ARES 16
+#define NSS_CC_MAC2_GEPHY1_TX_ARES 17
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES 18
+#define NSS_CC_MAC2_SRDS1_CH1_TX_ARES 19
+#define NSS_CC_MAC2_RX_ARES 20
+#define NSS_CC_MAC2_GEPHY1_RX_ARES 21
+#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES 22
+#define NSS_CC_MAC3_SRDS1_CH2_RX_ARES 23
+#define NSS_CC_MAC3_TX_ARES 24
+#define NSS_CC_MAC3_GEPHY2_TX_ARES 25
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES 26
+#define NSS_CC_MAC3_SRDS1_CH2_TX_ARES 27
+#define NSS_CC_MAC3_RX_ARES 28
+#define NSS_CC_MAC3_GEPHY2_RX_ARES 29
+#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES 30
+#define NSS_CC_MAC4_SRDS1_CH3_RX_ARES 31
+#define NSS_CC_MAC4_TX_ARES 32
+#define NSS_CC_MAC4_GEPHY3_TX_ARES 33
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES 34
+#define NSS_CC_MAC4_SRDS1_CH3_TX_ARES 35
+#define NSS_CC_MAC4_RX_ARES 36
+#define NSS_CC_MAC4_GEPHY3_RX_ARES 37
+#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES 38
+#define NSS_CC_MAC5_TX_ARES 39
+#define NSS_CC_MAC5_TX_SRDS0_ARES 40
+#define NSS_CC_MAC5_RX_ARES 41
+#define NSS_CC_MAC5_RX_SRDS0_ARES 42
+#define NSS_CC_AHB_ARES 43
+#define NSS_CC_SEC_CTRL_AHB_ARES 44
+#define NSS_CC_TLMM_ARES 45
+#define NSS_CC_TLMM_AHB_ARES 46
+#define NSS_CC_CNOC_AHB_ARES 47
+#define NSS_CC_MDIO_AHB_ARES 48
+#define NSS_CC_MDIO_MASTER_AHB_ARES 49
+#define NSS_CC_SRDS0_SYS_ARES 50
+#define NSS_CC_SRDS1_SYS_ARES 51
+#define NSS_CC_GEPHY0_SYS_ARES 52
+#define NSS_CC_GEPHY1_SYS_ARES 53
+#define NSS_CC_GEPHY2_SYS_ARES 54
+#define NSS_CC_GEPHY3_SYS_ARES 55
+#define NSS_CC_SEC_CTRL_ARES 56
+#define NSS_CC_SEC_CTRL_SENSE_ARES 57
+#define NSS_CC_SLEEP_ARES 58
+#define NSS_CC_DEBUG_ARES 59
+#define NSS_CC_GEPHY0_ARES 60
+#define NSS_CC_GEPHY1_ARES 61
+#define NSS_CC_GEPHY2_ARES 62
+#define NSS_CC_GEPHY3_ARES 63
+#define NSS_CC_DSP_ARES 64
+#define NSS_CC_GLOBAL_ARES 65
+#define NSS_CC_XPCS_ARES 66
+#endif
--
2.42.0
The clock controller driver of qca8386/qca8084 is registered
as the MDIO device, the hardware register is accessed by MDIO bus
that is normally used to access general PHY device, which is
different from the current existed qcom clock controller drivers
using ioremap to access hardware clock registers, nsscc-qca8k is
accessed via an MDIO bus.
MDIO bus is commonly utilized by both qca8386/qca8084 and other
PHY devices, so the mutex lock mdio_bus->mdio_lock should be
used instead of using the mutex lock of remap.
To access the hardware clock registers of qca8386/qca8084, there
is a special MDIO frame sequence, which needs to be sent to the
device.
Signed-off-by: Luo Jie <[email protected]>
Reviewed-by: Bryan O'Donoghue <[email protected]>
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/nsscc-qca8k.c | 2139 ++++++++++++++++++++++++++++++++
3 files changed, 2149 insertions(+)
create mode 100644 drivers/clk/qcom/nsscc-qca8k.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ad1acd9b7426..76faf5a6293a 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -204,6 +204,15 @@ config IPQ_GCC_9574
i2c, USB, SD/eMMC, etc. Select this for the root clock
of ipq9574.
+config IPQ_NSSCC_QCA8K
+ tristate "QCA8K(QCA8386 or QCA8084) NSS Clock Controller"
+ depends on MDIO_BUS || COMPILE_TEST
+ help
+ Support for NSS(Network SubSystem) clock controller on
+ qca8386/qca8084 chip.
+ Say Y or M if you want to use network features of switch or
+ PHY device. Select this for the root clock of qca8k.
+
config MSM_GCC_8660
tristate "MSM8660 Global Clock Controller"
depends on ARM || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 17edd73f9839..21b0669ec514 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
+obj-$(CONFIG_IPQ_NSSCC_QCA8K) += nsscc-qca8k.o
obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
diff --git a/drivers/clk/qcom/nsscc-qca8k.c b/drivers/clk/qcom/nsscc-qca8k.c
new file mode 100644
index 000000000000..bb5ac38a263c
--- /dev/null
+++ b/drivers/clk/qcom/nsscc-qca8k.c
@@ -0,0 +1,2139 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+#include <linux/phy.h>
+#include <linux/mdio.h>
+
+#include <dt-bindings/clock/qcom,qca8k-nsscc.h>
+#include <dt-bindings/reset/qcom,qca8k-nsscc.h>
+
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "common.h"
+#include "reset.h"
+
+#define QCA8K_CLK_REG_BASE 0x800000
+#define QCA8K_HIGH_ADDR_PREFIX 0x18
+#define QCA8K_LOW_ADDR_PREFIX 0x10
+#define QCA8K_CFG_PAGE_REG 0xc
+#define QCA8K_CLK_REG_MASK GENMASK(4, 0)
+#define QCA8K_CLK_PHY_ADDR_MASK GENMASK(7, 5)
+#define QCA8K_CLK_PAGE_MASK GENMASK(23, 8)
+#define QCA8K_REG_DATA_UPPER_16_BITS BIT(1)
+
+enum {
+ DT_XO,
+ DT_UNIPHY0_RX_CLK,
+ DT_UNIPHY0_TX_CLK,
+ DT_UNIPHY1_RX_CLK,
+ DT_UNIPHY1_TX_CLK,
+ DT_UNIPHY1_RX312P5M_CLK,
+ DT_UNIPHY1_TX312P5M_CLK,
+};
+
+enum {
+ P_XO,
+ P_UNIPHY0_RX,
+ P_UNIPHY0_TX,
+ P_UNIPHY1_RX,
+ P_UNIPHY1_TX,
+ P_UNIPHY1_RX312P5M,
+ P_UNIPHY1_TX312P5M,
+ P_MAC4_RX_DIV,
+ P_MAC4_TX_DIV,
+ P_MAC5_RX_DIV,
+ P_MAC5_TX_DIV,
+};
+
+static const struct clk_parent_data nss_cc_uniphy1_tx312p5m_data[] = {
+ { .index = DT_XO },
+ { .index = DT_UNIPHY1_TX312P5M_CLK },
+};
+
+static const struct parent_map nss_cc_uniphy1_tx312p5m_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY1_TX312P5M, 1 },
+};
+
+static struct clk_rcg2 nss_cc_switch_core_clk_src = {
+ .cmd_rcgr = 0x0,
+ .hid_width = 5,
+ .parent_map = nss_cc_uniphy1_tx312p5m_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_switch_core_clk_src",
+ .parent_data = nss_cc_uniphy1_tx312p5m_data,
+ .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_data),
+ .ops = &clk_rcg2_mux_closest_ops,
+ },
+};
+
+static struct clk_branch nss_cc_switch_core_clk = {
+ .halt_reg = 0x8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_switch_core_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_switch_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_apb_bridge_clk = {
+ .halt_reg = 0x10,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x10,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_apb_bridge_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_switch_core_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static const struct clk_parent_data nss_cc_uniphy1_tx_data[] = {
+ { .index = DT_XO },
+ { .index = DT_UNIPHY1_TX_CLK },
+};
+
+static const struct parent_map nss_cc_uniphy1_tx_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY1_TX, 2 },
+};
+
+static struct clk_rcg2 nss_cc_mac0_tx_clk_src = {
+ .cmd_rcgr = 0x14,
+ .hid_width = 5,
+ .parent_map = nss_cc_uniphy1_tx_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac0_tx_clk_src",
+ .parent_data = nss_cc_uniphy1_tx_data,
+ .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx_data),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_mux_closest_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac0_tx_div_clk_src = {
+ .reg = 0x1c,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac0_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac0_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac0_tx_clk = {
+ .halt_reg = 0x20,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x20,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac0_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac0_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac0_tx_srds1_clk = {
+ .halt_reg = 0x24,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x24,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac0_tx_srds1_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac0_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static const struct clk_parent_data nss_cc_uniphy1_rx_tx_data[] = {
+ { .index = DT_XO },
+ { .index = DT_UNIPHY1_RX_CLK },
+ { .index = DT_UNIPHY1_TX_CLK },
+};
+
+static const struct parent_map nss_cc_uniphy1_rx_tx_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY1_RX, 1 },
+ { P_UNIPHY1_TX, 2 },
+};
+
+static struct clk_rcg2 nss_cc_mac0_rx_clk_src = {
+ .cmd_rcgr = 0x28,
+ .hid_width = 5,
+ .parent_map = nss_cc_uniphy1_rx_tx_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac0_rx_clk_src",
+ .parent_data = nss_cc_uniphy1_rx_tx_data,
+ .num_parents = ARRAY_SIZE(nss_cc_uniphy1_rx_tx_data),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_mux_closest_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac0_rx_div_clk_src = {
+ .reg = 0x30,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac0_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac0_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac0_rx_clk = {
+ .halt_reg = 0x34,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x34,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac0_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac0_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac0_rx_srds1_clk = {
+ .halt_reg = 0x3c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac0_rx_srds1_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac0_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static const struct clk_parent_data nss_cc_uniphy1_rx_tx312p5m_data[] = {
+ { .index = DT_XO },
+ { .index = DT_UNIPHY1_TX312P5M_CLK },
+ { .index = DT_UNIPHY1_RX312P5M_CLK },
+};
+
+static const struct parent_map nss_cc_uniphy1_rx_tx312p5m_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY1_TX312P5M, 6 },
+ { P_UNIPHY1_RX312P5M, 7 },
+};
+
+static const struct freq_tbl ftbl_nss_cc_mac1_tx_clk_src[] = {
+ F(25000000, P_UNIPHY1_TX312P5M, 12.5, 0, 0),
+ F(25000000, P_UNIPHY1_RX312P5M, 12.5, 0, 0),
+ F(50000000, P_XO, 1, 0, 0),
+ F(125000000, P_UNIPHY1_TX312P5M, 2.5, 0, 0),
+ F(125000000, P_UNIPHY1_RX312P5M, 2.5, 0, 0),
+ F(312500000, P_UNIPHY1_TX312P5M, 1, 0, 0),
+ F(312500000, P_UNIPHY1_RX312P5M, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_mac1_tx_clk_src = {
+ .cmd_rcgr = 0x40,
+ .freq_tbl = ftbl_nss_cc_mac1_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = nss_cc_uniphy1_rx_tx312p5m_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac1_tx_clk_src",
+ .parent_data = nss_cc_uniphy1_rx_tx312p5m_data,
+ .num_parents = ARRAY_SIZE(nss_cc_uniphy1_rx_tx312p5m_data),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac1_tx_div_clk_src = {
+ .reg = 0x48,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac1_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac1_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac1_srds1_ch0_xgmii_rx_div_clk_src = {
+ .reg = 0x4c,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac1_srds1_ch0_xgmii_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac1_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac1_srds1_ch0_rx_clk = {
+ .halt_reg = 0x50,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x50,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac1_srds1_ch0_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac1_tx_clk = {
+ .halt_reg = 0x54,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x54,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac1_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac1_gephy0_tx_clk = {
+ .halt_reg = 0x58,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x58,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac1_gephy0_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac1_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac1_srds1_ch0_xgmii_rx_clk = {
+ .halt_reg = 0x5c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac1_srds1_ch0_xgmii_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac1_srds1_ch0_xgmii_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static const struct clk_parent_data nss_cc_uniphy1_tx312p5m_prx_data[] = {
+ { .index = DT_XO },
+ { .index = DT_UNIPHY1_TX312P5M_CLK },
+};
+
+static const struct parent_map nss_cc_uniphy1_tx312p5m_prx_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY1_TX312P5M, 6 },
+};
+
+static const struct freq_tbl ftbl_nss_cc_mac1_rx_clk_src[] = {
+ F(25000000, P_UNIPHY1_TX312P5M, 12.5, 0, 0),
+ F(50000000, P_XO, 1, 0, 0),
+ F(125000000, P_UNIPHY1_TX312P5M, 2.5, 0, 0),
+ F(312500000, P_UNIPHY1_TX312P5M, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_mac1_rx_clk_src = {
+ .cmd_rcgr = 0x60,
+ .freq_tbl = ftbl_nss_cc_mac1_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = nss_cc_uniphy1_tx312p5m_prx_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac1_rx_clk_src",
+ .parent_data = nss_cc_uniphy1_tx312p5m_prx_data,
+ .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_prx_data),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac1_rx_div_clk_src = {
+ .reg = 0x68,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac1_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac1_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac1_srds1_ch0_xgmii_tx_div_clk_src = {
+ .reg = 0x6c,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac1_srds1_ch0_xgmii_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac1_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac1_srds1_ch0_tx_clk = {
+ .halt_reg = 0x70,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x70,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac1_srds1_ch0_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac1_rx_clk = {
+ .halt_reg = 0x74,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x74,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac1_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac1_gephy0_rx_clk = {
+ .halt_reg = 0x78,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x78,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac1_gephy0_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac1_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac1_srds1_ch0_xgmii_tx_clk = {
+ .halt_reg = 0x7c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac1_srds1_ch0_xgmii_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac1_srds1_ch0_xgmii_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_cc_mac2_tx_clk_src = {
+ .cmd_rcgr = 0x80,
+ .freq_tbl = ftbl_nss_cc_mac1_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = nss_cc_uniphy1_rx_tx312p5m_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac2_tx_clk_src",
+ .parent_data = nss_cc_uniphy1_rx_tx312p5m_data,
+ .num_parents = ARRAY_SIZE(nss_cc_uniphy1_rx_tx312p5m_data),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac2_tx_div_clk_src = {
+ .reg = 0x88,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac2_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac2_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac2_srds1_ch1_xgmii_rx_div_clk_src = {
+ .reg = 0x8c,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac2_srds1_ch1_xgmii_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac2_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac2_srds1_ch1_rx_clk = {
+ .halt_reg = 0x90,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x90,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac2_srds1_ch1_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac2_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac2_tx_clk = {
+ .halt_reg = 0x94,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x94,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac2_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac2_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac2_gephy1_tx_clk = {
+ .halt_reg = 0x98,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x98,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac2_gephy1_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac2_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac2_srds1_ch1_xgmii_rx_clk = {
+ .halt_reg = 0x9c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac2_srds1_ch1_xgmii_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac2_srds1_ch1_xgmii_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_cc_mac2_rx_clk_src = {
+ .cmd_rcgr = 0xa0,
+ .freq_tbl = ftbl_nss_cc_mac1_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = nss_cc_uniphy1_tx312p5m_prx_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac2_rx_clk_src",
+ .parent_data = nss_cc_uniphy1_tx312p5m_prx_data,
+ .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_prx_data),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac2_rx_div_clk_src = {
+ .reg = 0xa8,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac2_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac2_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac2_srds1_ch1_xgmii_tx_div_clk_src = {
+ .reg = 0xac,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac2_srds1_ch1_xgmii_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac2_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac2_srds1_ch1_tx_clk = {
+ .halt_reg = 0xb0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac2_srds1_ch1_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac2_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac2_rx_clk = {
+ .halt_reg = 0xb4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac2_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac2_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac2_gephy1_rx_clk = {
+ .halt_reg = 0xb8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xb8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac2_gephy1_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac2_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac2_srds1_ch1_xgmii_tx_clk = {
+ .halt_reg = 0xbc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xbc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac2_srds1_ch1_xgmii_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac2_srds1_ch1_xgmii_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_cc_mac3_tx_clk_src = {
+ .cmd_rcgr = 0xc0,
+ .freq_tbl = ftbl_nss_cc_mac1_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = nss_cc_uniphy1_rx_tx312p5m_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac3_tx_clk_src",
+ .parent_data = nss_cc_uniphy1_rx_tx312p5m_data,
+ .num_parents = ARRAY_SIZE(nss_cc_uniphy1_rx_tx312p5m_data),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac3_tx_div_clk_src = {
+ .reg = 0xc8,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac3_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac3_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac3_srds1_ch2_xgmii_rx_div_clk_src = {
+ .reg = 0xcc,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac3_srds1_ch2_xgmii_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac3_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac3_srds1_ch2_rx_clk = {
+ .halt_reg = 0xd0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xd0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac3_srds1_ch2_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac3_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac3_tx_clk = {
+ .halt_reg = 0xd4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xd4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac3_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac3_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac3_gephy2_tx_clk = {
+ .halt_reg = 0xd8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xd8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac3_gephy2_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac3_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac3_srds1_ch2_xgmii_rx_clk = {
+ .halt_reg = 0xdc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xdc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac3_srds1_ch2_xgmii_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac3_srds1_ch2_xgmii_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_cc_mac3_rx_clk_src = {
+ .cmd_rcgr = 0xe0,
+ .freq_tbl = ftbl_nss_cc_mac1_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = nss_cc_uniphy1_tx312p5m_prx_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac3_rx_clk_src",
+ .parent_data = nss_cc_uniphy1_tx312p5m_prx_data,
+ .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_prx_data),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac3_rx_div_clk_src = {
+ .reg = 0xe8,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac3_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac3_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac3_srds1_ch2_xgmii_tx_div_clk_src = {
+ .reg = 0xec,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac3_srds1_ch2_xgmii_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac3_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac3_srds1_ch2_tx_clk = {
+ .halt_reg = 0xf0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac3_srds1_ch2_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac3_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac3_rx_clk = {
+ .halt_reg = 0xf4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac3_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac3_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac3_gephy2_rx_clk = {
+ .halt_reg = 0xf8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac3_gephy2_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac3_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac3_srds1_ch2_xgmii_tx_clk = {
+ .halt_reg = 0xfc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xfc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac3_srds1_ch2_xgmii_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac3_srds1_ch2_xgmii_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static const struct clk_parent_data nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_data[] = {
+ { .index = DT_XO },
+ { .index = DT_UNIPHY1_TX312P5M_CLK },
+ { .index = DT_UNIPHY1_RX312P5M_CLK },
+};
+
+static const struct parent_map nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY1_TX312P5M, 3 },
+ { P_UNIPHY1_RX312P5M, 7 },
+};
+
+static const struct freq_tbl ftbl_nss_cc_mac4_tx_clk_src[] = {
+ F(25000000, P_UNIPHY1_TX312P5M, 12.5, 0, 0),
+ F(25000000, P_UNIPHY1_RX312P5M, 12.5, 0, 0),
+ F(50000000, P_XO, 1, 0, 0),
+ F(125000000, P_UNIPHY1_TX312P5M, 2.5, 0, 0),
+ F(125000000, P_UNIPHY1_RX312P5M, 2.5, 0, 0),
+ F(312500000, P_UNIPHY1_TX312P5M, 1, 0, 0),
+ F(312500000, P_UNIPHY1_RX312P5M, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_mac4_tx_clk_src = {
+ .cmd_rcgr = 0x100,
+ .freq_tbl = ftbl_nss_cc_mac4_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac4_tx_clk_src",
+ .parent_data = nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_data,
+ .num_parents = ARRAY_SIZE(nss_cc_uniphy0_rx_uniphy1_rx_tx312p5m_data),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac4_tx_div_clk_src = {
+ .reg = 0x108,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac4_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac4_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac4_srds1_ch3_xgmii_rx_div_clk_src = {
+ .reg = 0x10c,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac4_srds1_ch3_xgmii_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac4_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac4_srds1_ch3_rx_clk = {
+ .halt_reg = 0x110,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x110,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac4_srds1_ch3_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac4_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac4_tx_clk = {
+ .halt_reg = 0x114,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x114,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac4_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac4_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac4_gephy3_tx_clk = {
+ .halt_reg = 0x118,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x118,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac4_gephy3_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac4_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac4_srds1_ch3_xgmii_rx_clk = {
+ .halt_reg = 0x11c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x11c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac4_srds1_ch3_xgmii_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac4_srds1_ch3_xgmii_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static const struct clk_parent_data nss_cc_uniphy0_tx_uniphy1_tx312p5m_data[] = {
+ { .index = DT_XO },
+ { .index = DT_UNIPHY1_TX312P5M_CLK },
+};
+
+static const struct parent_map nss_cc_uniphy0_tx_uniphy1_tx312p5m_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY1_TX312P5M, 3 },
+};
+
+static const struct freq_tbl ftbl_nss_cc_mac4_rx_clk_src[] = {
+ F(25000000, P_UNIPHY1_TX312P5M, 12.5, 0, 0),
+ F(50000000, P_XO, 1, 0, 0),
+ F(125000000, P_UNIPHY1_TX312P5M, 2.5, 0, 0),
+ F(312500000, P_UNIPHY1_TX312P5M, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_mac4_rx_clk_src = {
+ .cmd_rcgr = 0x120,
+ .freq_tbl = ftbl_nss_cc_mac4_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = nss_cc_uniphy0_tx_uniphy1_tx312p5m_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac4_rx_clk_src",
+ .parent_data = nss_cc_uniphy0_tx_uniphy1_tx312p5m_data,
+ .num_parents = ARRAY_SIZE(nss_cc_uniphy0_tx_uniphy1_tx312p5m_data),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac4_rx_div_clk_src = {
+ .reg = 0x128,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac4_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac4_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac4_srds1_ch3_xgmii_tx_div_clk_src = {
+ .reg = 0x12c,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac4_srds1_ch3_xgmii_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac4_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac4_srds1_ch3_tx_clk = {
+ .halt_reg = 0x130,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x130,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac4_srds1_ch3_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac4_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac4_rx_clk = {
+ .halt_reg = 0x134,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x134,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac4_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac4_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac4_gephy3_rx_clk = {
+ .halt_reg = 0x138,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x138,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac4_gephy3_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac4_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac4_srds1_ch3_xgmii_tx_clk = {
+ .halt_reg = 0x13c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x13c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac4_srds1_ch3_xgmii_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac4_srds1_ch3_xgmii_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static const struct clk_parent_data nss_cc_uniphy0_tx_data[] = {
+ { .index = DT_XO },
+ { .index = DT_UNIPHY0_TX_CLK },
+};
+
+static const struct parent_map nss_cc_uniphy0_tx_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_TX, 2 },
+};
+
+static struct clk_rcg2 nss_cc_mac5_tx_clk_src = {
+ .cmd_rcgr = 0x140,
+ .hid_width = 5,
+ .parent_map = nss_cc_uniphy0_tx_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac5_tx_clk_src",
+ .parent_data = nss_cc_uniphy0_tx_data,
+ .num_parents = ARRAY_SIZE(nss_cc_uniphy0_tx_data),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_mux_closest_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac5_tx_div_clk_src = {
+ .reg = 0x148,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac5_tx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac5_tx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac5_tx_clk = {
+ .halt_reg = 0x14c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac5_tx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac5_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static const struct clk_parent_data nss_cc_uniphy0_rx_tx_data[] = {
+ { .index = DT_XO },
+ { .index = DT_UNIPHY0_RX_CLK },
+ { .index = DT_UNIPHY0_TX_CLK },
+};
+
+static const struct parent_map nss_cc_uniphy0_rx_tx_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_RX, 1 },
+ { P_UNIPHY0_TX, 2 },
+};
+
+static struct clk_rcg2 nss_cc_mac5_rx_clk_src = {
+ .cmd_rcgr = 0x154,
+ .hid_width = 5,
+ .parent_map = nss_cc_uniphy0_rx_tx_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac5_rx_clk_src",
+ .parent_data = nss_cc_uniphy0_rx_tx_data,
+ .num_parents = ARRAY_SIZE(nss_cc_uniphy0_rx_tx_data),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_mux_closest_ops,
+ },
+};
+
+static struct clk_regmap_div nss_cc_mac5_rx_div_clk_src = {
+ .reg = 0x15c,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac5_rx_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac5_rx_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac5_rx_clk = {
+ .halt_reg = 0x160,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x160,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac5_rx_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac5_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static const struct parent_map nss_cc_mac4_rx_div_mac5_tx_div_map[] = {
+ { P_MAC4_RX_DIV, 0 },
+ { P_MAC5_TX_DIV, 1 },
+};
+
+static struct clk_regmap_mux nss_cc_mac5_tx_srds0_clk_src = {
+ .reg = 0x300,
+ .shift = 0,
+ .width = 1,
+ .parent_map = nss_cc_mac4_rx_div_mac5_tx_div_map,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac5_tx_srds0_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac4_rx_div_clk_src.clkr.hw,
+ &nss_cc_mac5_tx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_mux_closest_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac5_tx_srds0_clk = {
+ .halt_reg = 0x150,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x150,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac5_tx_srds0_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac5_tx_srds0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static const struct parent_map nss_cc_mac4_tx_div_mac5_rx_div_map[] = {
+ { P_MAC4_TX_DIV, 0 },
+ { P_MAC5_RX_DIV, 1 },
+};
+
+static struct clk_regmap_mux nss_cc_mac5_rx_srds0_clk_src = {
+ .reg = 0x300,
+ .shift = 1,
+ .width = 1,
+ .parent_map = nss_cc_mac4_tx_div_mac5_rx_div_map,
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac5_rx_srds0_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac4_tx_div_clk_src.clkr.hw,
+ &nss_cc_mac5_rx_div_clk_src.clkr.hw,
+ },
+ .num_parents = 2,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_mux_closest_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mac5_rx_srds0_clk = {
+ .halt_reg = 0x164,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x164,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mac5_rx_srds0_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_mac5_rx_srds0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static const struct parent_map nss_cc_uniphy1_tx312p5m_map2[] = {
+ { P_XO, 0 },
+ { P_UNIPHY1_TX312P5M, 2 },
+};
+
+static const struct freq_tbl ftbl_nss_cc_ahb_clk_src[] = {
+ F(50000000, P_XO, 1, 0, 0),
+ F(104170000, P_UNIPHY1_TX312P5M, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_ahb_clk_src = {
+ .cmd_rcgr = 0x168,
+ .freq_tbl = ftbl_nss_cc_ahb_clk_src,
+ .hid_width = 5,
+ .parent_map = nss_cc_uniphy1_tx312p5m_map2,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ahb_clk_src",
+ .parent_data = nss_cc_uniphy1_tx312p5m_data,
+ .num_parents = ARRAY_SIZE(nss_cc_uniphy1_tx312p5m_data),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch nss_cc_ahb_clk = {
+ .halt_reg = 0x170,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x170,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_sec_ctrl_ahb_clk = {
+ .halt_reg = 0x174,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x174,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_sec_ctrl_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_tlmm_clk = {
+ .halt_reg = 0x178,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x178,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_tlmm_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_tlmm_ahb_clk = {
+ .halt_reg = 0x190,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x190,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_tlmm_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_cnoc_ahb_clk = {
+ .halt_reg = 0x194,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x194,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_cnoc_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mdio_ahb_clk = {
+ .halt_reg = 0x198,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x198,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mdio_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_mdio_master_ahb_clk = {
+ .halt_reg = 0x19c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x19c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_mdio_master_ahb_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static const struct clk_parent_data nss_cc_xo_data[] = {
+ { .index = DT_XO },
+};
+
+static const struct parent_map nss_cc_xo_map[] = {
+ { P_XO, 0 },
+};
+
+static const struct freq_tbl ftbl_nss_cc_sys_clk_src[] = {
+ F(25000000, P_XO, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_cc_sys_clk_src = {
+ .cmd_rcgr = 0x1a0,
+ .freq_tbl = ftbl_nss_cc_sys_clk_src,
+ .hid_width = 5,
+ .parent_map = nss_cc_xo_map,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_sys_clk_src",
+ .parent_data = nss_cc_xo_data,
+ .num_parents = ARRAY_SIZE(nss_cc_xo_data),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch nss_cc_srds0_sys_clk = {
+ .halt_reg = 0x1a8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1a8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_srds0_sys_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_sys_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_srds1_sys_clk = {
+ .halt_reg = 0x1ac,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1ac,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_srds1_sys_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_sys_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_gephy0_sys_clk = {
+ .halt_reg = 0x1b0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1b0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_gephy0_sys_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_sys_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_gephy1_sys_clk = {
+ .halt_reg = 0x1b4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1b4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_gephy1_sys_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_sys_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_gephy2_sys_clk = {
+ .halt_reg = 0x1b8,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1b8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_gephy2_sys_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_sys_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_branch nss_cc_gephy3_sys_clk = {
+ .halt_reg = 0x1bc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "nss_cc_gephy3_sys_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &nss_cc_sys_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_prepare_ops,
+ },
+ },
+};
+
+static struct clk_regmap *nss_cc_qca8k_clocks[] = {
+ [NSS_CC_SWITCH_CORE_CLK_SRC] = &nss_cc_switch_core_clk_src.clkr,
+ [NSS_CC_SWITCH_CORE_CLK] = &nss_cc_switch_core_clk.clkr,
+ [NSS_CC_APB_BRIDGE_CLK] = &nss_cc_apb_bridge_clk.clkr,
+ [NSS_CC_MAC0_TX_CLK_SRC] = &nss_cc_mac0_tx_clk_src.clkr,
+ [NSS_CC_MAC0_TX_DIV_CLK_SRC] = &nss_cc_mac0_tx_div_clk_src.clkr,
+ [NSS_CC_MAC0_TX_CLK] = &nss_cc_mac0_tx_clk.clkr,
+ [NSS_CC_MAC0_TX_SRDS1_CLK] = &nss_cc_mac0_tx_srds1_clk.clkr,
+ [NSS_CC_MAC0_RX_CLK_SRC] = &nss_cc_mac0_rx_clk_src.clkr,
+ [NSS_CC_MAC0_RX_DIV_CLK_SRC] = &nss_cc_mac0_rx_div_clk_src.clkr,
+ [NSS_CC_MAC0_RX_CLK] = &nss_cc_mac0_rx_clk.clkr,
+ [NSS_CC_MAC0_RX_SRDS1_CLK] = &nss_cc_mac0_rx_srds1_clk.clkr,
+ [NSS_CC_MAC1_TX_CLK_SRC] = &nss_cc_mac1_tx_clk_src.clkr,
+ [NSS_CC_MAC1_TX_DIV_CLK_SRC] = &nss_cc_mac1_tx_div_clk_src.clkr,
+ [NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_DIV_CLK_SRC] =
+ &nss_cc_mac1_srds1_ch0_xgmii_rx_div_clk_src.clkr,
+ [NSS_CC_MAC1_SRDS1_CH0_RX_CLK] = &nss_cc_mac1_srds1_ch0_rx_clk.clkr,
+ [NSS_CC_MAC1_TX_CLK] = &nss_cc_mac1_tx_clk.clkr,
+ [NSS_CC_MAC1_GEPHY0_TX_CLK] = &nss_cc_mac1_gephy0_tx_clk.clkr,
+ [NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_CLK] = &nss_cc_mac1_srds1_ch0_xgmii_rx_clk.clkr,
+ [NSS_CC_MAC1_RX_CLK_SRC] = &nss_cc_mac1_rx_clk_src.clkr,
+ [NSS_CC_MAC1_RX_DIV_CLK_SRC] = &nss_cc_mac1_rx_div_clk_src.clkr,
+ [NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_DIV_CLK_SRC] =
+ &nss_cc_mac1_srds1_ch0_xgmii_tx_div_clk_src.clkr,
+ [NSS_CC_MAC1_SRDS1_CH0_TX_CLK] = &nss_cc_mac1_srds1_ch0_tx_clk.clkr,
+ [NSS_CC_MAC1_RX_CLK] = &nss_cc_mac1_rx_clk.clkr,
+ [NSS_CC_MAC1_GEPHY0_RX_CLK] = &nss_cc_mac1_gephy0_rx_clk.clkr,
+ [NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_CLK] = &nss_cc_mac1_srds1_ch0_xgmii_tx_clk.clkr,
+ [NSS_CC_MAC2_TX_CLK_SRC] = &nss_cc_mac2_tx_clk_src.clkr,
+ [NSS_CC_MAC2_TX_DIV_CLK_SRC] = &nss_cc_mac2_tx_div_clk_src.clkr,
+ [NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_DIV_CLK_SRC] =
+ &nss_cc_mac2_srds1_ch1_xgmii_rx_div_clk_src.clkr,
+ [NSS_CC_MAC2_SRDS1_CH1_RX_CLK] = &nss_cc_mac2_srds1_ch1_rx_clk.clkr,
+ [NSS_CC_MAC2_TX_CLK] = &nss_cc_mac2_tx_clk.clkr,
+ [NSS_CC_MAC2_GEPHY1_TX_CLK] = &nss_cc_mac2_gephy1_tx_clk.clkr,
+ [NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_CLK] = &nss_cc_mac2_srds1_ch1_xgmii_rx_clk.clkr,
+ [NSS_CC_MAC2_RX_CLK_SRC] = &nss_cc_mac2_rx_clk_src.clkr,
+ [NSS_CC_MAC2_RX_DIV_CLK_SRC] = &nss_cc_mac2_rx_div_clk_src.clkr,
+ [NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_DIV_CLK_SRC] =
+ &nss_cc_mac2_srds1_ch1_xgmii_tx_div_clk_src.clkr,
+ [NSS_CC_MAC2_SRDS1_CH1_TX_CLK] = &nss_cc_mac2_srds1_ch1_tx_clk.clkr,
+ [NSS_CC_MAC2_RX_CLK] = &nss_cc_mac2_rx_clk.clkr,
+ [NSS_CC_MAC2_GEPHY1_RX_CLK] = &nss_cc_mac2_gephy1_rx_clk.clkr,
+ [NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_CLK] = &nss_cc_mac2_srds1_ch1_xgmii_tx_clk.clkr,
+ [NSS_CC_MAC3_TX_CLK_SRC] = &nss_cc_mac3_tx_clk_src.clkr,
+ [NSS_CC_MAC3_TX_DIV_CLK_SRC] = &nss_cc_mac3_tx_div_clk_src.clkr,
+ [NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC] =
+ &nss_cc_mac3_srds1_ch2_xgmii_rx_div_clk_src.clkr,
+ [NSS_CC_MAC3_SRDS1_CH2_RX_CLK] = &nss_cc_mac3_srds1_ch2_rx_clk.clkr,
+ [NSS_CC_MAC3_TX_CLK] = &nss_cc_mac3_tx_clk.clkr,
+ [NSS_CC_MAC3_GEPHY2_TX_CLK] = &nss_cc_mac3_gephy2_tx_clk.clkr,
+ [NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_CLK] = &nss_cc_mac3_srds1_ch2_xgmii_rx_clk.clkr,
+ [NSS_CC_MAC3_RX_CLK_SRC] = &nss_cc_mac3_rx_clk_src.clkr,
+ [NSS_CC_MAC3_RX_DIV_CLK_SRC] = &nss_cc_mac3_rx_div_clk_src.clkr,
+ [NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC] =
+ &nss_cc_mac3_srds1_ch2_xgmii_tx_div_clk_src.clkr,
+ [NSS_CC_MAC3_SRDS1_CH2_TX_CLK] = &nss_cc_mac3_srds1_ch2_tx_clk.clkr,
+ [NSS_CC_MAC3_RX_CLK] = &nss_cc_mac3_rx_clk.clkr,
+ [NSS_CC_MAC3_GEPHY2_RX_CLK] = &nss_cc_mac3_gephy2_rx_clk.clkr,
+ [NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_CLK] = &nss_cc_mac3_srds1_ch2_xgmii_tx_clk.clkr,
+ [NSS_CC_MAC4_TX_CLK_SRC] = &nss_cc_mac4_tx_clk_src.clkr,
+ [NSS_CC_MAC4_TX_DIV_CLK_SRC] = &nss_cc_mac4_tx_div_clk_src.clkr,
+ [NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_DIV_CLK_SRC] =
+ &nss_cc_mac4_srds1_ch3_xgmii_rx_div_clk_src.clkr,
+ [NSS_CC_MAC4_SRDS1_CH3_RX_CLK] = &nss_cc_mac4_srds1_ch3_rx_clk.clkr,
+ [NSS_CC_MAC4_TX_CLK] = &nss_cc_mac4_tx_clk.clkr,
+ [NSS_CC_MAC4_GEPHY3_TX_CLK] = &nss_cc_mac4_gephy3_tx_clk.clkr,
+ [NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_CLK] = &nss_cc_mac4_srds1_ch3_xgmii_rx_clk.clkr,
+ [NSS_CC_MAC4_RX_CLK_SRC] = &nss_cc_mac4_rx_clk_src.clkr,
+ [NSS_CC_MAC4_RX_DIV_CLK_SRC] = &nss_cc_mac4_rx_div_clk_src.clkr,
+ [NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_DIV_CLK_SRC] =
+ &nss_cc_mac4_srds1_ch3_xgmii_tx_div_clk_src.clkr,
+ [NSS_CC_MAC4_SRDS1_CH3_TX_CLK] = &nss_cc_mac4_srds1_ch3_tx_clk.clkr,
+ [NSS_CC_MAC4_RX_CLK] = &nss_cc_mac4_rx_clk.clkr,
+ [NSS_CC_MAC4_GEPHY3_RX_CLK] = &nss_cc_mac4_gephy3_rx_clk.clkr,
+ [NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_CLK] = &nss_cc_mac4_srds1_ch3_xgmii_tx_clk.clkr,
+ [NSS_CC_MAC5_TX_CLK_SRC] = &nss_cc_mac5_tx_clk_src.clkr,
+ [NSS_CC_MAC5_TX_DIV_CLK_SRC] = &nss_cc_mac5_tx_div_clk_src.clkr,
+ [NSS_CC_MAC5_TX_SRDS0_CLK] = &nss_cc_mac5_tx_srds0_clk.clkr,
+ [NSS_CC_MAC5_TX_CLK] = &nss_cc_mac5_tx_clk.clkr,
+ [NSS_CC_MAC5_RX_CLK_SRC] = &nss_cc_mac5_rx_clk_src.clkr,
+ [NSS_CC_MAC5_RX_DIV_CLK_SRC] = &nss_cc_mac5_rx_div_clk_src.clkr,
+ [NSS_CC_MAC5_RX_SRDS0_CLK] = &nss_cc_mac5_rx_srds0_clk.clkr,
+ [NSS_CC_MAC5_RX_CLK] = &nss_cc_mac5_rx_clk.clkr,
+ [NSS_CC_MAC5_TX_SRDS0_CLK_SRC] = &nss_cc_mac5_tx_srds0_clk_src.clkr,
+ [NSS_CC_MAC5_RX_SRDS0_CLK_SRC] = &nss_cc_mac5_rx_srds0_clk_src.clkr,
+ [NSS_CC_AHB_CLK_SRC] = &nss_cc_ahb_clk_src.clkr,
+ [NSS_CC_AHB_CLK] = &nss_cc_ahb_clk.clkr,
+ [NSS_CC_SEC_CTRL_AHB_CLK] = &nss_cc_sec_ctrl_ahb_clk.clkr,
+ [NSS_CC_TLMM_CLK] = &nss_cc_tlmm_clk.clkr,
+ [NSS_CC_TLMM_AHB_CLK] = &nss_cc_tlmm_ahb_clk.clkr,
+ [NSS_CC_CNOC_AHB_CLK] = &nss_cc_cnoc_ahb_clk.clkr,
+ [NSS_CC_MDIO_AHB_CLK] = &nss_cc_mdio_ahb_clk.clkr,
+ [NSS_CC_MDIO_MASTER_AHB_CLK] = &nss_cc_mdio_master_ahb_clk.clkr,
+ [NSS_CC_SYS_CLK_SRC] = &nss_cc_sys_clk_src.clkr,
+ [NSS_CC_SRDS0_SYS_CLK] = &nss_cc_srds0_sys_clk.clkr,
+ [NSS_CC_SRDS1_SYS_CLK] = &nss_cc_srds1_sys_clk.clkr,
+ [NSS_CC_GEPHY0_SYS_CLK] = &nss_cc_gephy0_sys_clk.clkr,
+ [NSS_CC_GEPHY1_SYS_CLK] = &nss_cc_gephy1_sys_clk.clkr,
+ [NSS_CC_GEPHY2_SYS_CLK] = &nss_cc_gephy2_sys_clk.clkr,
+ [NSS_CC_GEPHY3_SYS_CLK] = &nss_cc_gephy3_sys_clk.clkr,
+};
+
+static const struct qcom_reset_map nss_cc_qca8k_resets[] = {
+ [NSS_CC_SWITCH_CORE_ARES] = { 0xc, 2 },
+ [NSS_CC_APB_BRIDGE_ARES] = { 0x10, 2 },
+ [NSS_CC_MAC0_TX_ARES] = { 0x20, 2 },
+ [NSS_CC_MAC0_TX_SRDS1_ARES] = { 0x24, 2 },
+ [NSS_CC_MAC0_RX_ARES] = { 0x34, 2 },
+ [NSS_CC_MAC0_RX_SRDS1_ARES] = { 0x3c, 2 },
+ [NSS_CC_MAC1_SRDS1_CH0_RX_ARES] = { 0x50, 2 },
+ [NSS_CC_MAC1_TX_ARES] = { 0x54, 2 },
+ [NSS_CC_MAC1_GEPHY0_TX_ARES] = { 0x58, 2 },
+ [NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES] = { 0x5c, 2 },
+ [NSS_CC_MAC1_SRDS1_CH0_TX_ARES] = { 0x70, 2 },
+ [NSS_CC_MAC1_RX_ARES] = { 0x74, 2 },
+ [NSS_CC_MAC1_GEPHY0_RX_ARES] = { 0x78, 2 },
+ [NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES] = { 0x7c, 2 },
+ [NSS_CC_MAC2_SRDS1_CH1_RX_ARES] = { 0x90, 2 },
+ [NSS_CC_MAC2_TX_ARES] = { 0x94, 2 },
+ [NSS_CC_MAC2_GEPHY1_TX_ARES] = { 0x98, 2 },
+ [NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES] = { 0x9c, 2 },
+ [NSS_CC_MAC2_SRDS1_CH1_TX_ARES] = { 0xb0, 2 },
+ [NSS_CC_MAC2_RX_ARES] = { 0xb4, 2 },
+ [NSS_CC_MAC2_GEPHY1_RX_ARES] = { 0xb8, 2 },
+ [NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES] = { 0xbc, 2 },
+ [NSS_CC_MAC3_SRDS1_CH2_RX_ARES] = { 0xd0, 2 },
+ [NSS_CC_MAC3_TX_ARES] = { 0xd4, 2 },
+ [NSS_CC_MAC3_GEPHY2_TX_ARES] = { 0xd8, 2 },
+ [NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES] = { 0xdc, 2 },
+ [NSS_CC_MAC3_SRDS1_CH2_TX_ARES] = { 0xf0, 2 },
+ [NSS_CC_MAC3_RX_ARES] = { 0xf4, 2 },
+ [NSS_CC_MAC3_GEPHY2_RX_ARES] = { 0xf8, 2 },
+ [NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES] = { 0xfc, 2 },
+ [NSS_CC_MAC4_SRDS1_CH3_RX_ARES] = { 0x110, 2 },
+ [NSS_CC_MAC4_TX_ARES] = { 0x114, 2 },
+ [NSS_CC_MAC4_GEPHY3_TX_ARES] = { 0x118, 2 },
+ [NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES] = { 0x11c, 2 },
+ [NSS_CC_MAC4_SRDS1_CH3_TX_ARES] = { 0x130, 2 },
+ [NSS_CC_MAC4_RX_ARES] = { 0x134, 2 },
+ [NSS_CC_MAC4_GEPHY3_RX_ARES] = { 0x138, 2 },
+ [NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES] = { 0x13c, 2 },
+ [NSS_CC_MAC5_TX_ARES] = { 0x14c, 2 },
+ [NSS_CC_MAC5_TX_SRDS0_ARES] = { 0x150, 2 },
+ [NSS_CC_MAC5_RX_ARES] = { 0x160, 2 },
+ [NSS_CC_MAC5_RX_SRDS0_ARES] = { 0x164, 2 },
+ [NSS_CC_AHB_ARES] = { 0x170, 2 },
+ [NSS_CC_SEC_CTRL_AHB_ARES] = { 0x174, 2 },
+ [NSS_CC_TLMM_ARES] = { 0x178, 2 },
+ [NSS_CC_TLMM_AHB_ARES] = { 0x190, 2 },
+ [NSS_CC_CNOC_AHB_ARES] = { 0x194, 2 }, /* reset CNOC AHB & APB */
+ [NSS_CC_MDIO_AHB_ARES] = { 0x198, 2 },
+ [NSS_CC_MDIO_MASTER_AHB_ARES] = { 0x19c, 2 },
+ [NSS_CC_SRDS0_SYS_ARES] = { 0x1a8, 2 },
+ [NSS_CC_SRDS1_SYS_ARES] = { 0x1ac, 2 },
+ [NSS_CC_GEPHY0_SYS_ARES] = { 0x1b0, 2 },
+ [NSS_CC_GEPHY1_SYS_ARES] = { 0x1b4, 2 },
+ [NSS_CC_GEPHY2_SYS_ARES] = { 0x1b8, 2 },
+ [NSS_CC_GEPHY3_SYS_ARES] = { 0x1bc, 2 },
+ [NSS_CC_SEC_CTRL_ARES] = { 0x1c8, 2 },
+ [NSS_CC_SEC_CTRL_SENSE_ARES] = { 0x1d0, 2 },
+ [NSS_CC_SLEEP_ARES] = { 0x1e0, 2 },
+ [NSS_CC_DEBUG_ARES] = { 0x1e8, 2 },
+ [NSS_CC_GEPHY0_ARES] = { 0x304, 0 },
+ [NSS_CC_GEPHY1_ARES] = { 0x304, 1 },
+ [NSS_CC_GEPHY2_ARES] = { 0x304, 2 },
+ [NSS_CC_GEPHY3_ARES] = { 0x304, 3 },
+ [NSS_CC_DSP_ARES] = { 0x304, 4 },
+ [NSS_CC_GLOBAL_ARES] = { 0x308, 0 },
+ [NSS_CC_XPCS_ARES] = { 0x30c, 0 },
+};
+
+/* For each read/write operation of clock register, there are three MDIO frames
+ * sent to the device.
+ *
+ * 1. The high address part[23:8] of register is packaged into the first MDIO frame
+ * for selecting page.
+ * 2. The low address part[7:0] of register is packaged into the second MDIO frame
+ * with the low 16bit data to read/write.
+ * 3. The low address part[7:0] of register is packaged into the last MDIO frame
+ * with the high 16bit data to read/write.
+ *
+ * The clause22 MDIO frame format used by device is as below.
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | ST| OP| ADDR | REG | TA| DATA |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+static inline void convert_reg_to_mii_addr(u32 regaddr, u16 *reg, u16 *phy_addr, u16 *page)
+{
+ *reg = FIELD_GET(QCA8K_CLK_REG_MASK, regaddr);
+ *phy_addr = FIELD_GET(QCA8K_CLK_PHY_ADDR_MASK, regaddr) | QCA8K_LOW_ADDR_PREFIX;
+ *page = FIELD_GET(QCA8K_CLK_PAGE_MASK, regaddr);
+}
+
+static int qca8k_mii_read(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u32 *val)
+{
+ int ret, data;
+
+ ret = __mdiobus_read(bus, switch_phy_id, reg);
+ if (ret >= 0) {
+ data = ret;
+
+ ret = __mdiobus_read(bus, switch_phy_id, (reg | QCA8K_REG_DATA_UPPER_16_BITS));
+ if (ret >= 0)
+ *val = data | ret << 16;
+ }
+
+ if (ret < 0)
+ dev_err_ratelimited(&bus->dev, "fail to read qca8k mii register\n");
+
+ return ret < 0 ? ret : 0;
+}
+
+static void qca8k_mii_write(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u32 val)
+{
+ int ret;
+
+ ret = __mdiobus_write(bus, switch_phy_id, reg, lower_16_bits(val));
+ if (ret >= 0)
+ ret = __mdiobus_write(bus, switch_phy_id, (reg | QCA8K_REG_DATA_UPPER_16_BITS),
+ upper_16_bits(val));
+
+ if (ret < 0)
+ dev_err_ratelimited(&bus->dev, "fail to write qca8k mii register\n");
+}
+
+static int qca8k_mii_page_set(struct mii_bus *bus, u16 switch_phy_id, u32 reg, u16 page)
+{
+ int ret;
+
+ ret = __mdiobus_write(bus, switch_phy_id, reg, page);
+ if (ret < 0)
+ dev_err_ratelimited(&bus->dev, "fail to set page\n");
+
+ return ret;
+}
+
+static int qca8k_regmap_read(void *context, unsigned int regaddr, unsigned int *val)
+{
+ struct mii_bus *bus = context;
+ u16 reg, phy_addr, page;
+ int ret;
+
+ regaddr += QCA8K_CLK_REG_BASE;
+ convert_reg_to_mii_addr(regaddr, ®, &phy_addr, &page);
+
+ mutex_lock(&bus->mdio_lock);
+ ret = qca8k_mii_page_set(bus, QCA8K_HIGH_ADDR_PREFIX, QCA8K_CFG_PAGE_REG, page);
+ if (ret < 0)
+ goto qca8k_read_exit;
+
+ ret = qca8k_mii_read(bus, phy_addr, reg, val);
+
+qca8k_read_exit:
+ mutex_unlock(&bus->mdio_lock);
+ return ret;
+};
+
+static int qca8k_regmap_write(void *context, unsigned int regaddr, unsigned int val)
+{
+ struct mii_bus *bus = context;
+ u16 reg, phy_addr, page;
+ int ret;
+
+ regaddr += QCA8K_CLK_REG_BASE;
+ convert_reg_to_mii_addr(regaddr, ®, &phy_addr, &page);
+
+ mutex_lock(&bus->mdio_lock);
+ ret = qca8k_mii_page_set(bus, QCA8K_HIGH_ADDR_PREFIX, QCA8K_CFG_PAGE_REG, page);
+ if (ret < 0)
+ goto qca8k_write_exit;
+
+ qca8k_mii_write(bus, phy_addr, reg, val);
+
+qca8k_write_exit:
+ mutex_unlock(&bus->mdio_lock);
+ return ret;
+};
+
+static int qca8k_regmap_update_bits(void *context, unsigned int regaddr, unsigned int mask,
+ unsigned int value)
+{
+ struct mii_bus *bus = context;
+ u16 reg, phy_addr, page;
+ int ret;
+ u32 val;
+
+ regaddr += QCA8K_CLK_REG_BASE;
+ convert_reg_to_mii_addr(regaddr, ®, &phy_addr, &page);
+
+ mutex_lock(&bus->mdio_lock);
+ ret = qca8k_mii_page_set(bus, QCA8K_HIGH_ADDR_PREFIX, QCA8K_CFG_PAGE_REG, page);
+ if (ret < 0)
+ goto qca8k_update_exit;
+
+ ret = qca8k_mii_read(bus, phy_addr, reg, &val);
+ if (ret < 0)
+ goto qca8k_update_exit;
+
+ val &= ~mask;
+ val |= value;
+ qca8k_mii_write(bus, phy_addr, reg, val);
+
+qca8k_update_exit:
+ mutex_unlock(&bus->mdio_lock);
+ return ret;
+}
+
+static const struct regmap_config nss_cc_qca8k_regmap_config = {
+ .reg_bits = 12,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x30c,
+ .reg_read = qca8k_regmap_read,
+ .reg_write = qca8k_regmap_write,
+ .reg_update_bits = qca8k_regmap_update_bits,
+ .disable_locking = true,
+};
+
+static const struct qcom_cc_desc nss_cc_qca8k_desc = {
+ .config = &nss_cc_qca8k_regmap_config,
+ .clks = nss_cc_qca8k_clocks,
+ .num_clks = ARRAY_SIZE(nss_cc_qca8k_clocks),
+ .resets = nss_cc_qca8k_resets,
+ .num_resets = ARRAY_SIZE(nss_cc_qca8k_resets),
+};
+
+static int nss_cc_qca8k_probe(struct mdio_device *mdiodev)
+{
+ struct regmap *regmap;
+
+ regmap = devm_regmap_init(&mdiodev->dev, NULL, mdiodev->bus, nss_cc_qca8k_desc.config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(&mdiodev->dev, PTR_ERR(regmap), "Failed to init regmap\n");
+
+ return qcom_cc_really_probe(&mdiodev->dev, &nss_cc_qca8k_desc, regmap);
+}
+
+static const struct of_device_id nss_cc_qca8k_match_table[] = {
+ { .compatible = "qcom,qca8084-nsscc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, nss_cc_qca8k_match_table);
+
+static struct mdio_driver nss_cc_qca8k_driver = {
+ .mdiodrv.driver = {
+ .name = "qcom,qca8k-nsscc",
+ .of_match_table = nss_cc_qca8k_match_table,
+ },
+ .probe = nss_cc_qca8k_probe,
+};
+
+mdio_module_driver(nss_cc_qca8k_driver);
+
+MODULE_DESCRIPTION("QCOM NSS_CC QCA8K Driver");
+MODULE_LICENSE("GPL");
--
2.42.0
The previous wrapper qcom_cc_really_probe takes the platform
device as parameter, which is limited to platform driver.
As for qca8k clock controller driver, which is registered as
the MDIO device, which also follows the qcom clock framework.
To commonize qcom_cc_really_probe, updating it to take the
struct device as parameter, so that the qcom_cc_really_probe
can be utilized by the previous platform device and the new
added MDIO device.
Also update the current clock controller drivers to take
&pdev->dev as parameter when calling qcom_cc_really_probe.
Signed-off-by: Luo Jie <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Tested-by: Bryan O'Donoghue <[email protected]>
Reviewed-by: Bryan O'Donoghue <[email protected]>
---
v11->v12: update the parameter pdev to &pdev->dev of
qcom_cc_really_probe in gcc-sm4450.c and camcc-sm8550.c.
drivers/clk/qcom/apss-ipq6018.c | 2 +-
drivers/clk/qcom/camcc-sc7180.c | 2 +-
drivers/clk/qcom/camcc-sc7280.c | 2 +-
drivers/clk/qcom/camcc-sdm845.c | 2 +-
drivers/clk/qcom/camcc-sm6350.c | 2 +-
drivers/clk/qcom/camcc-sm8250.c | 2 +-
drivers/clk/qcom/camcc-sm8450.c | 2 +-
drivers/clk/qcom/camcc-sm8550.c | 2 +-
drivers/clk/qcom/common.c | 7 +++----
drivers/clk/qcom/common.h | 2 +-
drivers/clk/qcom/dispcc-qcm2290.c | 2 +-
drivers/clk/qcom/dispcc-sc7180.c | 2 +-
drivers/clk/qcom/dispcc-sc7280.c | 2 +-
drivers/clk/qcom/dispcc-sc8280xp.c | 2 +-
drivers/clk/qcom/dispcc-sdm845.c | 2 +-
drivers/clk/qcom/dispcc-sm6115.c | 2 +-
drivers/clk/qcom/dispcc-sm6125.c | 2 +-
drivers/clk/qcom/dispcc-sm6350.c | 2 +-
drivers/clk/qcom/dispcc-sm6375.c | 2 +-
drivers/clk/qcom/dispcc-sm8250.c | 2 +-
drivers/clk/qcom/dispcc-sm8450.c | 2 +-
drivers/clk/qcom/dispcc-sm8550.c | 2 +-
drivers/clk/qcom/gcc-ipq5018.c | 2 +-
drivers/clk/qcom/gcc-ipq6018.c | 2 +-
drivers/clk/qcom/gcc-ipq8074.c | 2 +-
drivers/clk/qcom/gcc-mdm9607.c | 2 +-
drivers/clk/qcom/gcc-mdm9615.c | 2 +-
drivers/clk/qcom/gcc-msm8917.c | 2 +-
drivers/clk/qcom/gcc-msm8939.c | 2 +-
drivers/clk/qcom/gcc-msm8953.c | 2 +-
drivers/clk/qcom/gcc-msm8976.c | 2 +-
drivers/clk/qcom/gcc-msm8996.c | 2 +-
drivers/clk/qcom/gcc-msm8998.c | 2 +-
drivers/clk/qcom/gcc-qcm2290.c | 2 +-
drivers/clk/qcom/gcc-qcs404.c | 2 +-
drivers/clk/qcom/gcc-qdu1000.c | 2 +-
drivers/clk/qcom/gcc-sa8775p.c | 2 +-
drivers/clk/qcom/gcc-sc7180.c | 2 +-
drivers/clk/qcom/gcc-sc7280.c | 2 +-
drivers/clk/qcom/gcc-sc8180x.c | 2 +-
drivers/clk/qcom/gcc-sc8280xp.c | 2 +-
drivers/clk/qcom/gcc-sdm660.c | 2 +-
drivers/clk/qcom/gcc-sdm845.c | 2 +-
drivers/clk/qcom/gcc-sdx55.c | 2 +-
drivers/clk/qcom/gcc-sdx65.c | 2 +-
drivers/clk/qcom/gcc-sdx75.c | 2 +-
drivers/clk/qcom/gcc-sm4450.c | 2 +-
drivers/clk/qcom/gcc-sm6115.c | 2 +-
drivers/clk/qcom/gcc-sm6125.c | 2 +-
drivers/clk/qcom/gcc-sm6350.c | 2 +-
drivers/clk/qcom/gcc-sm6375.c | 2 +-
drivers/clk/qcom/gcc-sm7150.c | 2 +-
drivers/clk/qcom/gcc-sm8150.c | 2 +-
drivers/clk/qcom/gcc-sm8250.c | 2 +-
drivers/clk/qcom/gcc-sm8350.c | 2 +-
drivers/clk/qcom/gcc-sm8450.c | 2 +-
drivers/clk/qcom/gcc-sm8550.c | 2 +-
drivers/clk/qcom/gpucc-msm8998.c | 2 +-
drivers/clk/qcom/gpucc-sa8775p.c | 2 +-
drivers/clk/qcom/gpucc-sc7180.c | 2 +-
drivers/clk/qcom/gpucc-sc7280.c | 2 +-
drivers/clk/qcom/gpucc-sc8280xp.c | 2 +-
drivers/clk/qcom/gpucc-sdm660.c | 2 +-
drivers/clk/qcom/gpucc-sdm845.c | 2 +-
drivers/clk/qcom/gpucc-sm6115.c | 2 +-
drivers/clk/qcom/gpucc-sm6125.c | 2 +-
drivers/clk/qcom/gpucc-sm6350.c | 2 +-
drivers/clk/qcom/gpucc-sm6375.c | 2 +-
drivers/clk/qcom/gpucc-sm8150.c | 2 +-
drivers/clk/qcom/gpucc-sm8250.c | 2 +-
drivers/clk/qcom/gpucc-sm8350.c | 2 +-
drivers/clk/qcom/gpucc-sm8450.c | 2 +-
drivers/clk/qcom/gpucc-sm8550.c | 2 +-
drivers/clk/qcom/lcc-ipq806x.c | 2 +-
drivers/clk/qcom/lcc-msm8960.c | 2 +-
drivers/clk/qcom/lpassaudiocc-sc7280.c | 4 ++--
drivers/clk/qcom/lpasscorecc-sc7180.c | 2 +-
drivers/clk/qcom/lpasscorecc-sc7280.c | 2 +-
drivers/clk/qcom/mmcc-msm8960.c | 2 +-
drivers/clk/qcom/mmcc-msm8974.c | 2 +-
drivers/clk/qcom/mmcc-msm8994.c | 2 +-
drivers/clk/qcom/mmcc-msm8996.c | 2 +-
drivers/clk/qcom/mmcc-msm8998.c | 2 +-
drivers/clk/qcom/mmcc-sdm660.c | 2 +-
drivers/clk/qcom/tcsrcc-sm8550.c | 2 +-
drivers/clk/qcom/videocc-sc7180.c | 2 +-
drivers/clk/qcom/videocc-sc7280.c | 2 +-
drivers/clk/qcom/videocc-sdm845.c | 2 +-
drivers/clk/qcom/videocc-sm8150.c | 2 +-
drivers/clk/qcom/videocc-sm8250.c | 2 +-
drivers/clk/qcom/videocc-sm8350.c | 2 +-
drivers/clk/qcom/videocc-sm8450.c | 2 +-
drivers/clk/qcom/videocc-sm8550.c | 2 +-
93 files changed, 96 insertions(+), 97 deletions(-)
diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
index e6295b832686..c89d126ebac3 100644
--- a/drivers/clk/qcom/apss-ipq6018.c
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -123,7 +123,7 @@ static int apss_ipq6018_probe(struct platform_device *pdev)
if (!regmap)
return -ENODEV;
- ret = qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &apss_ipq6018_desc, regmap);
if (ret)
return ret;
diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c
index 0a9a6df3ddac..4ab741c924b3 100644
--- a/drivers/clk/qcom/camcc-sc7180.c
+++ b/drivers/clk/qcom/camcc-sc7180.c
@@ -1680,7 +1680,7 @@ static int cam_cc_sc7180_probe(struct platform_device *pdev)
clk_agera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
- ret = qcom_cc_really_probe(pdev, &cam_cc_sc7180_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sc7180_desc, regmap);
pm_runtime_put(&pdev->dev);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to register CAM CC clocks\n");
diff --git a/drivers/clk/qcom/camcc-sc7280.c b/drivers/clk/qcom/camcc-sc7280.c
index 49f046ea857c..87f281269ba6 100644
--- a/drivers/clk/qcom/camcc-sc7280.c
+++ b/drivers/clk/qcom/camcc-sc7280.c
@@ -2457,7 +2457,7 @@ static int cam_cc_sc7280_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
clk_lucid_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
- return qcom_cc_really_probe(pdev, &cam_cc_sc7280_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &cam_cc_sc7280_desc, regmap);
}
static struct platform_driver cam_cc_sc7280_driver = {
diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c
index 27d44188a7ab..8ba095587ce8 100644
--- a/drivers/clk/qcom/camcc-sdm845.c
+++ b/drivers/clk/qcom/camcc-sdm845.c
@@ -1735,7 +1735,7 @@ static int cam_cc_sdm845_probe(struct platform_device *pdev)
cam_cc_pll_config.l = 0x14;
clk_fabia_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll_config);
- return qcom_cc_really_probe(pdev, &cam_cc_sdm845_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &cam_cc_sdm845_desc, regmap);
}
static struct platform_driver cam_cc_sdm845_driver = {
diff --git a/drivers/clk/qcom/camcc-sm6350.c b/drivers/clk/qcom/camcc-sm6350.c
index acba9f99d960..d52073a6e204 100644
--- a/drivers/clk/qcom/camcc-sm6350.c
+++ b/drivers/clk/qcom/camcc-sm6350.c
@@ -1879,7 +1879,7 @@ static int camcc_sm6350_probe(struct platform_device *pdev)
clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config);
clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config);
- return qcom_cc_really_probe(pdev, &camcc_sm6350_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &camcc_sm6350_desc, regmap);
}
static struct platform_driver camcc_sm6350_driver = {
diff --git a/drivers/clk/qcom/camcc-sm8250.c b/drivers/clk/qcom/camcc-sm8250.c
index 9b32c56a5bc5..6ac85b96a1ea 100644
--- a/drivers/clk/qcom/camcc-sm8250.c
+++ b/drivers/clk/qcom/camcc-sm8250.c
@@ -2433,7 +2433,7 @@ static int cam_cc_sm8250_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
- return qcom_cc_really_probe(pdev, &cam_cc_sm8250_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8250_desc, regmap);
}
static struct platform_driver cam_cc_sm8250_driver = {
diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c
index 51338a2884d2..26b78eed15ef 100644
--- a/drivers/clk/qcom/camcc-sm8450.c
+++ b/drivers/clk/qcom/camcc-sm8450.c
@@ -2839,7 +2839,7 @@ static int cam_cc_sm8450_probe(struct platform_device *pdev)
clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
- return qcom_cc_really_probe(pdev, &cam_cc_sm8450_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8450_desc, regmap);
}
static struct platform_driver cam_cc_sm8450_driver = {
diff --git a/drivers/clk/qcom/camcc-sm8550.c b/drivers/clk/qcom/camcc-sm8550.c
index dd51ba4ea757..69d095e087e1 100644
--- a/drivers/clk/qcom/camcc-sm8550.c
+++ b/drivers/clk/qcom/camcc-sm8550.c
@@ -3544,7 +3544,7 @@ static int cam_cc_sm8550_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x1419c, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x142cc, BIT(0), BIT(0));
- ret = qcom_cc_really_probe(pdev, &cam_cc_sm8550_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8550_desc, regmap);
pm_runtime_put(&pdev->dev);
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index 75f09e6e057e..e21fd7992237 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -234,11 +234,10 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL;
}
-int qcom_cc_really_probe(struct platform_device *pdev,
+int qcom_cc_really_probe(struct device *dev,
const struct qcom_cc_desc *desc, struct regmap *regmap)
{
int i, ret;
- struct device *dev = &pdev->dev;
struct qcom_reset_controller *reset;
struct qcom_cc *cc;
struct gdsc_desc *scd;
@@ -315,7 +314,7 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- return qcom_cc_really_probe(pdev, desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, desc, regmap);
}
EXPORT_SYMBOL_GPL(qcom_cc_probe);
@@ -333,7 +332,7 @@ int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- return qcom_cc_really_probe(pdev, desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, desc, regmap);
}
EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 9c8f7b798d9f..e168a81a40e3 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -58,7 +58,7 @@ extern int qcom_cc_register_sleep_clk(struct device *dev);
extern struct regmap *qcom_cc_map(struct platform_device *pdev,
const struct qcom_cc_desc *desc);
-extern int qcom_cc_really_probe(struct platform_device *pdev,
+extern int qcom_cc_really_probe(struct device *dev,
const struct qcom_cc_desc *desc,
struct regmap *regmap);
extern int qcom_cc_probe(struct platform_device *pdev,
diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
index 9206f0eed446..bfbbf2bdd27a 100644
--- a/drivers/clk/qcom/dispcc-qcm2290.c
+++ b/drivers/clk/qcom/dispcc-qcm2290.c
@@ -522,7 +522,7 @@ static int disp_cc_qcm2290_probe(struct platform_device *pdev)
/* Keep DISP_CC_XO_CLK always-ON */
regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0));
- ret = qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_qcm2290_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
return ret;
diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c
index 9536bfc72a43..644dd6241c9b 100644
--- a/drivers/clk/qcom/dispcc-sc7180.c
+++ b/drivers/clk/qcom/dispcc-sc7180.c
@@ -713,7 +713,7 @@ static int disp_cc_sc7180_probe(struct platform_device *pdev)
clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config);
- return qcom_cc_really_probe(pdev, &disp_cc_sc7180_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &disp_cc_sc7180_desc, regmap);
}
static struct platform_driver disp_cc_sc7180_driver = {
diff --git a/drivers/clk/qcom/dispcc-sc7280.c b/drivers/clk/qcom/dispcc-sc7280.c
index ad596d567f6a..decb231cd135 100644
--- a/drivers/clk/qcom/dispcc-sc7280.c
+++ b/drivers/clk/qcom/dispcc-sc7280.c
@@ -884,7 +884,7 @@ static int disp_cc_sc7280_probe(struct platform_device *pdev)
*/
regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0));
- return qcom_cc_really_probe(pdev, &disp_cc_sc7280_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &disp_cc_sc7280_desc, regmap);
}
static struct platform_driver disp_cc_sc7280_driver = {
diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-sc8280xp.c
index 30f636b9f0ec..789dd5ea977e 100644
--- a/drivers/clk/qcom/dispcc-sc8280xp.c
+++ b/drivers/clk/qcom/dispcc-sc8280xp.c
@@ -3172,7 +3172,7 @@ static int disp_cc_sc8280xp_probe(struct platform_device *pdev)
clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL1]), regmap, &disp_cc_pll1_config);
clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL2]), regmap, &disp_cc_pll2_config);
- ret = qcom_cc_really_probe(pdev, desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register display clock controller\n");
goto out_pm_runtime_put;
diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
index 735adfefc379..633119a5c51d 100644
--- a/drivers/clk/qcom/dispcc-sdm845.c
+++ b/drivers/clk/qcom/dispcc-sdm845.c
@@ -861,7 +861,7 @@ static int disp_cc_sdm845_probe(struct platform_device *pdev)
/* Enable hardware clock gating for DSI and MDP clocks */
regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0);
- return qcom_cc_really_probe(pdev, &disp_cc_sdm845_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &disp_cc_sdm845_desc, regmap);
}
static struct platform_driver disp_cc_sdm845_driver = {
diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6115.c
index 1fab43f08e73..14f8743631a9 100644
--- a/drivers/clk/qcom/dispcc-sm6115.c
+++ b/drivers/clk/qcom/dispcc-sm6115.c
@@ -586,7 +586,7 @@ static int disp_cc_sm6115_probe(struct platform_device *pdev)
/* Keep DISP_CC_XO_CLK always-ON */
regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0));
- ret = qcom_cc_really_probe(pdev, &disp_cc_sm6115_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6115_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
return ret;
diff --git a/drivers/clk/qcom/dispcc-sm6125.c b/drivers/clk/qcom/dispcc-sm6125.c
index 87b27053ddb6..f9ef300146a7 100644
--- a/drivers/clk/qcom/dispcc-sm6125.c
+++ b/drivers/clk/qcom/dispcc-sm6125.c
@@ -682,7 +682,7 @@ static int disp_cc_sm6125_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
- return qcom_cc_really_probe(pdev, &disp_cc_sm6125_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6125_desc, regmap);
}
static struct platform_driver disp_cc_sm6125_driver = {
diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6350.c
index ea6f54ed846e..ff6e320a9c26 100644
--- a/drivers/clk/qcom/dispcc-sm6350.c
+++ b/drivers/clk/qcom/dispcc-sm6350.c
@@ -770,7 +770,7 @@ static int disp_cc_sm6350_probe(struct platform_device *pdev)
clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
- return qcom_cc_really_probe(pdev, &disp_cc_sm6350_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6350_desc, regmap);
}
static struct platform_driver disp_cc_sm6350_driver = {
diff --git a/drivers/clk/qcom/dispcc-sm6375.c b/drivers/clk/qcom/dispcc-sm6375.c
index caa1b90a5ff2..1ab189fe9d42 100644
--- a/drivers/clk/qcom/dispcc-sm6375.c
+++ b/drivers/clk/qcom/dispcc-sm6375.c
@@ -583,7 +583,7 @@ static int disp_cc_sm6375_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
- return qcom_cc_really_probe(pdev, &disp_cc_sm6375_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &disp_cc_sm6375_desc, regmap);
}
static struct platform_driver disp_cc_sm6375_driver = {
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
index e17bb8b543b5..fc46cb3ffa62 100644
--- a/drivers/clk/qcom/dispcc-sm8250.c
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -1368,7 +1368,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
/* DISP_CC_XO_CLK always-on */
regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0));
- ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8250_desc, regmap);
pm_runtime_put(&pdev->dev);
diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c
index 2c4aecd75186..691f56696ce2 100644
--- a/drivers/clk/qcom/dispcc-sm8450.c
+++ b/drivers/clk/qcom/dispcc-sm8450.c
@@ -1793,7 +1793,7 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev)
*/
regmap_update_bits(regmap, 0xe05c, BIT(0), BIT(0));
- ret = qcom_cc_really_probe(pdev, &disp_cc_sm8450_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8450_desc, regmap);
if (ret)
goto err_put_rpm;
diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c
index aefa19f3c2c5..82763a6884e2 100644
--- a/drivers/clk/qcom/dispcc-sm8550.c
+++ b/drivers/clk/qcom/dispcc-sm8550.c
@@ -1778,7 +1778,7 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev)
*/
regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0));
- ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8550_desc, regmap);
if (ret)
goto err_put_rpm;
diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c
index 4aba47e8700d..81408f894af7 100644
--- a/drivers/clk/qcom/gcc-ipq5018.c
+++ b/drivers/clk/qcom/gcc-ipq5018.c
@@ -3695,7 +3695,7 @@ static int gcc_ipq5018_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
- return qcom_cc_really_probe(pdev, &ipq5018_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &ipq5018_desc, regmap);
}
static struct platform_driver gcc_ipq5018_driver = {
diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
index b366912cd648..fc628b7154c3 100644
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -4623,7 +4623,7 @@ static int gcc_ipq6018_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
&nss_crypto_pll_config);
- return qcom_cc_really_probe(pdev, &gcc_ipq6018_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_ipq6018_desc, regmap);
}
static struct platform_driver gcc_ipq6018_driver = {
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index b7faf12a511a..03d82bbeb342 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4726,7 +4726,7 @@ static int gcc_ipq8074_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
&nss_crypto_pll_config);
- return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_ipq8074_desc, regmap);
}
static struct platform_driver gcc_ipq8074_driver = {
diff --git a/drivers/clk/qcom/gcc-mdm9607.c b/drivers/clk/qcom/gcc-mdm9607.c
index fb290e73ce94..6e6068b168e6 100644
--- a/drivers/clk/qcom/gcc-mdm9607.c
+++ b/drivers/clk/qcom/gcc-mdm9607.c
@@ -1604,7 +1604,7 @@ static int gcc_mdm9607_probe(struct platform_device *pdev)
/* Vote for GPLL0 to turn on. Needed by acpuclock. */
regmap_update_bits(regmap, 0x45000, BIT(0), BIT(0));
- return qcom_cc_really_probe(pdev, &gcc_mdm9607_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_mdm9607_desc, regmap);
}
static struct platform_driver gcc_mdm9607_driver = {
diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
index aec7c4a1d3de..33987b957737 100644
--- a/drivers/clk/qcom/gcc-mdm9615.c
+++ b/drivers/clk/qcom/gcc-mdm9615.c
@@ -1736,7 +1736,7 @@ static int gcc_mdm9615_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- return qcom_cc_really_probe(pdev, &gcc_mdm9615_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_mdm9615_desc, regmap);
}
static struct platform_driver gcc_mdm9615_driver = {
diff --git a/drivers/clk/qcom/gcc-msm8917.c b/drivers/clk/qcom/gcc-msm8917.c
index f2dd132e2fb1..503fa342c39a 100644
--- a/drivers/clk/qcom/gcc-msm8917.c
+++ b/drivers/clk/qcom/gcc-msm8917.c
@@ -3270,7 +3270,7 @@ static int gcc_msm8917_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&gpll3_early, regmap, &gpll3_early_config);
- return qcom_cc_really_probe(pdev, gcc_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, gcc_desc, regmap);
}
static const struct of_device_id gcc_msm8917_match_table[] = {
diff --git a/drivers/clk/qcom/gcc-msm8939.c b/drivers/clk/qcom/gcc-msm8939.c
index b45f97c07eeb..deee4c560d4f 100644
--- a/drivers/clk/qcom/gcc-msm8939.c
+++ b/drivers/clk/qcom/gcc-msm8939.c
@@ -4004,7 +4004,7 @@ static int gcc_msm8939_probe(struct platform_device *pdev)
clk_pll_configure_sr_hpm_lp(&gpll3, regmap, &gpll3_config, true);
clk_pll_configure_sr_hpm_lp(&gpll4, regmap, &gpll4_config, true);
- return qcom_cc_really_probe(pdev, &gcc_msm8939_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_msm8939_desc, regmap);
}
static struct platform_driver gcc_msm8939_driver = {
diff --git a/drivers/clk/qcom/gcc-msm8953.c b/drivers/clk/qcom/gcc-msm8953.c
index 3e5a8cb14d4d..a4893c01ce47 100644
--- a/drivers/clk/qcom/gcc-msm8953.c
+++ b/drivers/clk/qcom/gcc-msm8953.c
@@ -4216,7 +4216,7 @@ static int gcc_msm8953_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&gpll3_early, regmap, &gpll3_early_config);
- return qcom_cc_really_probe(pdev, &gcc_msm8953_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_msm8953_desc, regmap);
}
static const struct of_device_id gcc_msm8953_match_table[] = {
diff --git a/drivers/clk/qcom/gcc-msm8976.c b/drivers/clk/qcom/gcc-msm8976.c
index f60a8171972b..dfc343357ed0 100644
--- a/drivers/clk/qcom/gcc-msm8976.c
+++ b/drivers/clk/qcom/gcc-msm8976.c
@@ -4129,7 +4129,7 @@ static int gcc_msm8976_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_msm8976_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_msm8976_desc, regmap);
}
static struct platform_driver gcc_msm8976_driver = {
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index e7b03a17514a..4fc667b94cf2 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -3620,7 +3620,7 @@ static int gcc_msm8996_probe(struct platform_device *pdev)
*/
regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
- return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_msm8996_desc, regmap);
}
static struct platform_driver gcc_msm8996_driver = {
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index cad7f1c7789c..434ba6e21af1 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -3292,7 +3292,7 @@ static int gcc_msm8998_probe(struct platform_device *pdev)
regmap_write(regmap, GCC_MMSS_MISC, 0x10003);
regmap_write(regmap, GCC_GPU_MISC, 0x10003);
- return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_msm8998_desc, regmap);
}
static const struct of_device_id gcc_msm8998_match_table[] = {
diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c
index 48995e50c6bd..9a6703365e61 100644
--- a/drivers/clk/qcom/gcc-qcm2290.c
+++ b/drivers/clk/qcom/gcc-qcm2290.c
@@ -2994,7 +2994,7 @@ static int gcc_qcm2290_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&gpll8, regmap, &gpll8_config);
clk_alpha_pll_configure(&gpll9, regmap, &gpll9_config);
- return qcom_cc_really_probe(pdev, &gcc_qcm2290_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_qcm2290_desc, regmap);
}
static struct platform_driver gcc_qcm2290_driver = {
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index a39c4990b29d..c3cfd572e7c1 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -2824,7 +2824,7 @@ static int gcc_qcs404_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config);
- return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_qcs404_desc, regmap);
}
static struct platform_driver gcc_qcs404_driver = {
diff --git a/drivers/clk/qcom/gcc-qdu1000.c b/drivers/clk/qcom/gcc-qdu1000.c
index 9f42d2601464..dbe9e9437939 100644
--- a/drivers/clk/qcom/gcc-qdu1000.c
+++ b/drivers/clk/qcom/gcc-qdu1000.c
@@ -2674,7 +2674,7 @@ static int gcc_qdu1000_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = qcom_cc_really_probe(pdev, &gcc_qdu1000_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &gcc_qdu1000_desc, regmap);
if (ret)
return dev_err_probe(&pdev->dev, ret, "Failed to register GCC clocks\n");
diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c
index 8171d23c96e6..2b9283b325a4 100644
--- a/drivers/clk/qcom/gcc-sa8775p.c
+++ b/drivers/clk/qcom/gcc-sa8775p.c
@@ -4758,7 +4758,7 @@ static int gcc_sa8775p_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0));
- return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sa8775p_desc, regmap);
}
static struct platform_driver gcc_sa8775p_driver = {
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index a3406aadbd17..c33d1ef15b2a 100644
--- a/drivers/clk/qcom/gcc-sc7180.c
+++ b/drivers/clk/qcom/gcc-sc7180.c
@@ -2462,7 +2462,7 @@ static int gcc_sc7180_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sc7180_desc, regmap);
}
static struct platform_driver gcc_sc7180_driver = {
diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
index 2b661df5de26..3ace431ade6c 100644
--- a/drivers/clk/qcom/gcc-sc7280.c
+++ b/drivers/clk/qcom/gcc-sc7280.c
@@ -3472,7 +3472,7 @@ static int gcc_sc7280_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sc7280_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sc7280_desc, regmap);
}
static struct platform_driver gcc_sc7280_driver = {
diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c
index ae2147381559..0c82b6a16a45 100644
--- a/drivers/clk/qcom/gcc-sc8180x.c
+++ b/drivers/clk/qcom/gcc-sc8180x.c
@@ -4601,7 +4601,7 @@ static int gcc_sc8180x_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
- return qcom_cc_really_probe(pdev, &gcc_sc8180x_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sc8180x_desc, regmap);
}
static struct platform_driver gcc_sc8180x_driver = {
diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c
index bfb77931e868..03cbd485a8c5 100644
--- a/drivers/clk/qcom/gcc-sc8280xp.c
+++ b/drivers/clk/qcom/gcc-sc8280xp.c
@@ -7563,7 +7563,7 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev)
if (ret)
goto err_put_rpm;
- ret = qcom_cc_really_probe(pdev, &gcc_sc8280xp_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &gcc_sc8280xp_desc, regmap);
if (ret)
goto err_put_rpm;
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
index c4fe70871b6d..df79298a1a25 100644
--- a/drivers/clk/qcom/gcc-sdm660.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -2474,7 +2474,7 @@ static int gcc_sdm660_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sdm660_desc, regmap);
}
static struct platform_driver gcc_sdm660_driver = {
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 725cd52d2398..7c9122d761db 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -4011,7 +4011,7 @@ static int gcc_sdm845_probe(struct platform_device *pdev)
return ret;
gcc_desc = of_device_get_match_data(&pdev->dev);
- return qcom_cc_really_probe(pdev, gcc_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, gcc_desc, regmap);
}
static struct platform_driver gcc_sdm845_driver = {
diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c
index d5e17122698c..2b7a24b07119 100644
--- a/drivers/clk/qcom/gcc-sdx55.c
+++ b/drivers/clk/qcom/gcc-sdx55.c
@@ -1620,7 +1620,7 @@ static int gcc_sdx55_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21));
regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22));
- return qcom_cc_really_probe(pdev, &gcc_sdx55_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sdx55_desc, regmap);
}
static struct platform_driver gcc_sdx55_driver = {
diff --git a/drivers/clk/qcom/gcc-sdx65.c b/drivers/clk/qcom/gcc-sdx65.c
index ffddbed5a6db..a2e44c617a70 100644
--- a/drivers/clk/qcom/gcc-sdx65.c
+++ b/drivers/clk/qcom/gcc-sdx65.c
@@ -1583,7 +1583,7 @@ static int gcc_sdx65_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21));
regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22));
- return qcom_cc_really_probe(pdev, &gcc_sdx65_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sdx65_desc, regmap);
}
static struct platform_driver gcc_sdx65_driver = {
diff --git a/drivers/clk/qcom/gcc-sdx75.c b/drivers/clk/qcom/gcc-sdx75.c
index 573af17bd24c..2c395b93348e 100644
--- a/drivers/clk/qcom/gcc-sdx75.c
+++ b/drivers/clk/qcom/gcc-sdx75.c
@@ -2944,7 +2944,7 @@ static int gcc_sdx75_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x3e004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x3e008, BIT(0), BIT(0));
- return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sdx75_desc, regmap);
}
static struct platform_driver gcc_sdx75_driver = {
diff --git a/drivers/clk/qcom/gcc-sm4450.c b/drivers/clk/qcom/gcc-sm4450.c
index 31abe2775fc8..bb719ccf1147 100644
--- a/drivers/clk/qcom/gcc-sm4450.c
+++ b/drivers/clk/qcom/gcc-sm4450.c
@@ -2871,7 +2871,7 @@ static int gcc_sm4450_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21));
- return qcom_cc_really_probe(pdev, &gcc_sm4450_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm4450_desc, regmap);
}
static struct platform_driver gcc_sm4450_driver = {
diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c
index 13e521cd4259..f71752a50d03 100644
--- a/drivers/clk/qcom/gcc-sm6115.c
+++ b/drivers/clk/qcom/gcc-sm6115.c
@@ -3513,7 +3513,7 @@ static int gcc_sm6115_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&gpll10, regmap, &gpll10_config);
clk_alpha_pll_configure(&gpll11, regmap, &gpll11_config);
- return qcom_cc_really_probe(pdev, &gcc_sm6115_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm6115_desc, regmap);
}
static struct platform_driver gcc_sm6115_driver = {
diff --git a/drivers/clk/qcom/gcc-sm6125.c b/drivers/clk/qcom/gcc-sm6125.c
index da554efee2ce..07bb1e5c4a30 100644
--- a/drivers/clk/qcom/gcc-sm6125.c
+++ b/drivers/clk/qcom/gcc-sm6125.c
@@ -4161,7 +4161,7 @@ static int gcc_sm6125_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sm6125_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm6125_desc, regmap);
}
static struct platform_driver gcc_sm6125_driver = {
diff --git a/drivers/clk/qcom/gcc-sm6350.c b/drivers/clk/qcom/gcc-sm6350.c
index cf4a7b6e0b23..0dcc8eeb77e6 100644
--- a/drivers/clk/qcom/gcc-sm6350.c
+++ b/drivers/clk/qcom/gcc-sm6350.c
@@ -2559,7 +2559,7 @@ static int gcc_sm6350_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sm6350_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm6350_desc, regmap);
}
static struct platform_driver gcc_sm6350_driver = {
diff --git a/drivers/clk/qcom/gcc-sm6375.c b/drivers/clk/qcom/gcc-sm6375.c
index 3dd15d765b22..061494cced5a 100644
--- a/drivers/clk/qcom/gcc-sm6375.c
+++ b/drivers/clk/qcom/gcc-sm6375.c
@@ -3895,7 +3895,7 @@ static int gcc_sm6375_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&gpll8, regmap, &gpll8_config);
clk_zonda_pll_configure(&gpll9, regmap, &gpll9_config);
- return qcom_cc_really_probe(pdev, &gcc_sm6375_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm6375_desc, regmap);
}
static struct platform_driver gcc_sm6375_driver = {
diff --git a/drivers/clk/qcom/gcc-sm7150.c b/drivers/clk/qcom/gcc-sm7150.c
index d9983bb27475..d8a6f91060a4 100644
--- a/drivers/clk/qcom/gcc-sm7150.c
+++ b/drivers/clk/qcom/gcc-sm7150.c
@@ -3022,7 +3022,7 @@ static int gcc_sm7150_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sm7150_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm7150_desc, regmap);
}
static struct platform_driver gcc_sm7150_driver = {
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index 05d115c52dfe..cecab33fa0b1 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -3786,7 +3786,7 @@ static int gcc_sm8150_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
- return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm8150_desc, regmap);
}
static struct platform_driver gcc_sm8150_driver = {
diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c
index c6c5261264f1..80c69a6a8dac 100644
--- a/drivers/clk/qcom/gcc-sm8250.c
+++ b/drivers/clk/qcom/gcc-sm8250.c
@@ -3661,7 +3661,7 @@ static int gcc_sm8250_probe(struct platform_device *pdev)
if (ret)
return ret;
- return qcom_cc_really_probe(pdev, &gcc_sm8250_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm8250_desc, regmap);
}
static struct platform_driver gcc_sm8250_driver = {
diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
index 1385a98eb3bb..84de2db61cc3 100644
--- a/drivers/clk/qcom/gcc-sm8350.c
+++ b/drivers/clk/qcom/gcc-sm8350.c
@@ -3826,7 +3826,7 @@ static int gcc_sm8350_probe(struct platform_device *pdev)
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
- return qcom_cc_really_probe(pdev, &gcc_sm8350_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm8350_desc, regmap);
}
static struct platform_driver gcc_sm8350_driver = {
diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c
index 563542982551..554ce87e4224 100644
--- a/drivers/clk/qcom/gcc-sm8450.c
+++ b/drivers/clk/qcom/gcc-sm8450.c
@@ -3294,7 +3294,7 @@ static int gcc_sm8450_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0));
- return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm8450_desc, regmap);
}
static struct platform_driver gcc_sm8450_driver = {
diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c
index 586126c4dd90..ad9567619c9e 100644
--- a/drivers/clk/qcom/gcc-sm8550.c
+++ b/drivers/clk/qcom/gcc-sm8550.c
@@ -3361,7 +3361,7 @@ static int gcc_sm8550_probe(struct platform_device *pdev)
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
regmap_write(regmap, 0x52024, 0x0);
- return qcom_cc_really_probe(pdev, &gcc_sm8550_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gcc_sm8550_desc, regmap);
}
static struct platform_driver gcc_sm8550_driver = {
diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c
index 9a4fdff719ec..617a2e97a320 100644
--- a/drivers/clk/qcom/gpucc-msm8998.c
+++ b/drivers/clk/qcom/gpucc-msm8998.c
@@ -334,7 +334,7 @@ static int gpucc_msm8998_probe(struct platform_device *pdev)
/* tweak droop detector (GPUCC_GPU_DD_WRAP_CTRL) to reduce leakage */
regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0));
- return qcom_cc_really_probe(pdev, &gpucc_msm8998_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpucc_msm8998_desc, regmap);
}
static struct platform_driver gpucc_msm8998_driver = {
diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
index 26ecfa63be19..8954aef6f2ba 100644
--- a/drivers/clk/qcom/gpucc-sa8775p.c
+++ b/drivers/clk/qcom/gpucc-sa8775p.c
@@ -598,7 +598,7 @@ static int gpu_cc_sa8775p_probe(struct platform_device *pdev)
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
- return qcom_cc_really_probe(pdev, &gpu_cc_sa8775p_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sa8775p_desc, regmap);
}
static struct platform_driver gpu_cc_sa8775p_driver = {
diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c
index 3f92f0b43be6..03b48767cf4d 100644
--- a/drivers/clk/qcom/gpucc-sc7180.c
+++ b/drivers/clk/qcom/gpucc-sc7180.c
@@ -241,7 +241,7 @@ static int gpu_cc_sc7180_probe(struct platform_device *pdev)
value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
regmap_update_bits(regmap, 0x1098, mask, value);
- return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sc7180_desc, regmap);
}
static struct platform_driver gpu_cc_sc7180_driver = {
diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c
index 1490cd45a654..71ea731223c8 100644
--- a/drivers/clk/qcom/gpucc-sc7280.c
+++ b/drivers/clk/qcom/gpucc-sc7280.c
@@ -465,7 +465,7 @@ static int gpu_cc_sc7280_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x1098, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x1098, BIT(13), BIT(13));
- return qcom_cc_really_probe(pdev, &gpu_cc_sc7280_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sc7280_desc, regmap);
}
static struct platform_driver gpu_cc_sc7280_driver = {
diff --git a/drivers/clk/qcom/gpucc-sc8280xp.c b/drivers/clk/qcom/gpucc-sc8280xp.c
index 8e147ee294ee..3ec2437e8586 100644
--- a/drivers/clk/qcom/gpucc-sc8280xp.c
+++ b/drivers/clk/qcom/gpucc-sc8280xp.c
@@ -451,7 +451,7 @@ static int gpu_cc_sc8280xp_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0));
- ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &gpu_cc_sc8280xp_desc, regmap);
pm_runtime_put(&pdev->dev);
return ret;
diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c
index 459f123a6720..611edf6d9ee2 100644
--- a/drivers/clk/qcom/gpucc-sdm660.c
+++ b/drivers/clk/qcom/gpucc-sdm660.c
@@ -330,7 +330,7 @@ static int gpucc_sdm660_probe(struct platform_device *pdev)
gpu_pll_config.alpha_hi = 0x8a;
clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, &gpu_pll_config);
- return qcom_cc_really_probe(pdev, &gpucc_sdm660_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpucc_sdm660_desc, regmap);
}
static struct platform_driver gpucc_sdm660_driver = {
diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c
index 970d7414bdf0..8658f692fcea 100644
--- a/drivers/clk/qcom/gpucc-sdm845.c
+++ b/drivers/clk/qcom/gpucc-sdm845.c
@@ -192,7 +192,7 @@ static int gpu_cc_sdm845_probe(struct platform_device *pdev)
value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
regmap_update_bits(regmap, 0x1098, mask, value);
- return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sdm845_desc, regmap);
}
static struct platform_driver gpu_cc_sdm845_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm6115.c b/drivers/clk/qcom/gpucc-sm6115.c
index fb71c21c9a89..6ccbc93c5340 100644
--- a/drivers/clk/qcom/gpucc-sm6115.c
+++ b/drivers/clk/qcom/gpucc-sm6115.c
@@ -488,7 +488,7 @@ static int gpu_cc_sm6115_probe(struct platform_device *pdev)
qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true);
qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm6115_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm6115_desc, regmap);
}
static struct platform_driver gpu_cc_sm6115_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm6125.c b/drivers/clk/qcom/gpucc-sm6125.c
index 61959ba02f9a..aba3f802071b 100644
--- a/drivers/clk/qcom/gpucc-sm6125.c
+++ b/drivers/clk/qcom/gpucc-sm6125.c
@@ -409,7 +409,7 @@ static int gpu_cc_sm6125_probe(struct platform_device *pdev)
qcom_branch_set_force_mem_core(regmap, gpu_cc_gx_gfx3d_clk, true);
qcom_branch_set_force_periph_on(regmap, gpu_cc_gx_gfx3d_clk, true);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm6125_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm6125_desc, regmap);
}
static struct platform_driver gpu_cc_sm6125_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm6350.c b/drivers/clk/qcom/gpucc-sm6350.c
index 0bcbba2a2943..1e12ad8948db 100644
--- a/drivers/clk/qcom/gpucc-sm6350.c
+++ b/drivers/clk/qcom/gpucc-sm6350.c
@@ -502,7 +502,7 @@ static int gpu_cc_sm6350_probe(struct platform_device *pdev)
value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
regmap_update_bits(regmap, 0x1098, mask, value);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm6350_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm6350_desc, regmap);
}
static struct platform_driver gpu_cc_sm6350_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm6375.c b/drivers/clk/qcom/gpucc-sm6375.c
index da24276a018e..d8e0c1bbeedc 100644
--- a/drivers/clk/qcom/gpucc-sm6375.c
+++ b/drivers/clk/qcom/gpucc-sm6375.c
@@ -455,7 +455,7 @@ static int gpucc_sm6375_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&gpucc_pll0, regmap, &gpucc_pll0_config);
clk_lucid_pll_configure(&gpucc_pll1, regmap, &gpucc_pll1_config);
- ret = qcom_cc_really_probe(pdev, &gpucc_sm6375_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &gpucc_sm6375_desc, regmap);
pm_runtime_put(&pdev->dev);
return ret;
diff --git a/drivers/clk/qcom/gpucc-sm8150.c b/drivers/clk/qcom/gpucc-sm8150.c
index 8422fd047493..1aefe5c224b8 100644
--- a/drivers/clk/qcom/gpucc-sm8150.c
+++ b/drivers/clk/qcom/gpucc-sm8150.c
@@ -304,7 +304,7 @@ static int gpu_cc_sm8150_probe(struct platform_device *pdev)
clk_trion_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm8150_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8150_desc, regmap);
}
static struct platform_driver gpu_cc_sm8150_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm8250.c b/drivers/clk/qcom/gpucc-sm8250.c
index 9c1f8ce32da4..1bdd1a8ac53f 100644
--- a/drivers/clk/qcom/gpucc-sm8250.c
+++ b/drivers/clk/qcom/gpucc-sm8250.c
@@ -320,7 +320,7 @@ static int gpu_cc_sm8250_probe(struct platform_device *pdev)
value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
regmap_update_bits(regmap, 0x1098, mask, value);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm8250_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8250_desc, regmap);
}
static struct platform_driver gpu_cc_sm8250_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c
index 8dc54dff983f..0269e9fc26b7 100644
--- a/drivers/clk/qcom/gpucc-sm8350.c
+++ b/drivers/clk/qcom/gpucc-sm8350.c
@@ -604,7 +604,7 @@ static int gpu_cc_sm8350_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8350_desc, regmap);
}
static const struct of_device_id gpu_cc_sm8350_match_table[] = {
diff --git a/drivers/clk/qcom/gpucc-sm8450.c b/drivers/clk/qcom/gpucc-sm8450.c
index 1c4769b646b0..9d8734569c93 100644
--- a/drivers/clk/qcom/gpucc-sm8450.c
+++ b/drivers/clk/qcom/gpucc-sm8450.c
@@ -751,7 +751,7 @@ static int gpu_cc_sm8450_probe(struct platform_device *pdev)
clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
- return qcom_cc_really_probe(pdev, &gpu_cc_sm8450_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8450_desc, regmap);
}
static struct platform_driver gpu_cc_sm8450_driver = {
diff --git a/drivers/clk/qcom/gpucc-sm8550.c b/drivers/clk/qcom/gpucc-sm8550.c
index 420dcb27b47d..7b12006c9cbc 100644
--- a/drivers/clk/qcom/gpucc-sm8550.c
+++ b/drivers/clk/qcom/gpucc-sm8550.c
@@ -583,7 +583,7 @@ static int gpu_cc_sm8550_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0));
- return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm8550_desc, regmap);
}
static struct platform_driver gpu_cc_sm8550_driver = {
diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c
index fa8cda63cf20..bf5320a43e8c 100644
--- a/drivers/clk/qcom/lcc-ipq806x.c
+++ b/drivers/clk/qcom/lcc-ipq806x.c
@@ -454,7 +454,7 @@ static int lcc_ipq806x_probe(struct platform_device *pdev)
/* Enable PLL4 source on the LPASS Primary PLL Mux */
regmap_write(regmap, 0xc4, 0x1);
- return qcom_cc_really_probe(pdev, &lcc_ipq806x_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &lcc_ipq806x_desc, regmap);
}
static struct platform_driver lcc_ipq806x_driver = {
diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c
index e725e7b9c456..d53bf315e9c3 100644
--- a/drivers/clk/qcom/lcc-msm8960.c
+++ b/drivers/clk/qcom/lcc-msm8960.c
@@ -481,7 +481,7 @@ static int lcc_msm8960_probe(struct platform_device *pdev)
/* Enable PLL4 source on the LPASS Primary PLL Mux */
regmap_write(regmap, 0xc4, 0x1);
- return qcom_cc_really_probe(pdev, &lcc_msm8960_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &lcc_msm8960_desc, regmap);
}
static struct platform_driver lcc_msm8960_driver = {
diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
index c43d0b1af7f7..45e726477086 100644
--- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
+++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
@@ -772,7 +772,7 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
regmap_write(regmap, 0x4, 0x3b);
regmap_write(regmap, 0x8, 0xff05);
- ret = qcom_cc_really_probe(pdev, &lpass_audio_cc_sc7280_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &lpass_audio_cc_sc7280_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC clocks\n");
goto exit;
@@ -847,7 +847,7 @@ static int lpass_aon_cc_sc7280_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&lpass_aon_cc_pll, regmap, &lpass_aon_cc_pll_config);
- ret = qcom_cc_really_probe(pdev, &lpass_aon_cc_sc7280_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &lpass_aon_cc_sc7280_desc, regmap);
if (ret) {
dev_err(&pdev->dev, "Failed to register LPASS AON CC clocks\n");
goto exit;
diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c b/drivers/clk/qcom/lpasscorecc-sc7180.c
index 9051fd567112..2e2e32959ec3 100644
--- a/drivers/clk/qcom/lpasscorecc-sc7180.c
+++ b/drivers/clk/qcom/lpasscorecc-sc7180.c
@@ -414,7 +414,7 @@ static int lpass_core_cc_sc7180_probe(struct platform_device *pdev)
clk_fabia_pll_configure(&lpass_lpaaudio_dig_pll, regmap,
&lpass_lpaaudio_dig_pll_config);
- ret = qcom_cc_really_probe(pdev, &lpass_core_cc_sc7180_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &lpass_core_cc_sc7180_desc, regmap);
pm_runtime_mark_last_busy(&pdev->dev);
exit:
diff --git a/drivers/clk/qcom/lpasscorecc-sc7280.c b/drivers/clk/qcom/lpasscorecc-sc7280.c
index a2f1e6ad6da4..b0888cd2460b 100644
--- a/drivers/clk/qcom/lpasscorecc-sc7280.c
+++ b/drivers/clk/qcom/lpasscorecc-sc7280.c
@@ -406,7 +406,7 @@ static int lpass_core_cc_sc7280_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&lpass_core_cc_dig_pll, regmap, &lpass_core_cc_dig_pll_config);
- return qcom_cc_really_probe(pdev, &lpass_core_cc_sc7280_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &lpass_core_cc_sc7280_desc, regmap);
}
static struct platform_driver lpass_core_cc_sc7280_driver = {
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index 50638ab341ec..1061322534c4 100644
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -3122,7 +3122,7 @@ static int mmcc_msm8960_probe(struct platform_device *pdev)
clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
- return qcom_cc_really_probe(pdev, desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, desc, regmap);
}
static struct platform_driver mmcc_msm8960_driver = {
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index a31f6cf0c4e0..0074768e9940 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -2766,7 +2766,7 @@ static int mmcc_msm8974_probe(struct platform_device *pdev)
msm8226_clock_override();
}
- return qcom_cc_really_probe(pdev, desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, desc, regmap);
}
static struct platform_driver mmcc_msm8974_driver = {
diff --git a/drivers/clk/qcom/mmcc-msm8994.c b/drivers/clk/qcom/mmcc-msm8994.c
index 3229ff77372f..dd3f28c4bb00 100644
--- a/drivers/clk/qcom/mmcc-msm8994.c
+++ b/drivers/clk/qcom/mmcc-msm8994.c
@@ -2602,7 +2602,7 @@ static int mmcc_msm8994_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&mmpll3_early, regmap, &mmpll_p_config);
clk_alpha_pll_configure(&mmpll5_early, regmap, &mmpll_p_config);
- return qcom_cc_really_probe(pdev, &mmcc_msm8994_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8994_desc, regmap);
}
static struct platform_driver mmcc_msm8994_driver = {
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index d3f2dc798567..6849c16b3ce6 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -3626,7 +3626,7 @@ static int mmcc_msm8996_probe(struct platform_device *pdev)
/* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */
regmap_update_bits(regmap, 0x5054, BIT(15), 0);
- return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8996_desc, regmap);
}
static struct platform_driver mmcc_msm8996_driver = {
diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c
index 1180e48c687a..711245d388a1 100644
--- a/drivers/clk/qcom/mmcc-msm8998.c
+++ b/drivers/clk/qcom/mmcc-msm8998.c
@@ -2858,7 +2858,7 @@ static int mmcc_msm8998_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- return qcom_cc_really_probe(pdev, &mmcc_msm8998_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8998_desc, regmap);
}
static struct platform_driver mmcc_msm8998_driver = {
diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c
index 996bd01fb9ac..387e8efcd726 100644
--- a/drivers/clk/qcom/mmcc-sdm660.c
+++ b/drivers/clk/qcom/mmcc-sdm660.c
@@ -2847,7 +2847,7 @@ static int mmcc_660_probe(struct platform_device *pdev)
clk_alpha_pll_configure(&mmpll8, regmap, &mmpll8_config);
clk_alpha_pll_configure(&mmpll10, regmap, &mmpll10_config);
- return qcom_cc_really_probe(pdev, &mmcc_660_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &mmcc_660_desc, regmap);
}
static struct platform_driver mmcc_660_driver = {
diff --git a/drivers/clk/qcom/tcsrcc-sm8550.c b/drivers/clk/qcom/tcsrcc-sm8550.c
index 552a3eb1fd91..e5e8f2e82b94 100644
--- a/drivers/clk/qcom/tcsrcc-sm8550.c
+++ b/drivers/clk/qcom/tcsrcc-sm8550.c
@@ -166,7 +166,7 @@ static int tcsr_cc_sm8550_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- return qcom_cc_really_probe(pdev, &tcsr_cc_sm8550_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &tcsr_cc_sm8550_desc, regmap);
}
static struct platform_driver tcsr_cc_sm8550_driver = {
diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c
index 5b9b54f616b8..526165b2acb8 100644
--- a/drivers/clk/qcom/videocc-sc7180.c
+++ b/drivers/clk/qcom/videocc-sc7180.c
@@ -226,7 +226,7 @@ static int video_cc_sc7180_probe(struct platform_device *pdev)
/* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
regmap_update_bits(regmap, 0x984, 0x1, 0x1);
- return qcom_cc_really_probe(pdev, &video_cc_sc7180_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &video_cc_sc7180_desc, regmap);
}
static struct platform_driver video_cc_sc7180_driver = {
diff --git a/drivers/clk/qcom/videocc-sc7280.c b/drivers/clk/qcom/videocc-sc7280.c
index 615695d82319..fd6186d708b9 100644
--- a/drivers/clk/qcom/videocc-sc7280.c
+++ b/drivers/clk/qcom/videocc-sc7280.c
@@ -298,7 +298,7 @@ static int video_cc_sc7280_probe(struct platform_device *pdev)
clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);
- return qcom_cc_really_probe(pdev, &video_cc_sc7280_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &video_cc_sc7280_desc, regmap);
}
static struct platform_driver video_cc_sc7280_driver = {
diff --git a/drivers/clk/qcom/videocc-sdm845.c b/drivers/clk/qcom/videocc-sdm845.c
index c77a4dd5d39c..557264abdbaa 100644
--- a/drivers/clk/qcom/videocc-sdm845.c
+++ b/drivers/clk/qcom/videocc-sdm845.c
@@ -329,7 +329,7 @@ static int video_cc_sdm845_probe(struct platform_device *pdev)
clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config);
- return qcom_cc_really_probe(pdev, &video_cc_sdm845_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &video_cc_sdm845_desc, regmap);
}
static struct platform_driver video_cc_sdm845_driver = {
diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c
index 1afdbe4a249d..a5e7ba988372 100644
--- a/drivers/clk/qcom/videocc-sm8150.c
+++ b/drivers/clk/qcom/videocc-sm8150.c
@@ -245,7 +245,7 @@ static int video_cc_sm8150_probe(struct platform_device *pdev)
/* Keep VIDEO_CC_XO_CLK ALWAYS-ON */
regmap_update_bits(regmap, 0x984, 0x1, 0x1);
- return qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);
+ return qcom_cc_really_probe(&pdev->dev, &video_cc_sm8150_desc, regmap);
}
static struct platform_driver video_cc_sm8150_driver = {
diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c
index ad46c4014a40..6d119dcb7b1e 100644
--- a/drivers/clk/qcom/videocc-sm8250.c
+++ b/drivers/clk/qcom/videocc-sm8250.c
@@ -387,7 +387,7 @@ static int video_cc_sm8250_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0));
- ret = qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8250_desc, regmap);
pm_runtime_put(&pdev->dev);
diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c
index 7246f3c99492..5bf53efccdce 100644
--- a/drivers/clk/qcom/videocc-sm8350.c
+++ b/drivers/clk/qcom/videocc-sm8350.c
@@ -566,7 +566,7 @@ static int video_cc_sm8350_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
regmap_update_bits(regmap, video_cc_xo_clk_cbcr, BIT(0), BIT(0));
- ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8350_desc, regmap);
pm_runtime_put(&pdev->dev);
return ret;
diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c
index 16a61146e619..50cc79ed50bb 100644
--- a/drivers/clk/qcom/videocc-sm8450.c
+++ b/drivers/clk/qcom/videocc-sm8450.c
@@ -433,7 +433,7 @@ static int video_cc_sm8450_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x8130, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x8114, BIT(0), BIT(0));
- ret = qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8450_desc, regmap);
pm_runtime_put(&pdev->dev);
diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c
index f3c9dfaee968..82d7696bb67a 100644
--- a/drivers/clk/qcom/videocc-sm8550.c
+++ b/drivers/clk/qcom/videocc-sm8550.c
@@ -438,7 +438,7 @@ static int video_cc_sm8550_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0));
regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0));
- ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap);
+ ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8550_desc, regmap);
pm_runtime_put(&pdev->dev);
--
2.42.0
On 11/4/2023 11:48 AM, Luo Jie wrote:
> qca8xxx is 4 * 2.5GBaseT ports chip, working as switch mode
> named by qca8386, or working as PHY mode named by qca8084,
> clock hardware reigster is accessed by MDIO bus.
>
> This patch series add the clock controller of qca8363/qca8084,
> and add the clock ops clk_branch2_prepare_ops to avoid spin lock
> used during the clock operation of qca8k clock controller where
> the sleep happens when accessing clock control register by MDIO
> bus.
>
> Changes in v2:
> * remove clock flag CLK_ENABLE_MUTEX_LOCK.
> * add clock ops clk_branch2_qca8k_ops.
> * improve yaml file for fixing dtschema warnings.
> * enable clock controller driver in defconfig.
>
> Changes in v3:
> * rename clk_branch2_qca8k_ops to clk_branch2_mdio_ops.
> * fix review comments on yaml file.
> * use dev_err_probe on driver probe error.
> * only use the compatible "qcom,qca8084-nsscc".
> * remove enable clock controller driver patch.
>
> Changes in v4:
> * add _qcom_cc_really_probe function.
> * commonizing the probe function.
> * remove flag CLK_IS_CRITICAL from clocks only needed
> to be enabled in switch device.
> * update device tree property reg to 0x10.
>
> Changes in v5:
> * commonize qcom_cc_really_probe.
> * add halt_check for the branch clocks.
> * fix the review comments on nsscc-qca8k.c.
>
> Changes in v6:
> * rename clk_branch2_mdio_ops to clk_branch2_prepare_ops.
>
> Changes in v7:
> * remove the clock flag CLK_IS_CRITICAL.
> * optimize the file nsscc-qca8k.c.
> * identify & fix the comments from Stephen.
>
> Changes in v8:
> * add dependency on ARM in Kconfig.
>
> Changes in v9:
> * take the clk_ops clk_rcg2_mux_closest_ops to remove the
> redundant freq_tbls.
>
> Changes in v10:
> * fix the patch CHECK and improve the comments.
>
> Changes in v11:
> * update the clock names to reflect hardware connecton.
> NSS_CC_MAC4_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC ->
> NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_DIV_CLK_SRC
>
> NSS_CC_MAC4_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC ->
> NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_DIV_CLK_SRC
> * resolve the qcom_cc_really_probe merge conflict based
> on the latest code.
>
> Changes in v12:
> * Fix the compile error caused by the parameter of
> qcom_cc_really_probe updated from pdev to &pdev->dev in the
> new merged clock driver gcc-sm4450.c and camcc-sm8550.c.
>
> Luo Jie (4):
> clk: qcom: branch: Add clk_branch2_prepare_ops
> dt-bindings: clock: add qca8386/qca8084 clock and reset definitions
> clk: qcom: common: commonize qcom_cc_really_probe
> clk: qcom: add clock controller driver for qca8386/qca8084
>
> .../bindings/clock/qcom,qca8k-nsscc.yaml | 79 +
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/apss-ipq6018.c | 2 +-
> drivers/clk/qcom/camcc-sc7180.c | 2 +-
> drivers/clk/qcom/camcc-sc7280.c | 2 +-
> drivers/clk/qcom/camcc-sdm845.c | 2 +-
> drivers/clk/qcom/camcc-sm6350.c | 2 +-
> drivers/clk/qcom/camcc-sm8250.c | 2 +-
> drivers/clk/qcom/camcc-sm8450.c | 2 +-
> drivers/clk/qcom/camcc-sm8550.c | 2 +-
> drivers/clk/qcom/clk-branch.c | 7 +
> drivers/clk/qcom/clk-branch.h | 1 +
> drivers/clk/qcom/common.c | 7 +-
> drivers/clk/qcom/common.h | 2 +-
> drivers/clk/qcom/dispcc-qcm2290.c | 2 +-
> drivers/clk/qcom/dispcc-sc7180.c | 2 +-
> drivers/clk/qcom/dispcc-sc7280.c | 2 +-
> drivers/clk/qcom/dispcc-sc8280xp.c | 2 +-
> drivers/clk/qcom/dispcc-sdm845.c | 2 +-
> drivers/clk/qcom/dispcc-sm6115.c | 2 +-
> drivers/clk/qcom/dispcc-sm6125.c | 2 +-
> drivers/clk/qcom/dispcc-sm6350.c | 2 +-
> drivers/clk/qcom/dispcc-sm6375.c | 2 +-
> drivers/clk/qcom/dispcc-sm8250.c | 2 +-
> drivers/clk/qcom/dispcc-sm8450.c | 2 +-
> drivers/clk/qcom/dispcc-sm8550.c | 2 +-
> drivers/clk/qcom/gcc-ipq5018.c | 2 +-
> drivers/clk/qcom/gcc-ipq6018.c | 2 +-
> drivers/clk/qcom/gcc-ipq8074.c | 2 +-
> drivers/clk/qcom/gcc-mdm9607.c | 2 +-
> drivers/clk/qcom/gcc-mdm9615.c | 2 +-
> drivers/clk/qcom/gcc-msm8917.c | 2 +-
> drivers/clk/qcom/gcc-msm8939.c | 2 +-
> drivers/clk/qcom/gcc-msm8953.c | 2 +-
> drivers/clk/qcom/gcc-msm8976.c | 2 +-
> drivers/clk/qcom/gcc-msm8996.c | 2 +-
> drivers/clk/qcom/gcc-msm8998.c | 2 +-
> drivers/clk/qcom/gcc-qcm2290.c | 2 +-
> drivers/clk/qcom/gcc-qcs404.c | 2 +-
> drivers/clk/qcom/gcc-qdu1000.c | 2 +-
> drivers/clk/qcom/gcc-sa8775p.c | 2 +-
> drivers/clk/qcom/gcc-sc7180.c | 2 +-
> drivers/clk/qcom/gcc-sc7280.c | 2 +-
> drivers/clk/qcom/gcc-sc8180x.c | 2 +-
> drivers/clk/qcom/gcc-sc8280xp.c | 2 +-
> drivers/clk/qcom/gcc-sdm660.c | 2 +-
> drivers/clk/qcom/gcc-sdm845.c | 2 +-
> drivers/clk/qcom/gcc-sdx55.c | 2 +-
> drivers/clk/qcom/gcc-sdx65.c | 2 +-
> drivers/clk/qcom/gcc-sdx75.c | 2 +-
> drivers/clk/qcom/gcc-sm4450.c | 2 +-
> drivers/clk/qcom/gcc-sm6115.c | 2 +-
> drivers/clk/qcom/gcc-sm6125.c | 2 +-
> drivers/clk/qcom/gcc-sm6350.c | 2 +-
> drivers/clk/qcom/gcc-sm6375.c | 2 +-
> drivers/clk/qcom/gcc-sm7150.c | 2 +-
> drivers/clk/qcom/gcc-sm8150.c | 2 +-
> drivers/clk/qcom/gcc-sm8250.c | 2 +-
> drivers/clk/qcom/gcc-sm8350.c | 2 +-
> drivers/clk/qcom/gcc-sm8450.c | 2 +-
> drivers/clk/qcom/gcc-sm8550.c | 2 +-
> drivers/clk/qcom/gpucc-msm8998.c | 2 +-
> drivers/clk/qcom/gpucc-sa8775p.c | 2 +-
> drivers/clk/qcom/gpucc-sc7180.c | 2 +-
> drivers/clk/qcom/gpucc-sc7280.c | 2 +-
> drivers/clk/qcom/gpucc-sc8280xp.c | 2 +-
> drivers/clk/qcom/gpucc-sdm660.c | 2 +-
> drivers/clk/qcom/gpucc-sdm845.c | 2 +-
> drivers/clk/qcom/gpucc-sm6115.c | 2 +-
> drivers/clk/qcom/gpucc-sm6125.c | 2 +-
> drivers/clk/qcom/gpucc-sm6350.c | 2 +-
> drivers/clk/qcom/gpucc-sm6375.c | 2 +-
> drivers/clk/qcom/gpucc-sm8150.c | 2 +-
> drivers/clk/qcom/gpucc-sm8250.c | 2 +-
> drivers/clk/qcom/gpucc-sm8350.c | 2 +-
> drivers/clk/qcom/gpucc-sm8450.c | 2 +-
> drivers/clk/qcom/gpucc-sm8550.c | 2 +-
> drivers/clk/qcom/lcc-ipq806x.c | 2 +-
> drivers/clk/qcom/lcc-msm8960.c | 2 +-
> drivers/clk/qcom/lpassaudiocc-sc7280.c | 4 +-
> drivers/clk/qcom/lpasscorecc-sc7180.c | 2 +-
> drivers/clk/qcom/lpasscorecc-sc7280.c | 2 +-
> drivers/clk/qcom/mmcc-msm8960.c | 2 +-
> drivers/clk/qcom/mmcc-msm8974.c | 2 +-
> drivers/clk/qcom/mmcc-msm8994.c | 2 +-
> drivers/clk/qcom/mmcc-msm8996.c | 2 +-
> drivers/clk/qcom/mmcc-msm8998.c | 2 +-
> drivers/clk/qcom/mmcc-sdm660.c | 2 +-
> drivers/clk/qcom/nsscc-qca8k.c | 2139 +++++++++++++++++
> drivers/clk/qcom/tcsrcc-sm8550.c | 2 +-
> drivers/clk/qcom/videocc-sc7180.c | 2 +-
> drivers/clk/qcom/videocc-sc7280.c | 2 +-
> drivers/clk/qcom/videocc-sdm845.c | 2 +-
> drivers/clk/qcom/videocc-sm8150.c | 2 +-
> drivers/clk/qcom/videocc-sm8250.c | 2 +-
> drivers/clk/qcom/videocc-sm8350.c | 2 +-
> drivers/clk/qcom/videocc-sm8450.c | 2 +-
> drivers/clk/qcom/videocc-sm8550.c | 2 +-
> include/dt-bindings/clock/qcom,qca8k-nsscc.h | 101 +
> include/dt-bindings/reset/qcom,qca8k-nsscc.h | 75 +
> 101 files changed, 2508 insertions(+), 97 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml
> create mode 100644 drivers/clk/qcom/nsscc-qca8k.c
> create mode 100644 include/dt-bindings/clock/qcom,qca8k-nsscc.h
> create mode 100644 include/dt-bindings/reset/qcom,qca8k-nsscc.h
>
>
> base-commit: ff269e2cd5adce4ae14f883fc9c8803bc43ee1e9
Hi Bjorn,
Is this patch series fine to be merged now?