This adds the USB and PCIe to AXG, and enables USB & the two M.2 PCIe ports on the S400 board.
Dependencies:
- Patch 1, 2, 4: None
- Patch 3: [1] arm64: dts: meson-axg-s400: add support for Power Controller & MIPI-DSI PHY
[1] https://lore.kernel.org/r/[email protected]
Neil Armstrong (4):
arm64: dts: meson-axg: add USB nodes
arm64: dts: meson-axg-s400: enable USB OTG
arm64: dts: meson-axg: add PCIe nodes
arm64: dts: meson-axg-s400: enable PCIe M.2 Key E slots
.../arm64/boot/dts/amlogic/meson-axg-s400.dts | 16 +++
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 111 ++++++++++++++++++
2 files changed, 127 insertions(+)
--
2.25.1
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 7740f97c240f..359589d1dfa9 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -441,6 +441,16 @@ &pdm {
status = "okay";
};
+&pcieA {
+ reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcieB {
+ reset-gpios = <&gpio GPIOZ_10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
&pwm_ab {
status = "okay";
pinctrl-0 = <&pwm_a_x20_pins>;
--
2.25.1
This adds the USB Glue node, with the USB2 & USB3 controllers along the single
USB2 PHY node.
Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Kevin Hilman <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 50 ++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index d811708f8f67..0c4f0cf076ab 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -172,6 +172,46 @@ soc {
#size-cells = <2>;
ranges;
+ usb: usb@ffe09080 {
+ compatible = "amlogic,meson-axg-usb-ctrl";
+ reg = <0x0 0xffe09080 0x0 0x20>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
+ clock-names = "usb_ctrl", "ddr";
+ resets = <&reset RESET_USB_OTG>;
+
+ dr_mode = "otg";
+
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy1";
+
+ dwc2: usb@ff400000 {
+ compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
+ reg = <0x0 0xff400000 0x0 0x40000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc CLKID_USB1>;
+ clock-names = "otg";
+ phys = <&usb2_phy1>;
+ dr_mode = "peripheral";
+ g-rx-fifo-size = <192>;
+ g-np-tx-fifo-size = <128>;
+ g-tx-fifo-size = <128 128 16 16 16>;
+ };
+
+ dwc3: usb@ff500000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff500000 0x0 0x100000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ maximum-speed = "high-speed";
+ snps,dis_u2_susphy_quirk;
+ };
+ };
+
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,meson-axg-dwmac",
"snps,dwmac-3.70a",
@@ -1795,6 +1835,16 @@ sd_emmc_c: mmc@7000 {
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
};
+
+ usb2_phy1: phy@9020 {
+ compatible = "amlogic,meson-gxl-usb2-phy";
+ #phy-cells = <0>;
+ reg = <0x0 0x9020 0x0 0x20>;
+ clocks = <&clkc CLKID_USB>;
+ clock-names = "phy";
+ resets = <&reset RESET_USB_OTG>;
+ reset-names = "phy";
+ };
};
sram: sram@fffc0000 {
--
2.25.1
This enables USB OTG on the S400 board.
Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Kevin Hilman <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index cb1360ae1211..7740f97c240f 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -584,3 +584,9 @@ &uart_AO {
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
+
+&usb {
+ status = "okay";
+ dr_mode = "otg";
+ vbus-supply = <&usb_pwr>;
+};
--
2.25.1
This adds the nodes for the :
- AXG PCIe PHY, using the shared analog PCIe/MIPI DSI PHY
- 2x AXG PCIe controllers
Signed-off-by: Neil Armstrong <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 61 ++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 0c4f0cf076ab..b5a06210c49a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -172,6 +172,58 @@ soc {
#size-cells = <2>;
ranges;
+ pcieA: pcie@f9800000 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf9800000 0x0 0x400000>,
+ <0x0 0xff646000 0x0 0x2000>,
+ <0x0 0xf9f00000 0x0 0x100000>;
+ reg-names = "elbi", "cfg", "config";
+ interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
+
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
+ clock-names = "general", "pclk", "port";
+ resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>;
+ reset-names = "port", "apb";
+ num-lanes = <1>;
+ phys = <&pcie_phy>;
+ phy-names = "pcie";
+ status = "disabled";
+ };
+
+ pcieB: pcie@fa000000 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xfa000000 0x0 0x400000>,
+ <0x0 0xff648000 0x0 0x2000>,
+ <0x0 0xfa400000 0x0 0x100000>;
+ reg-names = "elbi", "cfg", "config";
+ interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
+
+ clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
+ clock-names = "general", "pclk", "port";
+ resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>;
+ reset-names = "port", "apb";
+ num-lanes = <1>;
+ phys = <&pcie_phy>;
+ phy-names = "pcie";
+ status = "disabled";
+ };
+
usb: usb@ffe09080 {
compatible = "amlogic,meson-axg-usb-ctrl";
reg = <0x0 0xffe09080 0x0 0x20>;
@@ -232,6 +284,15 @@ ethmac: ethernet@ff3f0000 {
status = "disabled";
};
+ pcie_phy: phy@ff644000 {
+ compatible = "amlogic,axg-pcie-phy";
+ reg = <0x0 0xff644000 0x0 0x1c>;
+ resets = <&reset RESET_PCIE_PHY>;
+ phys = <&mipi_pcie_analog_dphy>;
+ phy-names = "analog";
+ #phy-cells = <0>;
+ };
+
pdm: audio-controller@ff632000 {
compatible = "amlogic,axg-pdm";
reg = <0x0 0xff632000 0x0 0x34>;
--
2.25.1
On Fri, 20 Nov 2020 16:32:25 +0100, Neil Armstrong wrote:
> This adds the USB and PCIe to AXG, and enables USB & the two M.2 PCIe ports on the S400 board.
>
> Dependencies:
> - Patch 1, 2, 4: None
> - Patch 3: [1] arm64: dts: meson-axg-s400: add support for Power Controller & MIPI-DSI PHY
>
> [1] https://lore.kernel.org/r/[email protected]
>
> [...]
Applied, thanks!
[1/4] arm64: dts: meson-axg: add USB nodes
commit: ca91acde9a9858a20522abbb2c79c6883ef9bc73
[2/4] arm64: dts: meson-axg-s400: enable USB OTG
commit: 160f1630878e11668336fded29eeb0fe82fb3faf
[3/4] arm64: dts: meson-axg: add PCIe nodes
commit: 9bfc5abed67ae7dcc837dd8f6d61396d1cc9ac2b
[4/4] arm64: dts: meson-axg-s400: enable PCIe M.2 Key E slots
commit: eee685ef92d8cbabb2a61c45fe7d976c3ebc9b1e
Best regards,
--
Kevin Hilman <[email protected]>
Kevin Hilman <[email protected]> writes:
> On Fri, 20 Nov 2020 16:32:25 +0100, Neil Armstrong wrote:
>> This adds the USB and PCIe to AXG, and enables USB & the two M.2 PCIe ports on the S400 board.
>>
>> Dependencies:
>> - Patch 1, 2, 4: None
>> - Patch 3: [1] arm64: dts: meson-axg-s400: add support for Power Controller & MIPI-DSI PHY
>>
>> [1] https://lore.kernel.org/r/[email protected]
>>
>> [...]
>
> Applied, thanks!
>
> [1/4] arm64: dts: meson-axg: add USB nodes
> commit: ca91acde9a9858a20522abbb2c79c6883ef9bc73
> [2/4] arm64: dts: meson-axg-s400: enable USB OTG
> commit: 160f1630878e11668336fded29eeb0fe82fb3faf
> [3/4] arm64: dts: meson-axg: add PCIe nodes
> commit: 9bfc5abed67ae7dcc837dd8f6d61396d1cc9ac2b
> [4/4] arm64: dts: meson-axg-s400: enable PCIe M.2 Key E slots
> commit: eee685ef92d8cbabb2a61c45fe7d976c3ebc9b1e
FYI... these commit IDs are no longer accurate. I relized that the USB
patches were already in my fixes branch, so needed a rebase. I fixed
everything up locally, but the commit IDs are no longer the same as
above.
Kevin
Hi Neil,
On Fri, Nov 20, 2020 at 4:33 PM Neil Armstrong <[email protected]> wrote:
>
> This enables USB OTG on the S400 board.
>
> Signed-off-by: Neil Armstrong <[email protected]>
> Reviewed-by: Kevin Hilman <[email protected]>
this is already upstream [0]: 19f6a6b79880c97bf910c3c72725eb70
[0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f450d2c219f6a6b79880c97bf910c3c72725eb70
Hi Neil,
(I have to admit that for me the PCI(e) bindings are very complex, so
I may be mixing up things. I am still sending this review mail because
"you're doing it different than in meson-g12-common.dtsi")
On Fri, Nov 20, 2020 at 4:33 PM Neil Armstrong <[email protected]> wrote:
[...]
> + pcieA: pcie@f9800000 {
> + compatible = "amlogic,axg-pcie", "snps,dw-pcie";
> + reg = <0x0 0xf9800000 0x0 0x400000>,
> + <0x0 0xff646000 0x0 0x2000>,
> + <0x0 0xf9f00000 0x0 0x100000>;
> + reg-names = "elbi", "cfg", "config";
> + interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
> + bus-range = <0x0 0xff>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
only PCI IO space here, no PCI MEM space?
[...]
> + pcieB: pcie@fa000000 {
> + compatible = "amlogic,axg-pcie", "snps,dw-pcie";
> + reg = <0x0 0xfa000000 0x0 0x400000>,
> + <0x0 0xff648000 0x0 0x2000>,
> + <0x0 0xfa400000 0x0 0x100000>;
> + reg-names = "elbi", "cfg", "config";
> + interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
> + bus-range = <0x0 0xff>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
same as above: only PCI IO space here, no PCI MEM space?
Best regards,
Martin
On 22/11/2020 23:14, Martin Blumenstingl wrote:
> Hi Neil,
>
> (I have to admit that for me the PCI(e) bindings are very complex, so
> I may be mixing up things. I am still sending this review mail because
> "you're doing it different than in meson-g12-common.dtsi")
>
> On Fri, Nov 20, 2020 at 4:33 PM Neil Armstrong <[email protected]> wrote:
> [...]
>> + pcieA: pcie@f9800000 {
>> + compatible = "amlogic,axg-pcie", "snps,dw-pcie";
>> + reg = <0x0 0xf9800000 0x0 0x400000>,
>> + <0x0 0xff646000 0x0 0x2000>,
>> + <0x0 0xf9f00000 0x0 0x100000>;
>> + reg-names = "elbi", "cfg", "config";
>> + interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 0>;
>> + interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
>> + bus-range = <0x0 0xff>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + device_type = "pci";
>> + ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
> only PCI IO space here, no PCI MEM space?
I know, I tried to add IO & MEM space like g12, but it doesn't work.
>
> [...]
>> + pcieB: pcie@fa000000 {
>> + compatible = "amlogic,axg-pcie", "snps,dw-pcie";
>> + reg = <0x0 0xfa000000 0x0 0x400000>,
>> + <0x0 0xff648000 0x0 0x2000>,
>> + <0x0 0xfa400000 0x0 0x100000>;
>> + reg-names = "elbi", "cfg", "config";
>> + interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 0>;
>> + interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
>> + bus-range = <0x0 0xff>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + device_type = "pci";
>> + ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
> same as above: only PCI IO space here, no PCI MEM space?
Same,
I suspect they configured the two instance differently.
Anyway I managed to used an NVMe and a PCIe XHCI controller on each port successfully.
Since I'm a PCIe nOOb, I don't know...
Neil
>
>
> Best regards,
> Martin
>
On 20/11/2020 20:45, Kevin Hilman wrote:
> Kevin Hilman <[email protected]> writes:
>
>> On Fri, 20 Nov 2020 16:32:25 +0100, Neil Armstrong wrote:
>>> This adds the USB and PCIe to AXG, and enables USB & the two M.2 PCIe ports on the S400 board.
>>>
>>> Dependencies:
>>> - Patch 1, 2, 4: None
>>> - Patch 3: [1] arm64: dts: meson-axg-s400: add support for Power Controller & MIPI-DSI PHY
>>>
>>> [1] https://lore.kernel.org/r/[email protected]
>>>
>>> [...]
>>
>> Applied, thanks!
>>
>> [1/4] arm64: dts: meson-axg: add USB nodes
>> commit: ca91acde9a9858a20522abbb2c79c6883ef9bc73
>> [2/4] arm64: dts: meson-axg-s400: enable USB OTG
>> commit: 160f1630878e11668336fded29eeb0fe82fb3faf
>> [3/4] arm64: dts: meson-axg: add PCIe nodes
>> commit: 9bfc5abed67ae7dcc837dd8f6d61396d1cc9ac2b
>> [4/4] arm64: dts: meson-axg-s400: enable PCIe M.2 Key E slots
>> commit: eee685ef92d8cbabb2a61c45fe7d976c3ebc9b1e
>
> FYI... these commit IDs are no longer accurate. I relized that the USB
> patches were already in my fixes branch, so needed a rebase. I fixed
> everything up locally, but the commit IDs are no longer the same as
> above.
Oops it's my fault, i forgot they were merged on -rc2.
thx,
Neil
>
> Kevin
>