This commits are based on the Fabien Parent <[email protected]> work.
The purpose of this series is to add the following HWs / IPs support for
the mt8365-evk board:
- Watchdog
- Power Management Integrated Circuit "PMIC" wrapper
- MT6357 PMIC
- MultiMediaCard "MMC" & Secure Digital "SD" controller
- USB controller
- Ethernet MAC controller
Add CPU Freq & IDLE support for this board.
This series depends to anothers which add support for MT8365 EVK board
[1] and the MT8365 I2C support [2]. Both are currently applied.
The DTB check may failed/warn about pinctrl binding, but it should be
fixed thanks to this serie [3]
Regards,
Alex
[1]: https://lore.kernel.org/all/[email protected]/
[2]: https://lore.kernel.org/all/[email protected]/
[3]: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Changes in v4:
- Remove v3 applied patch from the serie:
- arm64: dts: mediatek: add ethernet support for mt8365 SoC
- arm64: dts: mediatek: add mmc support for mt8365 SoC
- arm64: dts: mediatek: add mt6357 device-tree
- arm64: dts: mediatek: add pwrap support to mt8365 SoC
- arm64: dts: mediatek: Increase the size BL31 reserved memory
- Drop "arm64: dts: mediatek: fix systimer properties" which is done [1]
- Fix style, typo and re-order properties.
- Use interrupts-extended for the PMIC node.
- Link to v3: https://lore.kernel.org/r/[email protected]
Changes in v3:
- Remove v2 applied patch from the serie:
- dt-bindings: mmc: mediatek,mtk-sd: add mt8365
- Add trailers and simply resend.
- Link to v2: https://lore.kernel.org/r/[email protected]
---
Alexandre Mergnat (9):
dt-bindings: watchdog: mediatek,mtk-wdt: add mt8365
dt-bindings: pinctrl: mediatek,mt8365-pinctrl: add drive strength property
arm64: dts: mediatek: add watchdog support for mt8365 SoC
arm64: dts: mediatek: add mt6357 PMIC support for mt8365-evk
arm64: dts: mediatek: add mmc support for mt8365-evk
arm64: dts: mediatek: add usb controller support for mt8365-evk
arm64: dts: mediatek: add ethernet support for mt8365-evk
arm64: dts: mediatek: add OPP support for mt8365 SoC
arm64: dts: mediatek: add cpufreq support for mt8365-evk
Amjad Ouled-Ameur (1):
arm64: dts: mediatek: Add CPU Idle support
Fabien Parent (1):
arm64: dts: mediatek: set vmc regulator as always on
.../bindings/pinctrl/mediatek,mt8365-pinctrl.yaml | 3 +
.../bindings/watchdog/mediatek,mtk-wdt.yaml | 1 +
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 249 +++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 142 ++++++++++++
4 files changed, 395 insertions(+)
---
base-commit: 4f2a499a344b36ebb325e610265452ea88541116
change-id: 20230203-evk-board-support-d5b7a839ed7b
Best regards,
--
Alexandre Mergnat <[email protected]>
This power management system chip integration helps to manage regulators
and keys.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index dd7da86420cf..a238bd0092d2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -12,6 +12,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
#include "mt8365.dtsi"
+#include "mt6357.dtsi"
/ {
model = "MediaTek MT8365 Open Platform EVK";
@@ -94,6 +95,12 @@ &i2c0 {
status = "okay";
};
+&mt6357_pmic {
+ interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
+
&pio {
gpio_keys: gpio-keys-pins {
pins {
--
2.25.1
From: Fabien Parent <[email protected]>
MSDC1 IP block is powered by VMC. Make sure it is always on.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index cd920d09c3fe..1c36d8f19525 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -137,6 +137,11 @@ &mt6357_pmic {
#interrupt-cells = <2>;
};
+/* Needed by MSDC1 */
+&mt6357_vmc_reg {
+ regulator-always-on;
+};
+
&pio {
gpio_keys: gpio-keys-pins {
pins {
--
2.25.1
This patch add support for SuperSpeed USB, in OTG mode, on micro connector.
It also add support for the Extensible Host Controller Interface USB.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index 1c36d8f19525..9760f181eb34 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -314,6 +314,28 @@ &pwm {
status = "okay";
};
+&ssusb {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+ pinctrl-0 = <&usb_pins>;
+ pinctrl-names = "default";
+ usb-role-switch;
+ vusb33-supply = <&mt6357_vusb33_reg>;
+ status = "okay";
+
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
+ type = "micro";
+ vbus-supply = <&usb_otg_vbus>;
+ };
+};
+
+&usb_host {
+ vusb33-supply = <&mt6357_vusb33_reg>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
--
2.25.1
- Enable "vibr" and "vsim2" regulators to power the ethernet chip.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 57 +++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index 9760f181eb34..431078f8670e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -88,6 +88,28 @@ optee_reserved: optee@43200000 {
};
};
+ðernet {
+ pinctrl-0 = <ðernet_pins>;
+ pinctrl-names = "default";
+ phy-handle = <ð_phy>;
+ phy-mode = "rmii";
+ /*
+ * Ethernet and HDMI (DSI0) are sharing pins.
+ * Only one can be enabled at a time and require the physical switch
+ * SW2101 to be set on LAN position
+ */
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
&i2c0 {
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
@@ -137,12 +159,47 @@ &mt6357_pmic {
#interrupt-cells = <2>;
};
+/* Needed by analog switch (multiplexer), HDMI and ethernet */
+&mt6357_vibr_reg {
+ regulator-always-on;
+};
+
/* Needed by MSDC1 */
&mt6357_vmc_reg {
regulator-always-on;
};
+/* Needed by ethernet */
+&mt6357_vsim2_reg {
+ regulator-always-on;
+};
+
&pio {
+ ethernet_pins: ethernet-pins {
+ phy_reset_pins {
+ pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
+ };
+
+ rmii_pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
+ <MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
+ <MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
+ <MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
+ <MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
+ <MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
+ <MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
+ <MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
+ <MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
+ <MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
+ <MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
+ <MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
+ <MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
+ <MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
+ <MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
+ <MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
+ };
+ };
+
gpio_keys: gpio-keys-pins {
pins {
pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
--
2.25.1
In order to have cpufreq support, this patch adds generic Operating
Performance Points support.
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 101 +++++++++++++++++++++++++++++++
1 file changed, 101 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index bb45aab2e6a9..cfe0c67ad61f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -20,6 +20,91 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-850000000 {
+ opp-hz = /bits/ 64 <850000000>;
+ opp-microvolt = <650000>;
+ };
+
+ opp-918000000 {
+ opp-hz = /bits/ 64 <918000000>;
+ opp-microvolt = <668750>;
+ };
+
+ opp-987000000 {
+ opp-hz = /bits/ 64 <987000000>;
+ opp-microvolt = <687500>;
+ };
+
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <706250>;
+ };
+
+ opp-1125000000 {
+ opp-hz = /bits/ 64 <1125000000>;
+ opp-microvolt = <725000>;
+ };
+
+ opp-1216000000 {
+ opp-hz = /bits/ 64 <1216000000>;
+ opp-microvolt = <750000>;
+ };
+
+ opp-1308000000 {
+ opp-hz = /bits/ 64 <1308000000>;
+ opp-microvolt = <775000>;
+ };
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <800000>;
+ };
+
+ opp-1466000000 {
+ opp-hz = /bits/ 64 <1466000000>;
+ opp-microvolt = <825000>;
+ };
+
+ opp-1533000000 {
+ opp-hz = /bits/ 64 <1533000000>;
+ opp-microvolt = <850000>;
+ };
+
+ opp-1633000000 {
+ opp-hz = /bits/ 64 <1633000000>;
+ opp-microvolt = <887500>;
+ };
+
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <912500>;
+ };
+
+ opp-1767000000 {
+ opp-hz = /bits/ 64 <1767000000>;
+ opp-microvolt = <937500>;
+ };
+
+ opp-1834000000 {
+ opp-hz = /bits/ 64 <1834000000>;
+ opp-microvolt = <962500>;
+ };
+
+ opp-1917000000 {
+ opp-hz = /bits/ 64 <1917000000>;
+ opp-microvolt = <993750>;
+ };
+
+ opp-2001000000 {
+ opp-hz = /bits/ 64 <2001000000>;
+ opp-microvolt = <1025000>;
+ };
+ };
+
cpu-map {
cluster0 {
core0 {
@@ -50,6 +135,10 @@ cpu0: cpu@0 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
@@ -65,6 +154,10 @@ cpu1: cpu@1 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate", "armpll";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@2 {
@@ -80,6 +173,10 @@ cpu2: cpu@2 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate", "armpll";
+ operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@3 {
@@ -95,6 +192,10 @@ cpu3: cpu@3 {
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate", "armpll";
+ operating-points-v2 = <&cluster0_opp>;
};
l2: l2-cache {
--
2.25.1
In order to have cpufreq support, this patch adds proc-supply and
sram-supply for each CPU.
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index 431078f8670e..d723838ed49b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -88,6 +88,26 @@ optee_reserved: optee@43200000 {
};
};
+&cpu0 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
ðernet {
pinctrl-0 = <ðernet_pins>;
pinctrl-names = "default";
--
2.25.1
- Add EMMC support on mmc0 (internal memory)
- Add SD-UHS support on mmc1 (external memory)
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 138 ++++++++++++++++++++++++++++
1 file changed, 138 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
index a238bd0092d2..cd920d09c3fe 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -95,6 +95,42 @@ &i2c0 {
status = "okay";
};
+&mmc0 {
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ hs400-ds-delay = <0x12012>;
+ max-frequency = <200000000>;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ pinctrl-0 = <&mmc0_default_pins>;
+ pinctrl-1 = <&mmc0_uhs_pins>;
+ pinctrl-names = "default", "state_uhs";
+ vmmc-supply = <&mt6357_vemc_reg>;
+ vqmmc-supply = <&mt6357_vio18_reg>;
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
+ max-frequency = <200000000>;
+ pinctrl-0 = <&mmc1_default_pins>;
+ pinctrl-1 = <&mmc1_uhs_pins>;
+ pinctrl-names = "default", "state_uhs";
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ vmmc-supply = <&mt6357_vmch_reg>;
+ vqmmc-supply = <&mt6357_vio18_reg>;
+ status = "okay";
+};
+
&mt6357_pmic {
interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
@@ -118,6 +154,108 @@ pins {
};
};
+ mmc0_default_pins: mmc0-default-pins {
+ clk-pins {
+ pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
+ bias-pull-down;
+ };
+
+ cmd-dat-pins {
+ pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+ <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+ <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+ <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+ <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+ <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+ <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+ <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+ <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ rst-pins {
+ pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+ bias-pull-up;
+ };
+ };
+
+ mmc0_uhs_pins: mmc0-uhs-pins {
+ clk-pins {
+ pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ cmd-dat-pins {
+ pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+ <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+ <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+ <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+ <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+ <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+ <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+ <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+ <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ ds-pins {
+ pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ rst-pins {
+ pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-up;
+ };
+ };
+
+ mmc1_default_pins: mmc1-default-pins {
+ cd-pins {
+ pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
+ bias-pull-up;
+ };
+
+ clk-pins {
+ pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ cmd-dat-pins {
+ pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
+ <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
+ <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
+ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
+ <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
+ input-enable;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_uhs_pins: mmc1-uhs-pins {
+ clk-pins {
+ pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ cmd-dat-pins {
+ pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
+ <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
+ <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
+ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
+ <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_6mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
uart0_pins: uart0-pins {
pins {
pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
--
2.25.1
From: Amjad Ouled-Ameur <[email protected]>
MT8365 has 3 CPU Idle states:
- MCDI_CPU. (Multi-Core-Deep-Idle)
- MCDI_CLUSTER.
- DPIDLE. (Deep-Idle)
Signed-off-by: Amjad Ouled-Ameur <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 35 ++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index cfe0c67ad61f..413496c92069 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -128,6 +128,7 @@ cpu0: cpu@0 {
reg = <0x0>;
#cooling-cells = <2>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -147,6 +148,7 @@ cpu1: cpu@1 {
reg = <0x1>;
#cooling-cells = <2>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -166,6 +168,7 @@ cpu2: cpu@2 {
reg = <0x2>;
#cooling-cells = <2>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -185,6 +188,7 @@ cpu3: cpu@3 {
reg = <0x3>;
#cooling-cells = <2>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -198,6 +202,37 @@ cpu3: cpu@3 {
operating-points-v2 = <&cluster0_opp>;
};
+ idle-states {
+ entry-method = "psci";
+
+ CPU_MCDI: cpu-mcdi {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x00010001>;
+ entry-latency-us = <300>;
+ exit-latency-us = <200>;
+ min-residency-us = <1000>;
+ };
+
+ CLUSTER_MCDI: cluster-mcdi {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x01010001>;
+ entry-latency-us = <350>;
+ exit-latency-us = <250>;
+ min-residency-us = <1200>;
+ };
+
+ CLUSTER_DPIDLE: cluster-dpidle {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x01010004>;
+ entry-latency-us = <300>;
+ exit-latency-us = <800>;
+ min-residency-us = <3300>;
+ };
+ };
+
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
--
2.25.1
Alexandre Mergnat <[email protected]> writes:
> This commits are based on the Fabien Parent <[email protected]> work.
>
> The purpose of this series is to add the following HWs / IPs support for
> the mt8365-evk board:
> - Watchdog
> - Power Management Integrated Circuit "PMIC" wrapper
> - MT6357 PMIC
> - MultiMediaCard "MMC" & Secure Digital "SD" controller
> - USB controller
> - Ethernet MAC controller
>
> Add CPU Freq & IDLE support for this board.
>
> This series depends to anothers which add support for MT8365 EVK board
> [1] and the MT8365 I2C support [2]. Both are currently applied.
>
> The DTB check may failed/warn about pinctrl binding, but it should be
> fixed thanks to this serie [3]
It's not just the DTB check that that depends on the pinctrl binding
series. Patch 2 of this series touches the pinctrl bindings, and does
not apply unless the pinctrl series is also applied.
IOW, I needed to apply [1], [2] and [3] to mainline in order to apply
this series.
After applying the dependencies, the kernel fails to build:
../arch/arm64/boot/dts/mediatek/mt8365-evk.dts:15:10: fatal error: mt6357.dtsi: No such file or directory
15 | #include "mt6357.dtsi"
| ^~~~~~~~~~~~~
compilation terminated.
With lots of dependencies like this, it would be useful for you to push
a temporary branch on mainline where you've applied all the dependencies
so we can better see what the dependencies actually are.
Kevin
You forgot to apply the patches merged by Matthias:
Changes in v4:
- Remove v3 applied patch from the serie:
- arm64: dts: mediatek: add ethernet support for mt8365 SoC
- arm64: dts: mediatek: add mmc support for mt8365 SoC
- arm64: dts: mediatek: add mt6357 device-tree
- arm64: dts: mediatek: add pwrap support to mt8365 SoC
- arm64: dts: mediatek: Increase the size BL31 reserved memory
...
Changes in v3:
- Remove v2 applied patch from the serie:
- dt-bindings: mmc: mediatek,mtk-sd: add mt8365
Regards,
Alex
Here a build-able & working branch with dependencies:
https://gitlab.baylibre.com/baylibre/mediatek/bsp/linux/-/commits/amergnat/i350-evk-board-support
Regards,
Alex
Le ven. 31 mars 2023 à 20:45, Alexandre Mergnat
<[email protected]> a écrit :
>
> You forgot to apply the patches merged by Matthias:
>
> Changes in v4:
> - Remove v3 applied patch from the serie:
> - arm64: dts: mediatek: add ethernet support for mt8365 SoC
> - arm64: dts: mediatek: add mmc support for mt8365 SoC
> - arm64: dts: mediatek: add mt6357 device-tree
> - arm64: dts: mediatek: add pwrap support to mt8365 SoC
> - arm64: dts: mediatek: Increase the size BL31 reserved memory
>
> ...
>
> Changes in v3:
> - Remove v2 applied patch from the serie:
> - dt-bindings: mmc: mediatek,mtk-sd: add mt8365
>
> Regards,
> Alex
Alexandre Mergnat <[email protected]> writes:
> Here a build-able & working branch with dependencies:
> https://gitlab.baylibre.com/baylibre/mediatek/bsp/linux/-/commits/amergnat/i350-evk-board-support
This branch doesn't compile.
Kevin
Alexandre Mergnat <[email protected]> writes:
> You forgot to apply the patches merged by Matthias:
Because they weren't listed as dependencies. :)
Kevin
> Changes in v4:
> - Remove v3 applied patch from the serie:
> - arm64: dts: mediatek: add ethernet support for mt8365 SoC
> - arm64: dts: mediatek: add mmc support for mt8365 SoC
> - arm64: dts: mediatek: add mt6357 device-tree
> - arm64: dts: mediatek: add pwrap support to mt8365 SoC
> - arm64: dts: mediatek: Increase the size BL31 reserved memory
>
> ...
>
> Changes in v3:
> - Remove v2 applied patch from the serie:
> - dt-bindings: mmc: mediatek,mtk-sd: add mt8365
>
> Regards,
> Alex
Kevin Hilman <[email protected]> writes:
> Alexandre Mergnat <[email protected]> writes:
>
>> Here a build-able & working branch with dependencies:
>> https://gitlab.baylibre.com/baylibre/mediatek/bsp/linux/-/commits/amergnat/i350-evk-board-support
>
> This branch doesn't compile.
I'm wrong, it compiles fine. I was on the wrong branch.
Sorry for the noise,
Kevin
Alexandre Mergnat <[email protected]> writes:
> Here a build-able & working branch with dependencies:
> https://gitlab.baylibre.com/baylibre/mediatek/bsp/linux/-/commits/amergnat/i350-evk-board-support
Thanks for a branch with all the dependencies.
This branch builds & boots, but crashes because in the upstream default
defconfig, the CPUfreq driver is built-in and the regulator that it
depends on is not enabled.
Changing CPUfreq to be modular with CONFIG_ARM_MEDIATEK_CPUFREQ=m
allowed me to boot to a shell on mt8365-evk.
This suggests that this series needs some defconfig patches to enable
the new features, preferably as modules.
It's probably OK that the defconfig patch(es) come as a separate series,
but not sure what Matthias' preferences are here.
Kevin