This series add a HEVC backend to the Rockchip Video Decoder driver.
A version of this HEVC backend has been in use by the LibreELEC distro
for the past 3+ years [1]. It was initially created based on a copy of
the H264 backend, unstable HEVC uAPI controls and a cabac table + scaling
matrix functions shamelessly copied 1:1 from the Rockchip mpp library.
It has since then been extended to use the stable HEVC uAPI controls and
improved opon e.g. to include support for rk3288 and fix decoding issues
by Alex Bee and Nicolas Dufresne.
The version submitted in this series is based on the code currently used
by the LibreELEC distro, excluding hard/soft reset, and with cabac table
and scaling matrix functions picked from Sebastian Fricke prior series
to add a HEVC backend [2].
Big thanks to Alex Bee, Nicolas Dufresne and Sebastian Fricke for making
this series possible!
Patch 1 add the new HEVC backend.
Patch 2-3 add variants support to the driver.
Patch 4 add support for a rk3288 variant.
Patch 5 add a rk3328 variant to work around hw quirks.
Patch 6-7 add device tree node for rk3288.
Patch 8-9 extend vdec node reg size to include cache/perf registers.
This was tested on a ROCK Pi 4 (RK3399) and Rock64 (RK3328):
v4l2-compliance 1.24.1, 64 bits, 64-bit time_t
...
Total for rkvdec device /dev/video1: 46, Succeeded: 46, Failed: 0, Warnings: 0
Running test suite JCT-VC-HEVC_V1 with decoder FFmpeg-H.265-V4L2-request
...
Ran 135/147 tests successfully
Running test suite JCT-VC-MV-HEVC with decoder FFmpeg-H.265-V4L2-request
...
Ran 9/9 tests successfully
And on a TinkerBoard (RK3288):
v4l2-compliance 1.24.1, 32 bits, 32-bit time_t
...
Total for rkvdec device /dev/video3: 47, Succeeded: 47, Failed: 0, Warnings: 0
Running test suite JCT-VC-HEVC_V1 with decoder FFmpeg-H.265-V4L2-request
...
Ran 137/147 tests successfully
Running test suite JCT-VC-MV-HEVC with decoder FFmpeg-H.265-V4L2-request
...
Ran 9/9 tests successfully
This series depend on the following series:
- media: rkvdec: Add H.264 High 10 and 4:2:2 profile support [3]
To fully runtime test this series you need above series and ffmpeg
patches from [4], this series and its depends is also available at [5].
Full summary of fluster run can be found at [6].
[1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/projects/Rockchip/patches/linux/default/linux-2000-v4l2-wip-rkvdec-hevc.patch
[2] https://lore.kernel.org/linux-media/[email protected]/
[3] https://lore.kernel.org/linux-media/[email protected]/
[4] https://github.com/Kwiboo/FFmpeg/commits/v4l2-request-n6.1-dev/
[5] https://github.com/Kwiboo/linux-rockchip/commits/linuxtv-rkvdec-hevc-v1/
[6] https://gist.github.com/Kwiboo/4c0ed87774dede44ce6838451a1ec93d
Regards,
Jonas
Alex Bee (5):
media: rkvdec: Add variants support
media: rkvdec: Add RK3288 variant
media: rkvdec: Disable QoS for HEVC and VP9 on RK3328
ARM: dts: rockchip: Add vdec node for RK3288
arm64: dts: rockchip: Expand reg size of vdec node for RK3399
Jonas Karlman (4):
media: rkvdec: Add HEVC backend
media: rkvdec: Implement capability filtering
media: dt-bindings: rockchip,vdec: Add RK3288 compatible
arm64: dts: rockchip: Expand reg size of vdec node for RK3328
.../bindings/media/rockchip,vdec.yaml | 4 +-
arch/arm/boot/dts/rockchip/rk3288.dtsi | 17 +-
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +-
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 +-
drivers/staging/media/rkvdec/Makefile | 2 +-
drivers/staging/media/rkvdec/TODO | 7 -
.../staging/media/rkvdec/rkvdec-hevc-data.c | 1848 +++++++++++++++++
drivers/staging/media/rkvdec/rkvdec-hevc.c | 823 ++++++++
drivers/staging/media/rkvdec/rkvdec-regs.h | 3 +
drivers/staging/media/rkvdec/rkvdec-vp9.c | 10 +
drivers/staging/media/rkvdec/rkvdec.c | 180 +-
drivers/staging/media/rkvdec/rkvdec.h | 15 +
12 files changed, 2886 insertions(+), 31 deletions(-)
create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc-data.c
create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c
--
2.42.0
From: Alex Bee <[email protected]>
Add a RK3288 variant, a version of the Rockchip VDEC IP that only
support HEVC decoding.
Signed-off-by: Alex Bee <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
---
drivers/staging/media/rkvdec/rkvdec.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 9cf7b63c1371..aa017ad40270 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -1200,6 +1200,10 @@ static void rkvdec_watchdog_func(struct work_struct *work)
}
}
+static const struct rkvdec_variant rk3288_rkvdec_variant = {
+ .capabilities = RKVDEC_CAPABILITY_HEVC,
+};
+
static const struct rkvdec_variant rk3399_rkvdec_variant = {
.capabilities = RKVDEC_CAPABILITY_HEVC |
RKVDEC_CAPABILITY_H264 |
@@ -1207,6 +1211,10 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = {
};
static const struct of_device_id of_rkvdec_match[] = {
+ {
+ .compatible = "rockchip,rk3288-vdec",
+ .data = &rk3288_rkvdec_variant,
+ },
{
.compatible = "rockchip,rk3399-vdec",
.data = &rk3399_rkvdec_variant,
--
2.42.0
The Rockchip VDEC supports the HEVC codec with the Main and Main10
Profile up to Level 5.1 High tier: 4096x2304@60 fps.
Add the backend for HEVC format to the decoder.
Signed-off-by: Alex Bee <[email protected]>
Signed-off-by: Nicolas Dufresne <[email protected]>
Signed-off-by: Sebastian Fricke <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
---
drivers/staging/media/rkvdec/Makefile | 2 +-
drivers/staging/media/rkvdec/TODO | 7 -
.../staging/media/rkvdec/rkvdec-hevc-data.c | 1848 +++++++++++++++++
drivers/staging/media/rkvdec/rkvdec-hevc.c | 814 ++++++++
drivers/staging/media/rkvdec/rkvdec-regs.h | 1 +
drivers/staging/media/rkvdec/rkvdec.c | 76 +
drivers/staging/media/rkvdec/rkvdec.h | 1 +
7 files changed, 2741 insertions(+), 8 deletions(-)
create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc-data.c
create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c
diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile
index cb86b429cfaa..a77122641d14 100644
--- a/drivers/staging/media/rkvdec/Makefile
+++ b/drivers/staging/media/rkvdec/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o
-rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o
+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o
diff --git a/drivers/staging/media/rkvdec/TODO b/drivers/staging/media/rkvdec/TODO
index 2c0779383276..f089ef859e8c 100644
--- a/drivers/staging/media/rkvdec/TODO
+++ b/drivers/staging/media/rkvdec/TODO
@@ -1,10 +1,3 @@
-* Support for HEVC is planned for this driver.
-
- Given the V4L controls for that CODEC will be part of
- the uABI, it will be required to have the driver in staging.
-
- For this reason, we are keeping this driver in staging for now.
-
* Evaluate introducing a helper to consolidate duplicated
code in rkvdec_request_validate and cedrus_request_validate.
The helper needs to the driver private data associated with
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc-data.c b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c
new file mode 100644
index 000000000000..eac4ea604949
--- /dev/null
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c
@@ -0,0 +1,1848 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip Video Decoder driver
+ *
+ * Copyright (C) 2023 Collabora, Ltd.
+ * Sebastian Fricke <[email protected]>
+ */
+
+#include <linux/types.h>
+
+#define RKV_CABAC_TABLE_SIZE 27456
+
+/*
+ * This file is #include from rkvdec-hevc.c and not compiled.
+ */
+static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = {
+ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f,
+ 0x68, 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40,
+ 0x40, 0x68, 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60,
+ 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50,
+ 0x48, 0x68, 0x60, 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68,
+ 0x68, 0x68, 0x50, 0x48, 0x68, 0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60,
+ 0x50, 0x50, 0x50, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58,
+ 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50, 0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07,
+ 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40, 0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40,
+ 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f, 0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37,
+ 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0f, 0x47, 0x57,
+ 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66, 0x47, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67, 0x57, 0x5e,
+ 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57, 0x4f,
+ 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f,
+ 0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47,
+ 0x66, 0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47,
+ 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37,
+ 0x07, 0x57, 0x4f, 0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10,
+ 0x47, 0x67, 0x40, 0x40, 0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27,
+ 0x4e, 0x47, 0x47, 0x00, 0x0f, 0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07,
+ 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0e, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x64, 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x66, 0x57, 0x5d, 0x00, 0x1e, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5e, 0x5e, 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f,
+ 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x5e, 0x5e, 0x4e, 0x56, 0x4f, 0x07,
+ 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x45, 0x48, 0x20,
+ 0x57, 0x66, 0x66, 0x56, 0x5e, 0x5e, 0x5d, 0x4e, 0x4e, 0x4e, 0x46, 0x56, 0x57, 0x36, 0x07,
+ 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f, 0x47,
+ 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x66, 0x10, 0x47, 0x66, 0x40, 0x40,
+ 0x4f, 0x4d, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x03, 0x27, 0x4d, 0x47, 0x46, 0x01,
+ 0x0f, 0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x34, 0x01, 0x26, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x07, 0x0d, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40,
+ 0x40, 0x40, 0x0e, 0x62, 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x07, 0x00, 0x00, 0x65, 0x57, 0x5c, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+ 0x47, 0x47, 0x5d, 0x5d, 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, 0x65, 0x67, 0x66,
+ 0x65, 0x63, 0x4d, 0x46, 0x62, 0x5d, 0x5d, 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55,
+ 0x65, 0x67, 0x66, 0x65, 0x63, 0x4d, 0x46, 0x62, 0x44, 0x48, 0x20, 0x57, 0x65, 0x65, 0x56,
+ 0x5d, 0x5d, 0x5c, 0x4e, 0x4d, 0x4e, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x45, 0x56, 0x57,
+ 0x36, 0x07, 0x56, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f, 0x47, 0x1e, 0x1e, 0x0f, 0x10,
+ 0x0f, 0x10, 0x07, 0x10, 0x47, 0x65, 0x10, 0x47, 0x65, 0x40, 0x40, 0x4f, 0x4c, 0x08, 0x00,
+ 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x04, 0x27, 0x4c, 0x47, 0x45, 0x01, 0x0f, 0x4f, 0x36, 0x1f,
+ 0x1e, 0x4f, 0x33, 0x01, 0x25, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
+ 0x0c, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0d, 0x40, 0x40, 0x40, 0x0d, 0x60,
+ 0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01,
+ 0x64, 0x56, 0x5b, 0x01, 0x1d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5c, 0x5c,
+ 0x4d, 0x55, 0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, 0x61, 0x4c, 0x45,
+ 0x60, 0x5c, 0x5c, 0x4d, 0x55, 0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64,
+ 0x61, 0x4c, 0x45, 0x60, 0x43, 0x49, 0x21, 0x56, 0x64, 0x64, 0x55, 0x5c, 0x5c, 0x5b, 0x4d,
+ 0x4c, 0x4d, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x44,
+ 0x55, 0x56, 0x35, 0x07, 0x55, 0x4e, 0x46, 0x1d, 0x1d, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11,
+ 0x46, 0x64, 0x11, 0x46, 0x64, 0x40, 0x40, 0x4e, 0x4b, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46,
+ 0x07, 0x06, 0x27, 0x4b, 0x46, 0x44, 0x02, 0x0f, 0x4e, 0x35, 0x1e, 0x1d, 0x4e, 0x31, 0x02,
+ 0x24, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0b, 0x46, 0x56, 0x58,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x0c, 0x40, 0x40, 0x40, 0x0c, 0x5e, 0x46, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x63, 0x56, 0x59, 0x01,
+ 0x1c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5b, 0x5b, 0x4c, 0x54, 0x4e, 0x07,
+ 0x54, 0x64, 0x4e, 0x53, 0x63, 0x66, 0x64, 0x63, 0x60, 0x4b, 0x44, 0x5e, 0x5b, 0x5b, 0x4c,
+ 0x54, 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x53, 0x63, 0x66, 0x64, 0x63, 0x60, 0x4b, 0x44, 0x5e,
+ 0x41, 0x49, 0x21, 0x56, 0x63, 0x63, 0x54, 0x5b, 0x5b, 0x59, 0x4c, 0x4b, 0x4c, 0x43, 0x54,
+ 0x56, 0x34, 0x07, 0x54, 0x43, 0x54, 0x56, 0x34, 0x07, 0x54, 0x43, 0x54, 0x56, 0x34, 0x07,
+ 0x54, 0x4e, 0x46, 0x1c, 0x1c, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x63, 0x11, 0x46,
+ 0x63, 0x40, 0x40, 0x4e, 0x49, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x07, 0x27, 0x49,
+ 0x46, 0x43, 0x03, 0x0f, 0x4e, 0x34, 0x1e, 0x1c, 0x4e, 0x30, 0x03, 0x23, 0x01, 0x07, 0x11,
+ 0x16, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0a, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x0c, 0x40, 0x40, 0x40, 0x0c, 0x5c, 0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x62, 0x56, 0x58, 0x01, 0x1c, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x46, 0x46, 0x5a, 0x5a, 0x4c, 0x54, 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x52,
+ 0x62, 0x66, 0x64, 0x62, 0x5e, 0x4a, 0x44, 0x5c, 0x5a, 0x5a, 0x4c, 0x54, 0x4e, 0x07, 0x54,
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+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x24, 0x06,
+ 0x42, 0x40, 0x44, 0x55, 0x64, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x45, 0x0f, 0x06, 0x21, 0x40,
+ 0x16, 0x12, 0x21, 0x30, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x06, 0x09, 0x1d, 0x07, 0x04, 0x27,
+ 0x2a, 0x09, 0x40, 0x46, 0x4c, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c, 0x12,
+ 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, 0x22, 0x05, 0x0c,
+ 0x0d, 0x0c, 0x12, 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15,
+ 0x22, 0x25, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x30, 0x0d, 0x11,
+ 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e,
+ 0x07, 0x40, 0x4e, 0x07, 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x09, 0x17, 0x45, 0x41, 0x17,
+ 0x45, 0x41, 0x40, 0x40, 0x40, 0x03, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x02, 0x2e, 0x27,
+ 0x1e, 0x07, 0x25, 0x1e, 0x1d, 0x46, 0x15, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x24, 0x09,
+ 0x32, 0x24, 0x24, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x24, 0x06, 0x42, 0x40, 0x45, 0x56,
+ 0x65, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x46, 0x0f, 0x06, 0x22, 0x40, 0x16, 0x13, 0x22, 0x31,
+ 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x04, 0x08, 0x1d, 0x07, 0x04, 0x27, 0x2b, 0x08, 0x40, 0x47,
+ 0x4d, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c, 0x13, 0x1b, 0x05, 0x04, 0x04,
+ 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23, 0x05, 0x0c, 0x0d, 0x0c, 0x13, 0x1b,
+ 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23, 0x25, 0x41, 0x3e,
+ 0x40, 0x4f, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x31, 0x0d, 0x10, 0x46, 0x41, 0x1e, 0x07,
+ 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x4f, 0x07,
+ 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x08, 0x17, 0x46, 0x41, 0x17, 0x46, 0x41, 0x40, 0x40,
+ 0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e,
+ 0x1d, 0x47, 0x13, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x24, 0x08, 0x33, 0x24, 0x24, 0x08,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x07, 0x3e, 0x25, 0x07, 0x41, 0x40, 0x45, 0x56, 0x65, 0x2f, 0x40, 0x07,
+ 0x40, 0x40, 0x46, 0x0f, 0x07, 0x24, 0x40, 0x17, 0x15, 0x24, 0x33, 0x3e, 0x3e, 0x07, 0x07,
+ 0x00, 0x03, 0x08, 0x1e, 0x07, 0x05, 0x27, 0x2d, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40,
+ 0x07, 0x07, 0x06, 0x0d, 0x0e, 0x0d, 0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05,
+ 0x05, 0x24, 0x1d, 0x16, 0x25, 0x06, 0x0d, 0x0e, 0x0d, 0x15, 0x1d, 0x06, 0x05, 0x05, 0x24,
+ 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25, 0x26, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07,
+ 0x07, 0x07, 0x16, 0x16, 0x33, 0x0e, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40,
+ 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x4f, 0x07, 0x0f, 0x0f, 0x1e, 0x26,
+ 0x1e, 0x26, 0x08, 0x17, 0x46, 0x40, 0x17, 0x46, 0x40, 0x40, 0x40, 0x40, 0x02, 0x08, 0x08,
+ 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2f, 0x27, 0x1f, 0x07, 0x26, 0x1f, 0x1e, 0x47, 0x12, 0x10,
+ 0x08, 0x40, 0x0f, 0x08, 0x01, 0x25, 0x08, 0x35, 0x25, 0x25, 0x08, 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
+ 0x3e, 0x26, 0x07, 0x40, 0x40, 0x46, 0x57, 0x66, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f,
+ 0x07, 0x26, 0x40, 0x17, 0x16, 0x26, 0x35, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x01, 0x08, 0x1f,
+ 0x07, 0x06, 0x27, 0x2e, 0x08, 0x40, 0x47, 0x4e, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0e,
+ 0x0f, 0x0e, 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17,
+ 0x26, 0x07, 0x0e, 0x0f, 0x0e, 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06,
+ 0x26, 0x1e, 0x17, 0x26, 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17,
+ 0x35, 0x0f, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10,
+ 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f, 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17,
+ 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40, 0x40, 0x01, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00,
+ 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f, 0x47, 0x11, 0x10, 0x08, 0x40, 0x0f, 0x08,
+ 0x00, 0x26, 0x08, 0x36, 0x26, 0x26, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x27, 0x07, 0x40,
+ 0x40, 0x47, 0x57, 0x67, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f, 0x07, 0x27, 0x40, 0x17,
+ 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07, 0x07, 0x27, 0x2f,
+ 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f, 0x17, 0x1f,
+ 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f, 0x0f,
+ 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27,
+ 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47,
+ 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07,
+ 0x40, 0x4f, 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47,
+ 0x40, 0x40, 0x40, 0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f,
+ 0x07, 0x27, 0x1f, 0x1f, 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37,
+ 0x27, 0x27, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
new file mode 100644
index 000000000000..0c4ddc073a6c
--- /dev/null
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
@@ -0,0 +1,814 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip Video Decoder HEVC backend
+ *
+ * Copyright (C) 2023 Collabora, Ltd.
+ * Sebastian Fricke <[email protected]>
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ * Boris Brezillon <[email protected]>
+ *
+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
+ * Jeffy Chen <[email protected]>
+ */
+
+#include <media/v4l2-mem2mem.h>
+
+#include "rkvdec.h"
+#include "rkvdec-regs.h"
+#include "rkvdec-hevc-data.c"
+
+/* Size in u8/u32 units. */
+#define RKV_SCALING_LIST_SIZE 1360
+#define RKV_PPS_SIZE (80 / 4)
+#define RKV_PPS_LEN 64
+#define RKV_RPS_SIZE (32 / 4)
+#define RKV_RPS_LEN 600
+
+struct rkvdec_sps_pps_packet {
+ u32 info[RKV_PPS_SIZE];
+};
+
+struct rkvdec_rps_packet {
+ u32 info[RKV_RPS_SIZE];
+};
+
+struct rkvdec_ps_field {
+ u16 offset;
+ u8 len;
+};
+
+#define PS_FIELD(_offset, _len) \
+ ((struct rkvdec_ps_field){ _offset, _len })
+
+/* SPS */
+#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4)
+#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4)
+#define CHROMA_FORMAT_IDC PS_FIELD(8, 2)
+#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13)
+#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13)
+#define BIT_DEPTH_LUMA PS_FIELD(36, 4)
+#define BIT_DEPTH_CHROMA PS_FIELD(40, 4)
+#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5)
+#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2)
+#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3)
+#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3)
+#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2)
+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3)
+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3)
+#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1)
+#define AMP_ENABLED_FLAG PS_FIELD(66, 1)
+#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1)
+#define PCM_ENABLED_FLAG PS_FIELD(68, 1)
+#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4)
+#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4)
+#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1)
+#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3)
+#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3)
+#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7)
+#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1)
+#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6)
+#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1)
+#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1)
+/* PPS */
+#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6)
+#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4)
+#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1)
+#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1)
+#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13)
+#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1)
+#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1)
+#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4)
+#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4)
+#define INIT_QP_MINUS26 PS_FIELD(163, 7)
+#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1)
+#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1)
+#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1)
+#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3)
+#define PPS_CB_QP_OFFSET PS_FIELD(176, 5)
+#define PPS_CR_QP_OFFSET PS_FIELD(181, 5)
+#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1)
+#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1)
+#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1)
+#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1)
+#define TILES_ENABLED_FLAG PS_FIELD(190, 1)
+#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1)
+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1)
+#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1)
+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1)
+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1)
+#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4)
+#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4)
+#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1)
+#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3)
+#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1)
+#define NUM_TILE_COLUMNS PS_FIELD(212, 5)
+#define NUM_TILE_ROWS PS_FIELD(217, 5)
+#define COLUMN_WIDTH(i) PS_FIELD(256 + ((i) * 8), 8)
+#define ROW_HEIGHT(i) PS_FIELD(416 + ((i) * 8), 8)
+#define SCALING_LIST_ADDRESS PS_FIELD(592, 32)
+
+/* Data structure describing auxiliary buffer format. */
+struct rkvdec_hevc_priv_tbl {
+ u8 cabac_table[RKV_CABAC_TABLE_SIZE];
+ u8 scaling_list[RKV_SCALING_LIST_SIZE];
+ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN];
+ struct rkvdec_rps_packet rps[RKV_RPS_LEN];
+};
+
+struct rkvdec_hevc_run {
+ struct rkvdec_run base;
+ const struct v4l2_ctrl_hevc_slice_params *slices_params;
+ const struct v4l2_ctrl_hevc_decode_params *decode_params;
+ const struct v4l2_ctrl_hevc_sps *sps;
+ const struct v4l2_ctrl_hevc_pps *pps;
+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix;
+ int num_slices;
+};
+
+struct rkvdec_hevc_ctx {
+ struct rkvdec_aux_buf priv_tbl;
+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache;
+};
+
+struct scaling_factor {
+ u8 scalingfactor0[1248];
+ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/
+ u8 scalingdc[12]; /*N1005 Vienna Meeting*/
+ u8 reserved[4]; /*16Bytes align*/
+};
+
+static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value)
+{
+ u8 bit = field.offset % 32, word = field.offset / 32;
+ u64 mask = GENMASK_ULL(bit + field.len - 1, bit);
+ u64 val = ((u64)value << bit) & mask;
+
+ buf[word] &= ~mask;
+ buf[word] |= val;
+ if (bit + field.len > 32) {
+ buf[word + 1] &= ~(mask >> 32);
+ buf[word + 1] |= val >> 32;
+ }
+}
+
+static void assemble_hw_pps(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
+ const struct v4l2_ctrl_hevc_pps *pps = run->pps;
+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
+ struct rkvdec_sps_pps_packet *hw_ps;
+ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y;
+ u32 log2_min_cu_qp_delta_size, scaling_distance;
+ dma_addr_t scaling_list_address;
+ int i;
+
+ /*
+ * HW read the SPS/PPS information from PPS packet index by PPS id.
+ * offset from the base can be calculated by PPS_id * 80 (size per PPS
+ * packet unit). so the driver copy SPS/PPS information to the exact PPS
+ * packet unit for HW accessing.
+ */
+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
+ memset(hw_ps, 0, sizeof(*hw_ps));
+
+#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
+ /* write sps */
+ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID);
+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
+ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
+ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES);
+ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES);
+ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
+ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
+ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4,
+ LOG2_MAX_PIC_ORDER_CNT_LSB);
+ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size,
+ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3,
+ LOG2_MIN_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2,
+ LOG2_MIN_TRANSFORM_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size,
+ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE);
+ WRITE_PPS(sps->max_transform_hierarchy_depth_inter,
+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER);
+ WRITE_PPS(sps->max_transform_hierarchy_depth_intra,
+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED),
+ SCALING_LIST_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED),
+ AMP_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET),
+ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG);
+ if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) {
+ WRITE_PPS(1, PCM_ENABLED_FLAG);
+ WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1,
+ PCM_SAMPLE_BIT_DEPTH_LUMA);
+ WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1,
+ PCM_SAMPLE_BIT_DEPTH_CHROMA);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED),
+ PCM_LOOP_FILTER_DISABLED_FLAG);
+ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size,
+ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3,
+ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
+ }
+ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT),
+ LONG_TERM_REF_PICS_PRESENT_FLAG);
+ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED),
+ SPS_TEMPORAL_MVP_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED),
+ STRONG_INTRA_SMOOTHING_ENABLED_FLAG);
+
+ /* write pps */
+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
+ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED),
+ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT),
+ OUTPUT_FLAG_PRESENT_FLAG);
+ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED),
+ SIGN_DATA_HIDING_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT),
+ CABAC_INIT_PRESENT_FLAG);
+ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1,
+ NUM_REF_IDX_L0_DEFAULT_ACTIVE);
+ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1,
+ NUM_REF_IDX_L1_DEFAULT_ACTIVE);
+ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED),
+ CONSTRAINED_INTRA_PRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED),
+ TRANSFORM_SKIP_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED),
+ CU_QP_DELTA_ENABLED_FLAG);
+
+ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3;
+ ctb_log2_size_y = min_cb_log2_size_y +
+ sps->log2_diff_max_min_luma_coding_block_size;
+ ctb_size_y = 1 << ctb_log2_size_y;
+ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth;
+ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE);
+ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET);
+ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT),
+ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED),
+ WEIGHTED_PRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED),
+ WEIGHTED_BIPRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED),
+ TRANSQUANT_BYPASS_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED),
+ TILES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED),
+ ENTROPY_CODING_SYNC_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED),
+ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED),
+ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED),
+ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER),
+ PPS_DEBLOCKING_FILTER_DISABLED_FLAG);
+ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2);
+ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT),
+ LISTS_MODIFICATION_PRESENT_FLAG);
+ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT),
+ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG);
+ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS);
+ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS);
+
+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) {
+ /* Userspace also provide column width and row height for uniform spacing */
+ for (i = 0; i <= pps->num_tile_columns_minus1; i++)
+ WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i));
+ for (i = 0; i <= pps->num_tile_rows_minus1; i++)
+ WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i));
+ } else {
+ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1,
+ COLUMN_WIDTH(0));
+ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1,
+ ROW_HEIGHT(0));
+ }
+
+ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list);
+ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance;
+ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS);
+}
+
+/*
+ * Creation of the Reference Picture Set memory blob for the hardware.
+ * The layout looks like this:
+ * [0] 32 bits for L0 (6 references + 2 bits of the 7th reference)
+ * [1] 32 bits for L0 (remaining 3 bits of the 7th reference + 5 references
+ * + 4 bits of the 13th reference)
+ * [2] 11 bits for L0 (remaining bit for 13 and 2 references) and
+ * 21 bits for L1 (4 references + first bit of 5)
+ * [3] 32 bits of padding with 0s
+ * [4] 32 bits for L1 (remaining 4 bits for 5 + 5 references + 3 bits of 11)
+ * [5] 22 bits for L1 (remaining 2 bits of 11 and 4 references)
+ * lowdelay flag (bit 23), rps bit offset long term (bit 24 - 32)
+ * [6] rps bit offset long term (bit 1 - 3), rps bit offset short term (bit 4 - 12)
+ * number of references (bit 13 - 16), remaining 16 bits of padding with 0s
+ * [7] 32 bits of padding with 0s
+ *
+ * Thus we have to set up padding in between reference 5 of the L1 list.
+ */
+static void assemble_hw_rps(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
+ const struct v4l2_ctrl_hevc_slice_params *sl_params;
+ const struct v4l2_hevc_dpb_entry *dpb;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
+ struct rkvdec_rps_packet *hw_ps;
+ int i, j;
+ unsigned int lowdelay;
+
+#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value)
+
+#define REF_PIC_LONG_TERM_L0(i) PS_FIELD((i) * 5, 1)
+#define REF_PIC_IDX_L0(i) PS_FIELD(1 + ((i) * 5), 4)
+#define REF_PIC_LONG_TERM_L1(i) PS_FIELD(((i) < 5 ? 75 : 132) + ((i) * 5), 1)
+#define REF_PIC_IDX_L1(i) PS_FIELD(((i) < 4 ? 76 : 128) + ((i) * 5), 4)
+
+#define LOWDELAY PS_FIELD(182, 1)
+#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10)
+#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9)
+#define NUM_RPS_POC PS_FIELD(202, 4)
+
+ for (j = 0; j < run->num_slices; j++) {
+ uint st_bit_offset = 0;
+ uint num_l0_refs = 0;
+ uint num_l1_refs = 0;
+
+ sl_params = &run->slices_params[j];
+ dpb = decode_params->dpb;
+
+ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) {
+ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1;
+
+ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B)
+ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1;
+
+ lowdelay = 1;
+ } else {
+ lowdelay = 0;
+ }
+
+ hw_ps = &priv_tbl->rps[j];
+ memset(hw_ps, 0, sizeof(*hw_ps));
+
+ for (i = 0; i < num_l0_refs; i++) {
+ const struct v4l2_hevc_dpb_entry dpb_l0 = dpb[sl_params->ref_idx_l0[i]];
+
+ WRITE_RPS(!!(dpb_l0.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
+ REF_PIC_LONG_TERM_L0(i));
+ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
+
+ if (dpb_l0.pic_order_cnt_val > sl_params->slice_pic_order_cnt)
+ lowdelay = 0;
+ }
+
+ for (i = 0; i < num_l1_refs; i++) {
+ const struct v4l2_hevc_dpb_entry dpb_l1 = dpb[sl_params->ref_idx_l1[i]];
+ int is_long_term =
+ !!(dpb_l1.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE);
+
+ WRITE_RPS(is_long_term, REF_PIC_LONG_TERM_L1(i));
+ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
+
+ if (dpb_l1.pic_order_cnt_val > sl_params->slice_pic_order_cnt)
+ lowdelay = 0;
+ }
+
+ WRITE_RPS(lowdelay, LOWDELAY);
+
+ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) {
+ if (sl_params->short_term_ref_pic_set_size)
+ st_bit_offset = sl_params->short_term_ref_pic_set_size;
+ else if (sps->num_short_term_ref_pic_sets > 1)
+ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1);
+ }
+
+ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size,
+ LONG_TERM_RPS_BIT_OFFSET);
+ WRITE_RPS(sl_params->short_term_ref_pic_set_size,
+ SHORT_TERM_RPS_BIT_OFFSET);
+
+ WRITE_RPS(decode_params->num_poc_st_curr_before +
+ decode_params->num_poc_st_curr_after +
+ decode_params->num_poc_lt_curr,
+ NUM_RPS_POC);
+ }
+}
+
+/*
+ * Flip one or more matrices along their main diagonal and flatten them
+ * before writing it to the memory.
+ * Convert:
+ * ABCD AEIM
+ * EFGH => BFJN => AEIMBFJNCGKODHLP
+ * IJKL CGKO
+ * MNOP DHLP
+ */
+static void transpose_and_flatten_matrices(u8 *output, const u8 *input,
+ int matrices, int row_length)
+{
+ int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value;
+
+ matrix_size = row_length * row_length;
+ for (i = 0; i < matrices; i++) {
+ row = 0;
+ x_offset = 0;
+ matrix_offset = i * matrix_size;
+ for (j = 0; j < matrix_size; j++) {
+ y_offset = j - (row * row_length);
+ rot_index = y_offset * row_length + x_offset;
+ new_value = *(input + i * matrix_size + j);
+ output[matrix_offset + rot_index] = *(input + i * matrix_size + j);
+ if ((j + 1) % row_length == 0) {
+ row += 1;
+ x_offset += 1;
+ }
+ }
+ }
+}
+
+static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input)
+{
+ int offset = 0;
+
+ transpose_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4);
+ offset = 6 * 16 * sizeof(u8);
+ transpose_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8);
+ offset += 6 * 64 * sizeof(u8);
+ transpose_and_flatten_matrices(output + offset,
+ (const u8 *)input->scaling_list_16x16, 6, 8);
+ offset += 6 * 64 * sizeof(u8);
+ /* Add a 128 byte padding with 0s between the two 32x32 matrices */
+ transpose_and_flatten_matrices(output + offset,
+ (const u8 *)input->scaling_list_32x32, 1, 8);
+ offset += 64 * sizeof(u8);
+ memset(output + offset, 0, 128);
+ offset += 128 * sizeof(u8);
+ transpose_and_flatten_matrices(output + offset,
+ (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)),
+ 1, 8);
+ offset += 64 * sizeof(u8);
+ memset(output + offset, 0, 128);
+}
+
+/*
+ * Required layout:
+ * A = scaling_list_dc_coef_16x16
+ * B = scaling_list_dc_coef_32x32
+ * 0 = Padding
+ *
+ * A, A, A, A, A, A, B, 0, 0, B, 0, 0
+ */
+static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input)
+{
+ u8 list_32x32[6] = {0};
+
+ memcpy(output, input->scaling_list_dc_coef_16x16, 6 * sizeof(u8));
+ list_32x32[0] = input->scaling_list_dc_coef_32x32[0];
+ list_32x32[3] = input->scaling_list_dc_coef_32x32[1];
+ memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8));
+}
+
+static void translate_scaling_list(struct scaling_factor *output,
+ const struct v4l2_ctrl_hevc_scaling_matrix *input)
+{
+ assemble_scalingfactor0(output->scalingfactor0, input);
+ memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96);
+ assemble_scalingdc(output->scalingdc, input);
+ memset(output->reserved, 0, 4 * sizeof(u8));
+}
+
+static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu;
+ u8 *dst;
+
+ if (!memcmp((void *)&hevc_ctx->scaling_matrix_cache, scaling,
+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)))
+ return;
+
+ dst = tbl->scaling_list;
+ translate_scaling_list((struct scaling_factor *)dst, scaling);
+
+ memcpy((void *)&hevc_ctx->scaling_matrix_cache, scaling,
+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix));
+}
+
+static struct vb2_buffer *
+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run,
+ unsigned int dpb_idx)
+{
+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q;
+ struct vb2_buffer *buf = NULL;
+
+ if (dpb_idx < decode_params->num_active_dpb_entries)
+ buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp);
+
+ /*
+ * If a DPB entry is unused or invalid, the address of current destination
+ * buffer is returned.
+ */
+ if (!buf)
+ return &run->base.bufs.dst->vb2_buf;
+
+ return buf;
+}
+
+static void config_registers(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma;
+ const struct v4l2_pix_format_mplane *dst_fmt;
+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
+ const struct v4l2_format *f;
+ dma_addr_t rlc_addr;
+ dma_addr_t refer_addr;
+ u32 rlc_len;
+ u32 hor_virstride;
+ u32 ver_virstride;
+ u32 y_virstride;
+ u32 yuv_virstride = 0;
+ u32 offset;
+ dma_addr_t dst_addr;
+ u32 reg, i;
+
+ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL);
+
+ f = &ctx->decoded_fmt;
+ dst_fmt = &f->fmt.pix_mp;
+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
+ ver_virstride = dst_fmt->height;
+ y_virstride = hor_virstride * ver_virstride;
+
+ if (sps->chroma_format_idc == 0)
+ yuv_virstride = y_virstride;
+ else if (sps->chroma_format_idc == 1)
+ yuv_virstride = y_virstride + y_virstride / 2;
+ else if (sps->chroma_format_idc == 2)
+ yuv_virstride = 2 * y_virstride;
+
+ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) |
+ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) |
+ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR);
+
+ /* config rlc base address */
+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
+ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
+
+ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
+ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN);
+
+ /* config cabac table */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table);
+ writel_relaxed(priv_start_addr + offset,
+ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE);
+
+ /* config output base address */
+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
+ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
+
+ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
+
+ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
+
+ /* config ref pic address */
+ for (i = 0; i < 15; i++) {
+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i);
+
+ if (i < 4 && decode_params->num_active_dpb_entries) {
+ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0);
+ reg = (reg >> (i * 4)) & 0xf;
+ } else {
+ reg = 0;
+ }
+
+ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
+ writel_relaxed(refer_addr | reg,
+ rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i));
+
+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ?
+ dpb[i].pic_order_cnt_val : 0);
+ writel_relaxed(reg,
+ rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i));
+ }
+
+ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0);
+
+ /* config hw pps address */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set);
+ writel_relaxed(priv_start_addr + offset,
+ rkvdec->regs + RKVDEC_REG_PPS_BASE);
+
+ /* config hw rps address */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps);
+ writel_relaxed(priv_start_addr + offset,
+ rkvdec->regs + RKVDEC_REG_RPS_BASE);
+
+ reg = RKVDEC_AXI_DDR_RDATA(0);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA);
+
+ reg = RKVDEC_AXI_DDR_WDATA(0);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA);
+}
+
+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2
+
+static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx,
+ struct v4l2_format *f)
+{
+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp;
+
+ fmt->num_planes = 1;
+ if (!fmt->plane_fmt[0].sizeimage)
+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height *
+ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES;
+ return 0;
+}
+
+static enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx,
+ struct v4l2_ctrl *ctrl)
+{
+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
+
+ if (ctrl->id != V4L2_CID_STATELESS_HEVC_SPS)
+ return RKVDEC_IMG_FMT_ANY;
+
+ if (sps->bit_depth_luma_minus8 == 0) {
+ if (sps->chroma_format_idc == 2)
+ return RKVDEC_IMG_FMT_422_8BIT;
+ else
+ return RKVDEC_IMG_FMT_420_8BIT;
+ } else if (sps->bit_depth_luma_minus8 == 2) {
+ if (sps->chroma_format_idc == 2)
+ return RKVDEC_IMG_FMT_422_10BIT;
+ else
+ return RKVDEC_IMG_FMT_420_10BIT;
+ }
+
+ return RKVDEC_IMG_FMT_ANY;
+}
+
+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx,
+ const struct v4l2_ctrl_hevc_sps *sps)
+{
+ if (sps->chroma_format_idc > 1)
+ /* Only 4:0:0 and 4:2:0 are supported */
+ return -EINVAL;
+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
+ /* Luma and chroma bit depth mismatch */
+ return -EINVAL;
+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
+ /* Only 8-bit and 10-bit is supported */
+ return -EINVAL;
+
+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width ||
+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ struct rkvdec_hevc_priv_tbl *priv_tbl;
+ struct rkvdec_hevc_ctx *hevc_ctx;
+
+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL);
+ if (!hevc_ctx)
+ return -ENOMEM;
+
+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL);
+ if (!priv_tbl) {
+ kfree(hevc_ctx);
+ return -ENOMEM;
+ }
+
+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl);
+ hevc_ctx->priv_tbl.cpu = priv_tbl;
+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table,
+ sizeof(rkvdec_hevc_cabac_table));
+
+ ctx->priv = hevc_ctx;
+ return 0;
+}
+
+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_dev *rkvdec = ctx->dev;
+
+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size,
+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma);
+ kfree(hevc_ctx);
+}
+
+static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx,
+ struct rkvdec_hevc_run *run)
+{
+ struct v4l2_ctrl *ctrl;
+
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS);
+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS);
+ run->slices_params = ctrl ? ctrl->p_cur.p : NULL;
+ run->num_slices = ctrl->new_elems;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_SPS);
+ run->sps = ctrl ? ctrl->p_cur.p : NULL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_PPS);
+ run->pps = ctrl ? ctrl->p_cur.p : NULL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
+ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX);
+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL;
+
+ rkvdec_run_preamble(ctx, &run->base);
+}
+
+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ struct rkvdec_hevc_run run;
+
+ rkvdec_hevc_run_preamble(ctx, &run);
+
+ assemble_hw_scaling_list(ctx, &run);
+ assemble_hw_pps(ctx, &run);
+ assemble_hw_rps(ctx, &run);
+ config_registers(ctx, &run);
+
+ rkvdec_run_postamble(ctx, &run.base);
+
+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000));
+
+ writel(0, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
+ writel(0, rkvdec->regs + RKVDEC_REG_H264_ERR_E);
+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
+
+ /* Start decoding! */
+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
+ rkvdec->regs + RKVDEC_REG_INTERRUPT);
+
+ return 0;
+}
+
+static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
+{
+ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS)
+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps);
+
+ return 0;
+}
+
+const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = {
+ .adjust_fmt = rkvdec_hevc_adjust_fmt,
+ .start = rkvdec_hevc_start,
+ .stop = rkvdec_hevc_stop,
+ .run = rkvdec_hevc_run,
+ .try_ctrl = rkvdec_hevc_try_ctrl,
+ .get_image_fmt = rkvdec_hevc_get_image_fmt,
+};
diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
index 15b9bee92016..83bf790ed9b7 100644
--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
@@ -43,6 +43,7 @@
#define RKVDEC_RLC_MODE BIT(11)
#define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12)
#define RKVDEC_MODE(x) (((x) & 0x03) << 20)
+#define RKVDEC_MODE_HEVC 0
#define RKVDEC_MODE_H264 1
#define RKVDEC_MODE_VP9 2
#define RKVDEC_RPS_MODE BIT(24)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index eb59605ccf28..eec68a7a1c95 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -164,6 +164,67 @@ static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = {
.s_ctrl = rkvdec_s_ctrl,
};
+static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = {
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS,
+ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY,
+ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS,
+ .cfg.dims = { 600 },
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS,
+ .cfg.ops = &rkvdec_ctrl_ops,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
+ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE,
+ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ },
+ {
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ },
+ {
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
+ },
+};
+
+static const struct rkvdec_ctrls rkvdec_hevc_ctrls = {
+ .ctrls = rkvdec_hevc_ctrl_descs,
+ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs),
+};
+
+static const struct rkvdec_decoded_fmt_desc rkvdec_hevc_decoded_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_NV12,
+ .image_fmt = RKVDEC_IMG_FMT_420_8BIT,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_NV15,
+ .image_fmt = RKVDEC_IMG_FMT_420_10BIT,
+ },
+};
+
static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
{
.cfg.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
@@ -257,6 +318,21 @@ static const struct rkvdec_decoded_fmt_desc rkvdec_vp9_decoded_fmts[] = {
};
static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
+ .frmsize = {
+ .min_width = 64,
+ .max_width = 4096,
+ .step_width = 64,
+ .min_height = 64,
+ .max_height = 2304,
+ .step_height = 16,
+ },
+ .ctrls = &rkvdec_hevc_ctrls,
+ .ops = &rkvdec_hevc_fmt_ops,
+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
+ .decoded_fmts = rkvdec_hevc_decoded_fmts,
+ },
{
.fourcc = V4L2_PIX_FMT_H264_SLICE,
.frmsize = {
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index 9a9f4fced7a1..2f3bda1df5f0 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -138,6 +138,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops;
+extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops;
extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops;
#endif /* RKVDEC_H_ */
--
2.42.0
Add filtering of coded formats and controls depending on a variant
capabilities.
Signed-off-by: Alex Bee <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
---
drivers/staging/media/rkvdec/rkvdec.c | 63 +++++++++++++++++++--------
1 file changed, 46 insertions(+), 17 deletions(-)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index dc1f75dd1c4f..9cf7b63c1371 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -370,13 +370,34 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
}
};
+static inline bool rkvdec_is_capable(struct rkvdec_ctx *ctx,
+ unsigned int capability)
+{
+ return (ctx->dev->capabilities & capability) == capability;
+}
+
static const struct rkvdec_coded_fmt_desc *
-rkvdec_find_coded_fmt_desc(u32 fourcc)
+rkvdec_enum_coded_fmt_desc(struct rkvdec_ctx *ctx, int index)
+{
+ unsigned int i, j;
+
+ for (i = 0, j = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
+ if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability) &&
+ index == j++)
+ return &rkvdec_coded_fmts[i];
+ }
+
+ return NULL;
+}
+
+static const struct rkvdec_coded_fmt_desc *
+rkvdec_find_coded_fmt_desc(struct rkvdec_ctx *ctx, u32 fourcc)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
- if (rkvdec_coded_fmts[i].fourcc == fourcc)
+ if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability) &&
+ rkvdec_coded_fmts[i].fourcc == fourcc)
return &rkvdec_coded_fmts[i];
}
@@ -387,7 +408,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx)
{
struct v4l2_format *f = &ctx->coded_fmt;
- ctx->coded_fmt_desc = &rkvdec_coded_fmts[0];
+ ctx->coded_fmt_desc = rkvdec_enum_coded_fmt_desc(ctx, 0);
rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc);
f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
@@ -401,17 +422,18 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx)
static int rkvdec_enum_framesizes(struct file *file, void *priv,
struct v4l2_frmsizeenum *fsize)
{
- const struct rkvdec_coded_fmt_desc *fmt;
+ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
+ const struct rkvdec_coded_fmt_desc *desc;
if (fsize->index != 0)
return -EINVAL;
- fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format);
- if (!fmt)
+ desc = rkvdec_find_coded_fmt_desc(ctx, fsize->pixel_format);
+ if (!desc)
return -EINVAL;
fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
- fsize->stepwise = fmt->frmsize;
+ fsize->stepwise = desc->frmsize;
return 0;
}
@@ -469,10 +491,10 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv,
struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
const struct rkvdec_coded_fmt_desc *desc;
- desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat);
+ desc = rkvdec_find_coded_fmt_desc(ctx, pix_mp->pixelformat);
if (!desc) {
- pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc;
- desc = &rkvdec_coded_fmts[0];
+ desc = rkvdec_enum_coded_fmt_desc(ctx, 0);
+ pix_mp->pixelformat = desc->fourcc;
}
v4l2_apply_frmsize_constraints(&pix_mp->width,
@@ -549,7 +571,7 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv,
if (ret)
return ret;
- desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat);
+ desc = rkvdec_find_coded_fmt_desc(ctx, f->fmt.pix_mp.pixelformat);
if (!desc)
return -EINVAL;
ctx->coded_fmt_desc = desc;
@@ -601,10 +623,14 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv,
static int rkvdec_enum_output_fmt(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
- if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts))
+ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv);
+ const struct rkvdec_coded_fmt_desc *desc;
+
+ desc = rkvdec_enum_coded_fmt_desc(ctx, f->index);
+ if (!desc)
return -EINVAL;
- f->pixelformat = rkvdec_coded_fmts[f->index].fourcc;
+ f->pixelformat = desc->fourcc;
return 0;
}
@@ -968,14 +994,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx)
int ret;
for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++)
- nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls;
+ if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability))
+ nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls;
v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls);
for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) {
- ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls);
- if (ret)
- goto err_free_handler;
+ if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) {
+ ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls);
+ if (ret)
+ goto err_free_handler;
+ }
}
ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl);
--
2.42.0
From: Alex Bee <[email protected]>
RK3288 contains a Rockchip VDEC block that only support HEVC
decoding. Add a vdec node for this.
Signed-off-by: Alex Bee <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
---
arch/arm/boot/dts/rockchip/rk3288.dtsi | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi
index cb9cdaddffd4..cdeb9c72dae1 100644
--- a/arch/arm/boot/dts/rockchip/rk3288.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi
@@ -1277,6 +1277,21 @@ vpu_mmu: iommu@ff9a0800 {
power-domains = <&power RK3288_PD_VIDEO>;
};
+ hevc: video-codec@ff9c0000 {
+ compatible = "rockchip,rk3288-vdec";
+ reg = <0x0 0xff9c0000 0x0 0x440>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>;
+ clock-names = "axi", "ahb", "cabac", "core";
+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>;
+ assigned-clock-rates = <400000000>, <100000000>,
+ <300000000>, <300000000>;
+ iommus = <&hevc_mmu>;
+ power-domains = <&power RK3288_PD_HEVC>;
+ };
+
hevc_mmu: iommu@ff9c0440 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
@@ -1284,7 +1299,7 @@ hevc_mmu: iommu@ff9c0440 {
clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3288_PD_HEVC>;
};
gpu: gpu@ffa30000 {
--
2.42.0
Expand the reg size for the vdec node to include cache/performance
registers the rkvdec driver writes to.
Fixes: 17408c9b119d ("arm64: dts: rockchip: Add vdec support for RK3328")
Signed-off-by: Jonas Karlman <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index e729e7a22b23..cc8209795c3e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -668,7 +668,7 @@ vpu_mmu: iommu@ff350800 {
vdec: video-codec@ff360000 {
compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec";
- reg = <0x0 0xff360000 0x0 0x400>;
+ reg = <0x0 0xff360000 0x0 0x480>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
--
2.42.0
From: Alex Bee <[email protected]>
Expand the reg size for the vdec node to include cache/performance
registers the rkvdec driver writes to. Also add missing clocks to the
related power-domain.
Fixes: cbd7214402ec ("arm64: dts: rockchip: Define the rockchip Video Decoder node on rk3399")
Signed-off-by: Alex Bee <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 9da0b6d77c8d..a4b693b710a5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1109,7 +1109,9 @@ power-domain@RK3399_PD_VCODEC {
power-domain@RK3399_PD_VDU {
reg = <RK3399_PD_VDU>;
clocks = <&cru ACLK_VDU>,
- <&cru HCLK_VDU>;
+ <&cru HCLK_VDU>,
+ <&cru SCLK_VDU_CA>,
+ <&cru SCLK_VDU_CORE>;
pm_qos = <&qos_video_m1_r>,
<&qos_video_m1_w>;
#power-domain-cells = <0>;
@@ -1385,7 +1387,7 @@ vpu_mmu: iommu@ff650800 {
vdec: video-codec@ff660000 {
compatible = "rockchip,rk3399-vdec";
- reg = <0x0 0xff660000 0x0 0x400>;
+ reg = <0x0 0xff660000 0x0 0x480>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
<&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
--
2.42.0
Add a RK3288 compatible for a version of the Rockchip VDEC IP that only
support HEVC decoding.
Signed-off-by: Jonas Karlman <[email protected]>
---
Documentation/devicetree/bindings/media/rockchip,vdec.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
index 08b02ec16755..0f00e9c86737 100644
--- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
@@ -16,7 +16,9 @@ description: |-
properties:
compatible:
oneOf:
- - const: rockchip,rk3399-vdec
+ - enum:
+ - rockchip,rk3288-vdec
+ - rockchip,rk3399-vdec
- items:
- enum:
- rockchip,rk3228-vdec
--
2.42.0
From: Alex Bee <[email protected]>
The RK3328 VDEC has a HW quirk that require QoS to be disabled when HEVC
or VP9 is decoded, otherwise the decoded picture may become corrupted.
Add a RK3328 variant with a quirk flag to disable QoS when before
decoding is started.
Signed-off-by: Alex Bee <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
---
drivers/staging/media/rkvdec/rkvdec-hevc.c | 9 +++++++++
drivers/staging/media/rkvdec/rkvdec-regs.h | 2 ++
drivers/staging/media/rkvdec/rkvdec-vp9.c | 10 ++++++++++
drivers/staging/media/rkvdec/rkvdec.c | 12 ++++++++++++
drivers/staging/media/rkvdec/rkvdec.h | 4 ++++
5 files changed, 37 insertions(+)
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
index 0c4ddc073a6c..d0a1859d54c1 100644
--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
@@ -788,6 +788,15 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
+ if (rkvdec->quirks & RKVDEC_QUIRK_DISABLE_QOS) {
+ u32 reg;
+
+ reg = readl(rkvdec->regs + RKVDEC_REG_QOS_CTRL);
+ reg |= 0xFFFF;
+ reg &= ~BIT(12);
+ writel(reg, rkvdec->regs + RKVDEC_REG_QOS_CTRL);
+ }
+
/* Start decoding! */
writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
index 83bf790ed9b7..740bdb498634 100644
--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
@@ -218,6 +218,8 @@
#define RKVDEC_REG_H264_ERR_E 0x134
#define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff)
+#define RKVDEC_REG_QOS_CTRL 0x18C
+
#define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410
#define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450
diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c
index 0e7e16f20eeb..cadb9d592308 100644
--- a/drivers/staging/media/rkvdec/rkvdec-vp9.c
+++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c
@@ -824,6 +824,16 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx)
writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
+
+ if (rkvdec->quirks & RKVDEC_QUIRK_DISABLE_QOS) {
+ u32 reg;
+
+ reg = readl(rkvdec->regs + RKVDEC_REG_QOS_CTRL);
+ reg |= 0xFFFF;
+ reg &= ~BIT(12);
+ writel(reg, rkvdec->regs + RKVDEC_REG_QOS_CTRL);
+ }
+
/* Start decoding! */
writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index aa017ad40270..03b6899e6637 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -1204,6 +1204,13 @@ static const struct rkvdec_variant rk3288_rkvdec_variant = {
.capabilities = RKVDEC_CAPABILITY_HEVC,
};
+static const struct rkvdec_variant rk3328_rkvdec_variant = {
+ .capabilities = RKVDEC_CAPABILITY_HEVC |
+ RKVDEC_CAPABILITY_H264 |
+ RKVDEC_CAPABILITY_VP9,
+ .quirks = RKVDEC_QUIRK_DISABLE_QOS,
+};
+
static const struct rkvdec_variant rk3399_rkvdec_variant = {
.capabilities = RKVDEC_CAPABILITY_HEVC |
RKVDEC_CAPABILITY_H264 |
@@ -1215,6 +1222,10 @@ static const struct of_device_id of_rkvdec_match[] = {
.compatible = "rockchip,rk3288-vdec",
.data = &rk3288_rkvdec_variant,
},
+ {
+ .compatible = "rockchip,rk3328-vdec",
+ .data = &rk3328_rkvdec_variant,
+ },
{
.compatible = "rockchip,rk3399-vdec",
.data = &rk3399_rkvdec_variant,
@@ -1245,6 +1256,7 @@ static int rkvdec_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, rkvdec);
rkvdec->dev = &pdev->dev;
rkvdec->capabilities = variant->capabilities;
+ rkvdec->quirks = variant->quirks;
mutex_init(&rkvdec->vdev_lock);
INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func);
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index 14ce26a6c618..1d5d405da56c 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -26,6 +26,8 @@
#define RKVDEC_CAPABILITY_H264 BIT(1)
#define RKVDEC_CAPABILITY_VP9 BIT(2)
+#define RKVDEC_QUIRK_DISABLE_QOS BIT(0)
+
struct rkvdec_ctx;
struct rkvdec_ctrl_desc {
@@ -69,6 +71,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
struct rkvdec_variant {
unsigned int capabilities;
+ unsigned int quirks;
};
struct rkvdec_coded_fmt_ops {
@@ -120,6 +123,7 @@ struct rkvdec_dev {
struct mutex vdev_lock; /* serializes ioctls */
struct delayed_work watchdog_work;
unsigned int capabilities;
+ unsigned int quirks;
};
struct rkvdec_ctx {
--
2.42.0
Hi Jonas,
Am Montag, 6. November 2023, 00:36:07 CET schrieb Jonas Karlman:
> This series add a HEVC backend to the Rockchip Video Decoder driver.
>
> A version of this HEVC backend has been in use by the LibreELEC distro
> for the past 3+ years [1]. It was initially created based on a copy of
> the H264 backend, unstable HEVC uAPI controls and a cabac table + scaling
> matrix functions shamelessly copied 1:1 from the Rockchip mpp library.
>
> It has since then been extended to use the stable HEVC uAPI controls and
> improved opon e.g. to include support for rk3288 and fix decoding issues
> by Alex Bee and Nicolas Dufresne.
>
> The version submitted in this series is based on the code currently used
> by the LibreELEC distro, excluding hard/soft reset, and with cabac table
> and scaling matrix functions picked from Sebastian Fricke prior series
> to add a HEVC backend [2].
>
> Big thanks to Alex Bee, Nicolas Dufresne and Sebastian Fricke for making
> this series possible!
>
> Patch 1 add the new HEVC backend.
> Patch 2-3 add variants support to the driver.
> Patch 4 add support for a rk3288 variant.
> Patch 5 add a rk3328 variant to work around hw quirks.
> Patch 6-7 add device tree node for rk3288.
> Patch 8-9 extend vdec node reg size to include cache/perf registers.
thanks a lot for working on this.
Looking at the rkvdec TODO file, isn't the hvec support the only thing
keeping the driver in staging? So with this support using stable hevc
uapi, shouldn't the driver then also move out of staging after this
series is applied?
Heiko
> This was tested on a ROCK Pi 4 (RK3399) and Rock64 (RK3328):
>
> v4l2-compliance 1.24.1, 64 bits, 64-bit time_t
> ...
> Total for rkvdec device /dev/video1: 46, Succeeded: 46, Failed: 0, Warnings: 0
>
> Running test suite JCT-VC-HEVC_V1 with decoder FFmpeg-H.265-V4L2-request
> ...
> Ran 135/147 tests successfully
>
> Running test suite JCT-VC-MV-HEVC with decoder FFmpeg-H.265-V4L2-request
> ...
> Ran 9/9 tests successfully
>
> And on a TinkerBoard (RK3288):
>
> v4l2-compliance 1.24.1, 32 bits, 32-bit time_t
> ...
> Total for rkvdec device /dev/video3: 47, Succeeded: 47, Failed: 0, Warnings: 0
>
> Running test suite JCT-VC-HEVC_V1 with decoder FFmpeg-H.265-V4L2-request
> ...
> Ran 137/147 tests successfully
>
> Running test suite JCT-VC-MV-HEVC with decoder FFmpeg-H.265-V4L2-request
> ...
> Ran 9/9 tests successfully
>
> This series depend on the following series:
> - media: rkvdec: Add H.264 High 10 and 4:2:2 profile support [3]
>
> To fully runtime test this series you need above series and ffmpeg
> patches from [4], this series and its depends is also available at [5].
>
> Full summary of fluster run can be found at [6].
>
> [1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/projects/Rockchip/patches/linux/default/linux-2000-v4l2-wip-rkvdec-hevc.patch
> [2] https://lore.kernel.org/linux-media/[email protected]/
> [3] https://lore.kernel.org/linux-media/[email protected]/
> [4] https://github.com/Kwiboo/FFmpeg/commits/v4l2-request-n6.1-dev/
> [5] https://github.com/Kwiboo/linux-rockchip/commits/linuxtv-rkvdec-hevc-v1/
> [6] https://gist.github.com/Kwiboo/4c0ed87774dede44ce6838451a1ec93d
>
> Regards,
> Jonas
>
> Alex Bee (5):
> media: rkvdec: Add variants support
> media: rkvdec: Add RK3288 variant
> media: rkvdec: Disable QoS for HEVC and VP9 on RK3328
> ARM: dts: rockchip: Add vdec node for RK3288
> arm64: dts: rockchip: Expand reg size of vdec node for RK3399
>
> Jonas Karlman (4):
> media: rkvdec: Add HEVC backend
> media: rkvdec: Implement capability filtering
> media: dt-bindings: rockchip,vdec: Add RK3288 compatible
> arm64: dts: rockchip: Expand reg size of vdec node for RK3328
>
> .../bindings/media/rockchip,vdec.yaml | 4 +-
> arch/arm/boot/dts/rockchip/rk3288.dtsi | 17 +-
> arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +-
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 +-
> drivers/staging/media/rkvdec/Makefile | 2 +-
> drivers/staging/media/rkvdec/TODO | 7 -
> .../staging/media/rkvdec/rkvdec-hevc-data.c | 1848 +++++++++++++++++
> drivers/staging/media/rkvdec/rkvdec-hevc.c | 823 ++++++++
> drivers/staging/media/rkvdec/rkvdec-regs.h | 3 +
> drivers/staging/media/rkvdec/rkvdec-vp9.c | 10 +
> drivers/staging/media/rkvdec/rkvdec.c | 180 +-
> drivers/staging/media/rkvdec/rkvdec.h | 15 +
> 12 files changed, 2886 insertions(+), 31 deletions(-)
> create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc-data.c
> create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c
>
>
On Sun, 5 Nov 2023 23:36:07 +0000, Jonas Karlman wrote:
> This series add a HEVC backend to the Rockchip Video Decoder driver.
>
> A version of this HEVC backend has been in use by the LibreELEC distro
> for the past 3+ years [1]. It was initially created based on a copy of
> the H264 backend, unstable HEVC uAPI controls and a cabac table + scaling
> matrix functions shamelessly copied 1:1 from the Rockchip mpp library.
>
> [...]
Applied as fix for 6.7-rc, thanks!
[8/9] arm64: dts: rockchip: Expand reg size of vdec node for RK3328
commit: 667a89fe8383de1be44a8cdf22716448f84ee510
[9/9] arm64: dts: rockchip: Expand reg size of vdec node for RK3399
commit: a31d776cccb98e0763dadce023ad5caa1a6dce2c
Expanding the range up to the start of the MMU should always be the
correct way, so this doesn't need the rest of the series :-) .
Best regards,
--
Heiko Stuebner <[email protected]>
On Sun, Nov 05, 2023 at 11:36:13PM +0000, Jonas Karlman wrote:
> Add a RK3288 compatible for a version of the Rockchip VDEC IP that only
> support HEVC decoding.
>
> Signed-off-by: Jonas Karlman <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Thanks,
Conor.
> ---
> Documentation/devicetree/bindings/media/rockchip,vdec.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
> index 08b02ec16755..0f00e9c86737 100644
> --- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
> +++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml
> @@ -16,7 +16,9 @@ description: |-
> properties:
> compatible:
> oneOf:
> - - const: rockchip,rk3399-vdec
> + - enum:
> + - rockchip,rk3288-vdec
> + - rockchip,rk3399-vdec
> - items:
> - enum:
> - rockchip,rk3228-vdec
> --
> 2.42.0
>
On 09/11/2023 18:44, Jonas Karlman wrote:
> Hi Hans,
>
> On 2023-11-07 14:49, Hans Verkuil wrote:
>> Hi Jonas,
>>
>> On 06/11/2023 00:36, Jonas Karlman wrote:
>>> This series add a HEVC backend to the Rockchip Video Decoder driver.
>>>
>>> A version of this HEVC backend has been in use by the LibreELEC distro
>>> for the past 3+ years [1]. It was initially created based on a copy of
>>> the H264 backend, unstable HEVC uAPI controls and a cabac table + scaling
>>> matrix functions shamelessly copied 1:1 from the Rockchip mpp library.
>>>
>>> It has since then been extended to use the stable HEVC uAPI controls and
>>> improved opon e.g. to include support for rk3288 and fix decoding issues
>>> by Alex Bee and Nicolas Dufresne.
>>>
>>> The version submitted in this series is based on the code currently used
>>> by the LibreELEC distro, excluding hard/soft reset, and with cabac table
>>> and scaling matrix functions picked from Sebastian Fricke prior series
>>> to add a HEVC backend [2].
>>>
>>> Big thanks to Alex Bee, Nicolas Dufresne and Sebastian Fricke for making
>>> this series possible!
>>
>> I ran this series through smatch and found these two issues:
>>
>> drivers/staging/media/rkvdec/rkvdec-hevc.c: In function 'transpose_and_flatten_matrices':
>> drivers/staging/media/rkvdec/rkvdec-hevc.c:429:83: warning: variable 'new_value' set but not used [-Wunused-but-set-variable]
>> 429 | int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value;
>> | ^~~~~~~~~
>> drivers/staging/media/rkvdec/rkvdec-hevc.c:756 rkvdec_hevc_run_preamble() error: we previously assumed 'ctrl' could be null (see line 755)
>
> Thanks, will fix in v2.
>
>>
>> Also, this series drops the HEVC part from the TODO file, but
>> I wonder if the last remaining item is still valid:
>>
>> * Evaluate introducing a helper to consolidate duplicated
>> code in rkvdec_request_validate and cedrus_request_validate.
>> The helper needs to the driver private data associated with
>> the videobuf2 queue, from a media request.
>>
>> It doesn't look like there is much duplicate code at all. It is certainly not
>> something that prevents this driver from moving out of staging.
>
> I agree, if this is still valid it is not something that should prevent
> this driver from moving out of staging.
>
> There is however one remaining feature/issue that is not listed in TODO.
>
> In certain situations the hw block may need a reset after there has been
> a decoding error, especially after a hevc decoding error. Decoding can
> typically be re-started with successful result after a short pm
> autosuspend timeout.
>
> We do have a soft/hard reset implementation in LibreELEC-distro,
> excluded it from this series because reset is typically not needed, and
> I think the reset code need some rework to be upstream ready.
>
> Would missing hard reset support be a reason for keeping this driver
> in staging?
I think Nicolas would be better placed to comment on that. If it is not
considered a blocker, shouldn't there at least be a patch adding comments
at the relevant place describing this issue? That way it is at least
documented as a known issue.
Regards,
Hans
>
> Regards,
> Jonas
>
>>
>> Regards,
>>
>> Hans
>>
>>>
>>> Patch 1 add the new HEVC backend.
>>> Patch 2-3 add variants support to the driver.
>>> Patch 4 add support for a rk3288 variant.
>>> Patch 5 add a rk3328 variant to work around hw quirks.
>>> Patch 6-7 add device tree node for rk3288.
>>> Patch 8-9 extend vdec node reg size to include cache/perf registers.
>>>
>>> This was tested on a ROCK Pi 4 (RK3399) and Rock64 (RK3328):
>>>
>>> v4l2-compliance 1.24.1, 64 bits, 64-bit time_t
>>> ...
>>> Total for rkvdec device /dev/video1: 46, Succeeded: 46, Failed: 0, Warnings: 0
>>>
>>> Running test suite JCT-VC-HEVC_V1 with decoder FFmpeg-H.265-V4L2-request
>>> ...
>>> Ran 135/147 tests successfully
>>>
>>> Running test suite JCT-VC-MV-HEVC with decoder FFmpeg-H.265-V4L2-request
>>> ...
>>> Ran 9/9 tests successfully
>>>
>>> And on a TinkerBoard (RK3288):
>>>
>>> v4l2-compliance 1.24.1, 32 bits, 32-bit time_t
>>> ...
>>> Total for rkvdec device /dev/video3: 47, Succeeded: 47, Failed: 0, Warnings: 0
>>>
>>> Running test suite JCT-VC-HEVC_V1 with decoder FFmpeg-H.265-V4L2-request
>>> ...
>>> Ran 137/147 tests successfully
>>>
>>> Running test suite JCT-VC-MV-HEVC with decoder FFmpeg-H.265-V4L2-request
>>> ...
>>> Ran 9/9 tests successfully
>>>
>>> This series depend on the following series:
>>> - media: rkvdec: Add H.264 High 10 and 4:2:2 profile support [3]
>>>
>>> To fully runtime test this series you need above series and ffmpeg
>>> patches from [4], this series and its depends is also available at [5].
>>>
>>> Full summary of fluster run can be found at [6].
>>>
>>> [1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/projects/Rockchip/patches/linux/default/linux-2000-v4l2-wip-rkvdec-hevc.patch
>>> [2] https://lore.kernel.org/linux-media/[email protected]/
>>> [3] https://lore.kernel.org/linux-media/[email protected]/
>>> [4] https://github.com/Kwiboo/FFmpeg/commits/v4l2-request-n6.1-dev/
>>> [5] https://github.com/Kwiboo/linux-rockchip/commits/linuxtv-rkvdec-hevc-v1/
>>> [6] https://gist.github.com/Kwiboo/4c0ed87774dede44ce6838451a1ec93d
>>>
>>> Regards,
>>> Jonas
>>>
>>> Alex Bee (5):
>>> media: rkvdec: Add variants support
>>> media: rkvdec: Add RK3288 variant
>>> media: rkvdec: Disable QoS for HEVC and VP9 on RK3328
>>> ARM: dts: rockchip: Add vdec node for RK3288
>>> arm64: dts: rockchip: Expand reg size of vdec node for RK3399
>>>
>>> Jonas Karlman (4):
>>> media: rkvdec: Add HEVC backend
>>> media: rkvdec: Implement capability filtering
>>> media: dt-bindings: rockchip,vdec: Add RK3288 compatible
>>> arm64: dts: rockchip: Expand reg size of vdec node for RK3328
>>>
>>> .../bindings/media/rockchip,vdec.yaml | 4 +-
>>> arch/arm/boot/dts/rockchip/rk3288.dtsi | 17 +-
>>> arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +-
>>> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 +-
>>> drivers/staging/media/rkvdec/Makefile | 2 +-
>>> drivers/staging/media/rkvdec/TODO | 7 -
>>> .../staging/media/rkvdec/rkvdec-hevc-data.c | 1848 +++++++++++++++++
>>> drivers/staging/media/rkvdec/rkvdec-hevc.c | 823 ++++++++
>>> drivers/staging/media/rkvdec/rkvdec-regs.h | 3 +
>>> drivers/staging/media/rkvdec/rkvdec-vp9.c | 10 +
>>> drivers/staging/media/rkvdec/rkvdec.c | 180 +-
>>> drivers/staging/media/rkvdec/rkvdec.h | 15 +
>>> 12 files changed, 2886 insertions(+), 31 deletions(-)
>>> create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc-data.c
>>> create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c
>>>
>>
>
On Wed, Nov 22, 2023 at 11:23 PM Hans Verkuil <[email protected]> wrote:
>
> On 09/11/2023 18:44, Jonas Karlman wrote:
> > Hi Hans,
> >
> > On 2023-11-07 14:49, Hans Verkuil wrote:
> >> Hi Jonas,
> >>
> >> On 06/11/2023 00:36, Jonas Karlman wrote:
> >>> This series add a HEVC backend to the Rockchip Video Decoder driver.
> >>>
> >>> A version of this HEVC backend has been in use by the LibreELEC distro
> >>> for the past 3+ years [1]. It was initially created based on a copy of
> >>> the H264 backend, unstable HEVC uAPI controls and a cabac table + scaling
> >>> matrix functions shamelessly copied 1:1 from the Rockchip mpp library.
> >>>
> >>> It has since then been extended to use the stable HEVC uAPI controls and
> >>> improved opon e.g. to include support for rk3288 and fix decoding issues
> >>> by Alex Bee and Nicolas Dufresne.
> >>>
> >>> The version submitted in this series is based on the code currently used
> >>> by the LibreELEC distro, excluding hard/soft reset, and with cabac table
> >>> and scaling matrix functions picked from Sebastian Fricke prior series
> >>> to add a HEVC backend [2].
> >>>
> >>> Big thanks to Alex Bee, Nicolas Dufresne and Sebastian Fricke for making
> >>> this series possible!
> >>
> >> I ran this series through smatch and found these two issues:
> >>
> >> drivers/staging/media/rkvdec/rkvdec-hevc.c: In function 'transpose_and_flatten_matrices':
> >> drivers/staging/media/rkvdec/rkvdec-hevc.c:429:83: warning: variable 'new_value' set but not used [-Wunused-but-set-variable]
> >> 429 | int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value;
> >> | ^~~~~~~~~
> >> drivers/staging/media/rkvdec/rkvdec-hevc.c:756 rkvdec_hevc_run_preamble() error: we previously assumed 'ctrl' could be null (see line 755)
> >
> > Thanks, will fix in v2.
> >
> >>
> >> Also, this series drops the HEVC part from the TODO file, but
> >> I wonder if the last remaining item is still valid:
> >>
> >> * Evaluate introducing a helper to consolidate duplicated
> >> code in rkvdec_request_validate and cedrus_request_validate.
> >> The helper needs to the driver private data associated with
> >> the videobuf2 queue, from a media request.
> >>
> >> It doesn't look like there is much duplicate code at all. It is certainly not
> >> something that prevents this driver from moving out of staging.
> >
> > I agree, if this is still valid it is not something that should prevent
> > this driver from moving out of staging.
> >
> > There is however one remaining feature/issue that is not listed in TODO.
> >
> > In certain situations the hw block may need a reset after there has been
> > a decoding error, especially after a hevc decoding error. Decoding can
> > typically be re-started with successful result after a short pm
> > autosuspend timeout.
> >
> > We do have a soft/hard reset implementation in LibreELEC-distro,
> > excluded it from this series because reset is typically not needed, and
> > I think the reset code need some rework to be upstream ready.
> >
> > Would missing hard reset support be a reason for keeping this driver
> > in staging?
>
> I think Nicolas would be better placed to comment on that. If it is not
> considered a blocker, shouldn't there at least be a patch adding comments
> at the relevant place describing this issue? That way it is at least
> documented as a known issue.
FWIW Hantro on i.MX8MM doesn't either.
ChenYu
> Regards,
>
> Hans
>
> >
> > Regards,
> > Jonas
> >
> >>
> >> Regards,
> >>
> >> Hans
> >>
> >>>
> >>> Patch 1 add the new HEVC backend.
> >>> Patch 2-3 add variants support to the driver.
> >>> Patch 4 add support for a rk3288 variant.
> >>> Patch 5 add a rk3328 variant to work around hw quirks.
> >>> Patch 6-7 add device tree node for rk3288.
> >>> Patch 8-9 extend vdec node reg size to include cache/perf registers.
> >>>
> >>> This was tested on a ROCK Pi 4 (RK3399) and Rock64 (RK3328):
> >>>
> >>> v4l2-compliance 1.24.1, 64 bits, 64-bit time_t
> >>> ...
> >>> Total for rkvdec device /dev/video1: 46, Succeeded: 46, Failed: 0, Warnings: 0
> >>>
> >>> Running test suite JCT-VC-HEVC_V1 with decoder FFmpeg-H.265-V4L2-request
> >>> ...
> >>> Ran 135/147 tests successfully
> >>>
> >>> Running test suite JCT-VC-MV-HEVC with decoder FFmpeg-H.265-V4L2-request
> >>> ...
> >>> Ran 9/9 tests successfully
> >>>
> >>> And on a TinkerBoard (RK3288):
> >>>
> >>> v4l2-compliance 1.24.1, 32 bits, 32-bit time_t
> >>> ...
> >>> Total for rkvdec device /dev/video3: 47, Succeeded: 47, Failed: 0, Warnings: 0
> >>>
> >>> Running test suite JCT-VC-HEVC_V1 with decoder FFmpeg-H.265-V4L2-request
> >>> ...
> >>> Ran 137/147 tests successfully
> >>>
> >>> Running test suite JCT-VC-MV-HEVC with decoder FFmpeg-H.265-V4L2-request
> >>> ...
> >>> Ran 9/9 tests successfully
> >>>
> >>> This series depend on the following series:
> >>> - media: rkvdec: Add H.264 High 10 and 4:2:2 profile support [3]
> >>>
> >>> To fully runtime test this series you need above series and ffmpeg
> >>> patches from [4], this series and its depends is also available at [5].
> >>>
> >>> Full summary of fluster run can be found at [6].
> >>>
> >>> [1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/projects/Rockchip/patches/linux/default/linux-2000-v4l2-wip-rkvdec-hevc.patch
> >>> [2] https://lore.kernel.org/linux-media/[email protected]/
> >>> [3] https://lore.kernel.org/linux-media/[email protected]/
> >>> [4] https://github.com/Kwiboo/FFmpeg/commits/v4l2-request-n6.1-dev/
> >>> [5] https://github.com/Kwiboo/linux-rockchip/commits/linuxtv-rkvdec-hevc-v1/
> >>> [6] https://gist.github.com/Kwiboo/4c0ed87774dede44ce6838451a1ec93d
> >>>
> >>> Regards,
> >>> Jonas
> >>>
> >>> Alex Bee (5):
> >>> media: rkvdec: Add variants support
> >>> media: rkvdec: Add RK3288 variant
> >>> media: rkvdec: Disable QoS for HEVC and VP9 on RK3328
> >>> ARM: dts: rockchip: Add vdec node for RK3288
> >>> arm64: dts: rockchip: Expand reg size of vdec node for RK3399
> >>>
> >>> Jonas Karlman (4):
> >>> media: rkvdec: Add HEVC backend
> >>> media: rkvdec: Implement capability filtering
> >>> media: dt-bindings: rockchip,vdec: Add RK3288 compatible
> >>> arm64: dts: rockchip: Expand reg size of vdec node for RK3328
> >>>
> >>> .../bindings/media/rockchip,vdec.yaml | 4 +-
> >>> arch/arm/boot/dts/rockchip/rk3288.dtsi | 17 +-
> >>> arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +-
> >>> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 +-
> >>> drivers/staging/media/rkvdec/Makefile | 2 +-
> >>> drivers/staging/media/rkvdec/TODO | 7 -
> >>> .../staging/media/rkvdec/rkvdec-hevc-data.c | 1848 +++++++++++++++++
> >>> drivers/staging/media/rkvdec/rkvdec-hevc.c | 823 ++++++++
> >>> drivers/staging/media/rkvdec/rkvdec-regs.h | 3 +
> >>> drivers/staging/media/rkvdec/rkvdec-vp9.c | 10 +
> >>> drivers/staging/media/rkvdec/rkvdec.c | 180 +-
> >>> drivers/staging/media/rkvdec/rkvdec.h | 15 +
> >>> 12 files changed, 2886 insertions(+), 31 deletions(-)
> >>> create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc-data.c
> >>> create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c
> >>>
> >>
> >
>
>
Le mercredi 22 novembre 2023 à 16:23 +0100, Hans Verkuil a écrit :
> On 09/11/2023 18:44, Jonas Karlman wrote:
> > Hi Hans,
> >
> > On 2023-11-07 14:49, Hans Verkuil wrote:
> > > Hi Jonas,
> > >
> > > On 06/11/2023 00:36, Jonas Karlman wrote:
> > > > This series add a HEVC backend to the Rockchip Video Decoder driver.
> > > >
> > > > A version of this HEVC backend has been in use by the LibreELEC distro
> > > > for the past 3+ years [1]. It was initially created based on a copy of
> > > > the H264 backend, unstable HEVC uAPI controls and a cabac table + scaling
> > > > matrix functions shamelessly copied 1:1 from the Rockchip mpp library.
> > > >
> > > > It has since then been extended to use the stable HEVC uAPI controls and
> > > > improved opon e.g. to include support for rk3288 and fix decoding issues
> > > > by Alex Bee and Nicolas Dufresne.
> > > >
> > > > The version submitted in this series is based on the code currently used
> > > > by the LibreELEC distro, excluding hard/soft reset, and with cabac table
> > > > and scaling matrix functions picked from Sebastian Fricke prior series
> > > > to add a HEVC backend [2].
> > > >
> > > > Big thanks to Alex Bee, Nicolas Dufresne and Sebastian Fricke for making
> > > > this series possible!
> > >
> > > I ran this series through smatch and found these two issues:
> > >
> > > drivers/staging/media/rkvdec/rkvdec-hevc.c: In function 'transpose_and_flatten_matrices':
> > > drivers/staging/media/rkvdec/rkvdec-hevc.c:429:83: warning: variable 'new_value' set but not used [-Wunused-but-set-variable]
> > > 429 | int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value;
> > > | ^~~~~~~~~
> > > drivers/staging/media/rkvdec/rkvdec-hevc.c:756 rkvdec_hevc_run_preamble() error: we previously assumed 'ctrl' could be null (see line 755)
> >
> > Thanks, will fix in v2.
> >
> > >
> > > Also, this series drops the HEVC part from the TODO file, but
> > > I wonder if the last remaining item is still valid:
> > >
> > > * Evaluate introducing a helper to consolidate duplicated
> > > code in rkvdec_request_validate and cedrus_request_validate.
> > > The helper needs to the driver private data associated with
> > > the videobuf2 queue, from a media request.
> > >
> > > It doesn't look like there is much duplicate code at all. It is certainly not
> > > something that prevents this driver from moving out of staging.
> >
> > I agree, if this is still valid it is not something that should prevent
> > this driver from moving out of staging.
> >
> > There is however one remaining feature/issue that is not listed in TODO.
> >
> > In certain situations the hw block may need a reset after there has been
> > a decoding error, especially after a hevc decoding error. Decoding can
> > typically be re-started with successful result after a short pm
> > autosuspend timeout.
> >
> > We do have a soft/hard reset implementation in LibreELEC-distro,
> > excluded it from this series because reset is typically not needed, and
> > I think the reset code need some rework to be upstream ready.
> >
> > Would missing hard reset support be a reason for keeping this driver
> > in staging?
>
> I think Nicolas would be better placed to comment on that. If it is not
> considered a blocker, shouldn't there at least be a patch adding comments
> at the relevant place describing this issue? That way it is at least
> documented as a known issue.
I *think* that Sebastian have identified how to detect when the self reset is
not sufficient (and I guess the same may exist in LibreELEC tree). As the
failure is not fatal, and it will recover if you let the codec idle for a
little, I don't have any argument to make this a hard blocker.
But before we unstated with this known issue, I'd like to see this well
documented, and ideally see a kernel warning whenever that state is reached.
From there, it will be easy to justify a more invasive change to reset the
entire block. It may also help identify when getting user reports of issues.
Nicolas
>
> Regards,
>
> Hans
>
> >
> > Regards,
> > Jonas
> >
> > >
> > > Regards,
> > >
> > > Hans
> > >
> > > >
> > > > Patch 1 add the new HEVC backend.
> > > > Patch 2-3 add variants support to the driver.
> > > > Patch 4 add support for a rk3288 variant.
> > > > Patch 5 add a rk3328 variant to work around hw quirks.
> > > > Patch 6-7 add device tree node for rk3288.
> > > > Patch 8-9 extend vdec node reg size to include cache/perf registers.
> > > >
> > > > This was tested on a ROCK Pi 4 (RK3399) and Rock64 (RK3328):
> > > >
> > > > v4l2-compliance 1.24.1, 64 bits, 64-bit time_t
> > > > ...
> > > > Total for rkvdec device /dev/video1: 46, Succeeded: 46, Failed: 0, Warnings: 0
> > > >
> > > > Running test suite JCT-VC-HEVC_V1 with decoder FFmpeg-H.265-V4L2-request
> > > > ...
> > > > Ran 135/147 tests successfully
> > > >
> > > > Running test suite JCT-VC-MV-HEVC with decoder FFmpeg-H.265-V4L2-request
> > > > ...
> > > > Ran 9/9 tests successfully
> > > >
> > > > And on a TinkerBoard (RK3288):
> > > >
> > > > v4l2-compliance 1.24.1, 32 bits, 32-bit time_t
> > > > ...
> > > > Total for rkvdec device /dev/video3: 47, Succeeded: 47, Failed: 0, Warnings: 0
> > > >
> > > > Running test suite JCT-VC-HEVC_V1 with decoder FFmpeg-H.265-V4L2-request
> > > > ...
> > > > Ran 137/147 tests successfully
> > > >
> > > > Running test suite JCT-VC-MV-HEVC with decoder FFmpeg-H.265-V4L2-request
> > > > ...
> > > > Ran 9/9 tests successfully
> > > >
> > > > This series depend on the following series:
> > > > - media: rkvdec: Add H.264 High 10 and 4:2:2 profile support [3]
> > > >
> > > > To fully runtime test this series you need above series and ffmpeg
> > > > patches from [4], this series and its depends is also available at [5].
> > > >
> > > > Full summary of fluster run can be found at [6].
> > > >
> > > > [1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/projects/Rockchip/patches/linux/default/linux-2000-v4l2-wip-rkvdec-hevc.patch
> > > > [2] https://lore.kernel.org/linux-media/[email protected]/
> > > > [3] https://lore.kernel.org/linux-media/[email protected]/
> > > > [4] https://github.com/Kwiboo/FFmpeg/commits/v4l2-request-n6.1-dev/
> > > > [5] https://github.com/Kwiboo/linux-rockchip/commits/linuxtv-rkvdec-hevc-v1/
> > > > [6] https://gist.github.com/Kwiboo/4c0ed87774dede44ce6838451a1ec93d
> > > >
> > > > Regards,
> > > > Jonas
> > > >
> > > > Alex Bee (5):
> > > > media: rkvdec: Add variants support
> > > > media: rkvdec: Add RK3288 variant
> > > > media: rkvdec: Disable QoS for HEVC and VP9 on RK3328
> > > > ARM: dts: rockchip: Add vdec node for RK3288
> > > > arm64: dts: rockchip: Expand reg size of vdec node for RK3399
> > > >
> > > > Jonas Karlman (4):
> > > > media: rkvdec: Add HEVC backend
> > > > media: rkvdec: Implement capability filtering
> > > > media: dt-bindings: rockchip,vdec: Add RK3288 compatible
> > > > arm64: dts: rockchip: Expand reg size of vdec node for RK3328
> > > >
> > > > .../bindings/media/rockchip,vdec.yaml | 4 +-
> > > > arch/arm/boot/dts/rockchip/rk3288.dtsi | 17 +-
> > > > arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +-
> > > > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 +-
> > > > drivers/staging/media/rkvdec/Makefile | 2 +-
> > > > drivers/staging/media/rkvdec/TODO | 7 -
> > > > .../staging/media/rkvdec/rkvdec-hevc-data.c | 1848 +++++++++++++++++
> > > > drivers/staging/media/rkvdec/rkvdec-hevc.c | 823 ++++++++
> > > > drivers/staging/media/rkvdec/rkvdec-regs.h | 3 +
> > > > drivers/staging/media/rkvdec/rkvdec-vp9.c | 10 +
> > > > drivers/staging/media/rkvdec/rkvdec.c | 180 +-
> > > > drivers/staging/media/rkvdec/rkvdec.h | 15 +
> > > > 12 files changed, 2886 insertions(+), 31 deletions(-)
> > > > create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc-data.c
> > > > create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c
> > > >
> > >
> >
>
>
Hey Jonas,
thanks a lot for finishing this driver up.
I have tested and reviewed this code, so far it looks sound to me.
Just two small comments below...
On 05.11.2023 23:36, Jonas Karlman wrote:
>The Rockchip VDEC supports the HEVC codec with the Main and Main10
>Profile up to Level 5.1 High tier: 4096x2304@60 fps.
>
>Add the backend for HEVC format to the decoder.
>
>Signed-off-by: Alex Bee <[email protected]>
>Signed-off-by: Nicolas Dufresne <[email protected]>
>Signed-off-by: Sebastian Fricke <[email protected]>
>Signed-off-by: Jonas Karlman <[email protected]>
>---
> drivers/staging/media/rkvdec/Makefile | 2 +-
> drivers/staging/media/rkvdec/TODO | 7 -
> .../staging/media/rkvdec/rkvdec-hevc-data.c | 1848 +++++++++++++++++
> drivers/staging/media/rkvdec/rkvdec-hevc.c | 814 ++++++++
> drivers/staging/media/rkvdec/rkvdec-regs.h | 1 +
> drivers/staging/media/rkvdec/rkvdec.c | 76 +
> drivers/staging/media/rkvdec/rkvdec.h | 1 +
> 7 files changed, 2741 insertions(+), 8 deletions(-)
> create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc-data.c
> create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c
>
>diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile
>index cb86b429cfaa..a77122641d14 100644
>--- a/drivers/staging/media/rkvdec/Makefile
>+++ b/drivers/staging/media/rkvdec/Makefile
>@@ -1,3 +1,3 @@
> obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o
>
>-rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o
>+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o
>diff --git a/drivers/staging/media/rkvdec/TODO b/drivers/staging/media/rkvdec/TODO
>index 2c0779383276..f089ef859e8c 100644
>--- a/drivers/staging/media/rkvdec/TODO
>+++ b/drivers/staging/media/rkvdec/TODO
>@@ -1,10 +1,3 @@
>-* Support for HEVC is planned for this driver.
>-
>- Given the V4L controls for that CODEC will be part of
>- the uABI, it will be required to have the driver in staging.
>-
>- For this reason, we are keeping this driver in staging for now.
>-
> * Evaluate introducing a helper to consolidate duplicated
> code in rkvdec_request_validate and cedrus_request_validate.
> The helper needs to the driver private data associated with
>diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc-data.c b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c
>new file mode 100644
>index 000000000000..eac4ea604949
>--- /dev/null
>+++ b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c
>@@ -0,0 +1,1848 @@
>+// SPDX-License-Identifier: GPL-2.0
>+/*
>+ * Rockchip Video Decoder driver
>+ *
>+ * Copyright (C) 2023 Collabora, Ltd.
>+ * Sebastian Fricke <[email protected]>
>+ */
>+
>+#include <linux/types.h>
>+
>+#define RKV_CABAC_TABLE_SIZE 27456
>+
>+/*
>+ * This file is #include from rkvdec-hevc.c and not compiled.
>+ */
>+static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = {
>+ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f,
>+ 0x68, 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40,
>+ 0x40, 0x68, 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60,
>+ 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50,
>+ 0x48, 0x68, 0x60, 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68,
>+ 0x68, 0x68, 0x50, 0x48, 0x68, 0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60,
>+ 0x50, 0x50, 0x50, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58,
>+ 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50, 0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07,
>+ 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40, 0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40,
>+ 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f, 0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37,
>+ 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
>+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0f, 0x47, 0x57,
>+ 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66, 0x47, 0x40, 0x40,
>+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67, 0x57, 0x5e,
>+ 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57, 0x4f,
>+ 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f,
>+ 0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47,
>+ 0x66, 0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47,
>+ 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37,
>+ 0x07, 0x57, 0x4f, 0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10,
>+ 0x47, 0x67, 0x40, 0x40, 0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27,
>+ 0x4e, 0x47, 0x47, 0x00, 0x0f, 0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07,
>+ 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
>+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0e, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40,
>+ 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x64, 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
>+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x66, 0x57, 0x5d, 0x00, 0x1e, 0x40, 0x40,
>+ 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5e, 0x5e, 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f,
>+ 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x5e, 0x5e, 0x4e, 0x56, 0x4f, 0x07,
>+ 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x45, 0x48, 0x20,
>+ 0x57, 0x66, 0x66, 0x56, 0x5e, 0x5e, 0x5d, 0x4e, 0x4e, 0x4e, 0x46, 0x56, 0x57, 0x36, 0x07,
>+ 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f, 0x47,
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>+ 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07, 0x07, 0x27, 0x2f,
>+ 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f, 0x17, 0x1f,
>+ 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f, 0x0f,
>+ 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27,
>+ 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47,
>+ 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07,
>+ 0x40, 0x4f, 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47,
>+ 0x40, 0x40, 0x40, 0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f,
>+ 0x07, 0x27, 0x1f, 0x1f, 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37,
>+ 0x27, 0x27, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
>+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>+};
>diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
>new file mode 100644
>index 000000000000..0c4ddc073a6c
>--- /dev/null
>+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
>@@ -0,0 +1,814 @@
>+// SPDX-License-Identifier: GPL-2.0
>+/*
>+ * Rockchip Video Decoder HEVC backend
>+ *
As you did a bunch of changes shouldn't your name find its place here?
>+ * Copyright (C) 2023 Collabora, Ltd.
>+ * Sebastian Fricke <[email protected]>
>+ *
>+ * Copyright (C) 2019 Collabora, Ltd.
>+ * Boris Brezillon <[email protected]>
>+ *
>+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
>+ * Jeffy Chen <[email protected]>
>+ */
>+
>+#include <media/v4l2-mem2mem.h>
>+
>+#include "rkvdec.h"
>+#include "rkvdec-regs.h"
>+#include "rkvdec-hevc-data.c"
>+
>+/* Size in u8/u32 units. */
>+#define RKV_SCALING_LIST_SIZE 1360
>+#define RKV_PPS_SIZE (80 / 4)
>+#define RKV_PPS_LEN 64
>+#define RKV_RPS_SIZE (32 / 4)
>+#define RKV_RPS_LEN 600
>+
>+struct rkvdec_sps_pps_packet {
>+ u32 info[RKV_PPS_SIZE];
>+};
>+
>+struct rkvdec_rps_packet {
>+ u32 info[RKV_RPS_SIZE];
>+};
>+
>+struct rkvdec_ps_field {
>+ u16 offset;
>+ u8 len;
>+};
>+
>+#define PS_FIELD(_offset, _len) \
>+ ((struct rkvdec_ps_field){ _offset, _len })
>+
>+/* SPS */
>+#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4)
>+#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4)
>+#define CHROMA_FORMAT_IDC PS_FIELD(8, 2)
>+#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13)
>+#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13)
>+#define BIT_DEPTH_LUMA PS_FIELD(36, 4)
>+#define BIT_DEPTH_CHROMA PS_FIELD(40, 4)
>+#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5)
>+#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2)
>+#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3)
>+#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3)
>+#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2)
>+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3)
>+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3)
>+#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1)
>+#define AMP_ENABLED_FLAG PS_FIELD(66, 1)
>+#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1)
>+#define PCM_ENABLED_FLAG PS_FIELD(68, 1)
>+#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4)
>+#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4)
>+#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1)
>+#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3)
>+#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3)
>+#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7)
>+#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1)
>+#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6)
>+#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1)
>+#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1)
>+/* PPS */
>+#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6)
>+#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4)
>+#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1)
>+#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1)
>+#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13)
>+#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1)
>+#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1)
>+#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4)
>+#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4)
>+#define INIT_QP_MINUS26 PS_FIELD(163, 7)
>+#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1)
>+#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1)
>+#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1)
>+#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3)
>+#define PPS_CB_QP_OFFSET PS_FIELD(176, 5)
>+#define PPS_CR_QP_OFFSET PS_FIELD(181, 5)
>+#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1)
>+#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1)
>+#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1)
>+#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1)
>+#define TILES_ENABLED_FLAG PS_FIELD(190, 1)
>+#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1)
>+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1)
>+#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1)
>+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1)
>+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1)
>+#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4)
>+#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4)
>+#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1)
>+#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3)
>+#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1)
>+#define NUM_TILE_COLUMNS PS_FIELD(212, 5)
>+#define NUM_TILE_ROWS PS_FIELD(217, 5)
>+#define COLUMN_WIDTH(i) PS_FIELD(256 + ((i) * 8), 8)
>+#define ROW_HEIGHT(i) PS_FIELD(416 + ((i) * 8), 8)
>+#define SCALING_LIST_ADDRESS PS_FIELD(592, 32)
>+
>+/* Data structure describing auxiliary buffer format. */
>+struct rkvdec_hevc_priv_tbl {
>+ u8 cabac_table[RKV_CABAC_TABLE_SIZE];
>+ u8 scaling_list[RKV_SCALING_LIST_SIZE];
>+ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN];
>+ struct rkvdec_rps_packet rps[RKV_RPS_LEN];
>+};
>+
>+struct rkvdec_hevc_run {
>+ struct rkvdec_run base;
>+ const struct v4l2_ctrl_hevc_slice_params *slices_params;
>+ const struct v4l2_ctrl_hevc_decode_params *decode_params;
>+ const struct v4l2_ctrl_hevc_sps *sps;
>+ const struct v4l2_ctrl_hevc_pps *pps;
>+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix;
>+ int num_slices;
>+};
>+
>+struct rkvdec_hevc_ctx {
>+ struct rkvdec_aux_buf priv_tbl;
>+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache;
>+};
>+
>+struct scaling_factor {
>+ u8 scalingfactor0[1248];
>+ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/
>+ u8 scalingdc[12]; /*N1005 Vienna Meeting*/
>+ u8 reserved[4]; /*16Bytes align*/
>+};
>+
>+static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value)
>+{
>+ u8 bit = field.offset % 32, word = field.offset / 32;
>+ u64 mask = GENMASK_ULL(bit + field.len - 1, bit);
>+ u64 val = ((u64)value << bit) & mask;
>+
>+ buf[word] &= ~mask;
>+ buf[word] |= val;
>+ if (bit + field.len > 32) {
>+ buf[word + 1] &= ~(mask >> 32);
>+ buf[word + 1] |= val >> 32;
>+ }
>+}
>+
>+static void assemble_hw_pps(struct rkvdec_ctx *ctx,
>+ struct rkvdec_hevc_run *run)
>+{
>+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
>+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
>+ const struct v4l2_ctrl_hevc_pps *pps = run->pps;
>+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
>+ struct rkvdec_sps_pps_packet *hw_ps;
>+ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y;
>+ u32 log2_min_cu_qp_delta_size, scaling_distance;
>+ dma_addr_t scaling_list_address;
>+ int i;
>+
>+ /*
>+ * HW read the SPS/PPS information from PPS packet index by PPS id.
>+ * offset from the base can be calculated by PPS_id * 80 (size per PPS
>+ * packet unit). so the driver copy SPS/PPS information to the exact PPS
>+ * packet unit for HW accessing.
>+ */
>+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
>+ memset(hw_ps, 0, sizeof(*hw_ps));
>+
>+#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
>+ /* write sps */
>+ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID);
>+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
>+ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
>+ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES);
>+ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES);
>+ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
>+ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
>+ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4,
>+ LOG2_MAX_PIC_ORDER_CNT_LSB);
>+ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size,
>+ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE);
>+ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3,
>+ LOG2_MIN_LUMA_CODING_BLOCK_SIZE);
>+ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2,
>+ LOG2_MIN_TRANSFORM_BLOCK_SIZE);
>+ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size,
>+ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE);
>+ WRITE_PPS(sps->max_transform_hierarchy_depth_inter,
>+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER);
>+ WRITE_PPS(sps->max_transform_hierarchy_depth_intra,
>+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA);
>+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED),
>+ SCALING_LIST_ENABLED_FLAG);
>+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED),
>+ AMP_ENABLED_FLAG);
>+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET),
>+ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG);
>+ if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) {
>+ WRITE_PPS(1, PCM_ENABLED_FLAG);
>+ WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1,
>+ PCM_SAMPLE_BIT_DEPTH_LUMA);
>+ WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1,
>+ PCM_SAMPLE_BIT_DEPTH_CHROMA);
>+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED),
>+ PCM_LOOP_FILTER_DISABLED_FLAG);
>+ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size,
>+ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
>+ WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3,
>+ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
>+ }
>+ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS);
>+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT),
>+ LONG_TERM_REF_PICS_PRESENT_FLAG);
>+ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS);
>+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED),
>+ SPS_TEMPORAL_MVP_ENABLED_FLAG);
>+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED),
>+ STRONG_INTRA_SMOOTHING_ENABLED_FLAG);
>+
>+ /* write pps */
>+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
>+ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED),
>+ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT),
>+ OUTPUT_FLAG_PRESENT_FLAG);
>+ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED),
>+ SIGN_DATA_HIDING_ENABLED_FLAG);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT),
>+ CABAC_INIT_PRESENT_FLAG);
>+ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1,
>+ NUM_REF_IDX_L0_DEFAULT_ACTIVE);
>+ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1,
>+ NUM_REF_IDX_L1_DEFAULT_ACTIVE);
>+ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED),
>+ CONSTRAINED_INTRA_PRED_FLAG);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED),
>+ TRANSFORM_SKIP_ENABLED_FLAG);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED),
>+ CU_QP_DELTA_ENABLED_FLAG);
>+
>+ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3;
>+ ctb_log2_size_y = min_cb_log2_size_y +
>+ sps->log2_diff_max_min_luma_coding_block_size;
>+ ctb_size_y = 1 << ctb_log2_size_y;
>+ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth;
>+ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE);
>+ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET);
>+ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT),
>+ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED),
>+ WEIGHTED_PRED_FLAG);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED),
>+ WEIGHTED_BIPRED_FLAG);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED),
>+ TRANSQUANT_BYPASS_ENABLED_FLAG);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED),
>+ TILES_ENABLED_FLAG);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED),
>+ ENTROPY_CODING_SYNC_ENABLED_FLAG);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED),
>+ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED),
>+ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED),
>+ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER),
>+ PPS_DEBLOCKING_FILTER_DISABLED_FLAG);
>+ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2);
>+ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT),
>+ LISTS_MODIFICATION_PRESENT_FLAG);
>+ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL);
>+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT),
>+ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG);
>+ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS);
>+ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS);
>+
>+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) {
>+ /* Userspace also provide column width and row height for uniform spacing */
>+ for (i = 0; i <= pps->num_tile_columns_minus1; i++)
>+ WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i));
>+ for (i = 0; i <= pps->num_tile_rows_minus1; i++)
>+ WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i));
>+ } else {
>+ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1,
>+ COLUMN_WIDTH(0));
>+ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1,
>+ ROW_HEIGHT(0));
>+ }
>+
>+ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list);
>+ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance;
>+ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS);
>+}
>+
>+/*
>+ * Creation of the Reference Picture Set memory blob for the hardware.
>+ * The layout looks like this:
>+ * [0] 32 bits for L0 (6 references + 2 bits of the 7th reference)
>+ * [1] 32 bits for L0 (remaining 3 bits of the 7th reference + 5 references
>+ * + 4 bits of the 13th reference)
>+ * [2] 11 bits for L0 (remaining bit for 13 and 2 references) and
>+ * 21 bits for L1 (4 references + first bit of 5)
>+ * [3] 32 bits of padding with 0s
>+ * [4] 32 bits for L1 (remaining 4 bits for 5 + 5 references + 3 bits of 11)
>+ * [5] 22 bits for L1 (remaining 2 bits of 11 and 4 references)
>+ * lowdelay flag (bit 23), rps bit offset long term (bit 24 - 32)
>+ * [6] rps bit offset long term (bit 1 - 3), rps bit offset short term (bit 4 - 12)
>+ * number of references (bit 13 - 16), remaining 16 bits of padding with 0s
>+ * [7] 32 bits of padding with 0s
>+ *
>+ * Thus we have to set up padding in between reference 5 of the L1 list.
>+ */
>+static void assemble_hw_rps(struct rkvdec_ctx *ctx,
>+ struct rkvdec_hevc_run *run)
>+{
>+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
>+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
>+ const struct v4l2_ctrl_hevc_slice_params *sl_params;
>+ const struct v4l2_hevc_dpb_entry *dpb;
>+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
>+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
>+ struct rkvdec_rps_packet *hw_ps;
>+ int i, j;
>+ unsigned int lowdelay;
>+
>+#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value)
>+
>+#define REF_PIC_LONG_TERM_L0(i) PS_FIELD((i) * 5, 1)
>+#define REF_PIC_IDX_L0(i) PS_FIELD(1 + ((i) * 5), 4)
>+#define REF_PIC_LONG_TERM_L1(i) PS_FIELD(((i) < 5 ? 75 : 132) + ((i) * 5), 1)
>+#define REF_PIC_IDX_L1(i) PS_FIELD(((i) < 4 ? 76 : 128) + ((i) * 5), 4)
>+
>+#define LOWDELAY PS_FIELD(182, 1)
>+#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10)
>+#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9)
>+#define NUM_RPS_POC PS_FIELD(202, 4)
>+
>+ for (j = 0; j < run->num_slices; j++) {
>+ uint st_bit_offset = 0;
>+ uint num_l0_refs = 0;
>+ uint num_l1_refs = 0;
>+
>+ sl_params = &run->slices_params[j];
>+ dpb = decode_params->dpb;
>+
>+ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) {
>+ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1;
>+
>+ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B)
>+ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1;
>+
>+ lowdelay = 1;
>+ } else {
>+ lowdelay = 0;
>+ }
>+
>+ hw_ps = &priv_tbl->rps[j];
>+ memset(hw_ps, 0, sizeof(*hw_ps));
>+
>+ for (i = 0; i < num_l0_refs; i++) {
>+ const struct v4l2_hevc_dpb_entry dpb_l0 = dpb[sl_params->ref_idx_l0[i]];
>+
>+ WRITE_RPS(!!(dpb_l0.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
>+ REF_PIC_LONG_TERM_L0(i));
>+ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
>+
>+ if (dpb_l0.pic_order_cnt_val > sl_params->slice_pic_order_cnt)
>+ lowdelay = 0;
>+ }
>+
>+ for (i = 0; i < num_l1_refs; i++) {
>+ const struct v4l2_hevc_dpb_entry dpb_l1 = dpb[sl_params->ref_idx_l1[i]];
>+ int is_long_term =
>+ !!(dpb_l1.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE);
>+
>+ WRITE_RPS(is_long_term, REF_PIC_LONG_TERM_L1(i));
>+ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
>+
>+ if (dpb_l1.pic_order_cnt_val > sl_params->slice_pic_order_cnt)
>+ lowdelay = 0;
>+ }
>+
>+ WRITE_RPS(lowdelay, LOWDELAY);
>+
>+ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) {
>+ if (sl_params->short_term_ref_pic_set_size)
>+ st_bit_offset = sl_params->short_term_ref_pic_set_size;
>+ else if (sps->num_short_term_ref_pic_sets > 1)
>+ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1);
>+ }
>+
>+ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size,
>+ LONG_TERM_RPS_BIT_OFFSET);
>+ WRITE_RPS(sl_params->short_term_ref_pic_set_size,
>+ SHORT_TERM_RPS_BIT_OFFSET);
>+
>+ WRITE_RPS(decode_params->num_poc_st_curr_before +
>+ decode_params->num_poc_st_curr_after +
>+ decode_params->num_poc_lt_curr,
>+ NUM_RPS_POC);
>+ }
>+}
>+
>+/*
>+ * Flip one or more matrices along their main diagonal and flatten them
>+ * before writing it to the memory.
>+ * Convert:
>+ * ABCD AEIM
>+ * EFGH => BFJN => AEIMBFJNCGKODHLP
>+ * IJKL CGKO
>+ * MNOP DHLP
>+ */
>+static void transpose_and_flatten_matrices(u8 *output, const u8 *input,
>+ int matrices, int row_length)
>+{
>+ int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value;
>+
>+ matrix_size = row_length * row_length;
>+ for (i = 0; i < matrices; i++) {
>+ row = 0;
>+ x_offset = 0;
>+ matrix_offset = i * matrix_size;
>+ for (j = 0; j < matrix_size; j++) {
>+ y_offset = j - (row * row_length);
>+ rot_index = y_offset * row_length + x_offset;
>+ new_value = *(input + i * matrix_size + j);
>+ output[matrix_offset + rot_index] = *(input + i * matrix_size + j);
>+ if ((j + 1) % row_length == 0) {
>+ row += 1;
>+ x_offset += 1;
>+ }
>+ }
>+ }
>+}
>+
>+static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input)
>+{
>+ int offset = 0;
>+
>+ transpose_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4);
>+ offset = 6 * 16 * sizeof(u8);
>+ transpose_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8);
>+ offset += 6 * 64 * sizeof(u8);
>+ transpose_and_flatten_matrices(output + offset,
>+ (const u8 *)input->scaling_list_16x16, 6, 8);
>+ offset += 6 * 64 * sizeof(u8);
>+ /* Add a 128 byte padding with 0s between the two 32x32 matrices */
>+ transpose_and_flatten_matrices(output + offset,
>+ (const u8 *)input->scaling_list_32x32, 1, 8);
>+ offset += 64 * sizeof(u8);
>+ memset(output + offset, 0, 128);
>+ offset += 128 * sizeof(u8);
>+ transpose_and_flatten_matrices(output + offset,
>+ (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)),
>+ 1, 8);
>+ offset += 64 * sizeof(u8);
>+ memset(output + offset, 0, 128);
>+}
>+
>+/*
>+ * Required layout:
>+ * A = scaling_list_dc_coef_16x16
>+ * B = scaling_list_dc_coef_32x32
>+ * 0 = Padding
>+ *
>+ * A, A, A, A, A, A, B, 0, 0, B, 0, 0
>+ */
>+static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input)
>+{
>+ u8 list_32x32[6] = {0};
>+
>+ memcpy(output, input->scaling_list_dc_coef_16x16, 6 * sizeof(u8));
>+ list_32x32[0] = input->scaling_list_dc_coef_32x32[0];
>+ list_32x32[3] = input->scaling_list_dc_coef_32x32[1];
>+ memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8));
>+}
>+
>+static void translate_scaling_list(struct scaling_factor *output,
>+ const struct v4l2_ctrl_hevc_scaling_matrix *input)
>+{
>+ assemble_scalingfactor0(output->scalingfactor0, input);
>+ memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96);
>+ assemble_scalingdc(output->scalingdc, input);
>+ memset(output->reserved, 0, 4 * sizeof(u8));
>+}
>+
>+static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx,
>+ struct rkvdec_hevc_run *run)
>+{
>+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix;
>+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
>+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu;
>+ u8 *dst;
>+
>+ if (!memcmp((void *)&hevc_ctx->scaling_matrix_cache, scaling,
>+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)))
>+ return;
>+
>+ dst = tbl->scaling_list;
>+ translate_scaling_list((struct scaling_factor *)dst, scaling);
>+
>+ memcpy((void *)&hevc_ctx->scaling_matrix_cache, scaling,
>+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix));
>+}
>+
>+static struct vb2_buffer *
>+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run,
>+ unsigned int dpb_idx)
>+{
>+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
>+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
>+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
>+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q;
>+ struct vb2_buffer *buf = NULL;
>+
>+ if (dpb_idx < decode_params->num_active_dpb_entries)
>+ buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp);
>+
>+ /*
>+ * If a DPB entry is unused or invalid, the address of current destination
>+ * buffer is returned.
>+ */
>+ if (!buf)
>+ return &run->base.bufs.dst->vb2_buf;
>+
>+ return buf;
>+}
>+
>+static void config_registers(struct rkvdec_ctx *ctx,
>+ struct rkvdec_hevc_run *run)
>+{
>+ struct rkvdec_dev *rkvdec = ctx->dev;
>+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
>+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
>+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
>+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
>+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
>+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma;
>+ const struct v4l2_pix_format_mplane *dst_fmt;
>+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
>+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
>+ const struct v4l2_format *f;
>+ dma_addr_t rlc_addr;
>+ dma_addr_t refer_addr;
>+ u32 rlc_len;
>+ u32 hor_virstride;
>+ u32 ver_virstride;
>+ u32 y_virstride;
>+ u32 yuv_virstride = 0;
>+ u32 offset;
>+ dma_addr_t dst_addr;
>+ u32 reg, i;
>+
>+ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC);
>+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL);
>+
>+ f = &ctx->decoded_fmt;
>+ dst_fmt = &f->fmt.pix_mp;
>+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
>+ ver_virstride = dst_fmt->height;
>+ y_virstride = hor_virstride * ver_virstride;
>+
>+ if (sps->chroma_format_idc == 0)
>+ yuv_virstride = y_virstride;
>+ else if (sps->chroma_format_idc == 1)
>+ yuv_virstride = y_virstride + y_virstride / 2;
>+ else if (sps->chroma_format_idc == 2)
>+ yuv_virstride = 2 * y_virstride;
I think that adding a comment here to indicate what chromat format idc
1,2 & 3 mean in terms of subsampling, might be helpful for readability
of the code, to understand better why those calculations are used.
Greetings,
Sebastian
>+
>+ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) |
>+ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) |
>+ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices);
>+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR);
>+
>+ /* config rlc base address */
>+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
>+ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
>+
>+ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
>+ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64);
>+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN);
>+
>+ /* config cabac table */
>+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table);
>+ writel_relaxed(priv_start_addr + offset,
>+ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE);
>+
>+ /* config output base address */
>+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
>+ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
>+
>+ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16);
>+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
>+
>+ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16);
>+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
>+
>+ /* config ref pic address */
>+ for (i = 0; i < 15; i++) {
>+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i);
>+
>+ if (i < 4 && decode_params->num_active_dpb_entries) {
>+ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0);
>+ reg = (reg >> (i * 4)) & 0xf;
>+ } else {
>+ reg = 0;
>+ }
>+
>+ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
>+ writel_relaxed(refer_addr | reg,
>+ rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i));
>+
>+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ?
>+ dpb[i].pic_order_cnt_val : 0);
>+ writel_relaxed(reg,
>+ rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i));
>+ }
>+
>+ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt);
>+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0);
>+
>+ /* config hw pps address */
>+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set);
>+ writel_relaxed(priv_start_addr + offset,
>+ rkvdec->regs + RKVDEC_REG_PPS_BASE);
>+
>+ /* config hw rps address */
>+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps);
>+ writel_relaxed(priv_start_addr + offset,
>+ rkvdec->regs + RKVDEC_REG_RPS_BASE);
>+
>+ reg = RKVDEC_AXI_DDR_RDATA(0);
>+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA);
>+
>+ reg = RKVDEC_AXI_DDR_WDATA(0);
>+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA);
>+}
>+
>+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2
>+
>+static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx,
>+ struct v4l2_format *f)
>+{
>+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp;
>+
>+ fmt->num_planes = 1;
>+ if (!fmt->plane_fmt[0].sizeimage)
>+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height *
>+ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES;
>+ return 0;
>+}
>+
>+static enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx,
>+ struct v4l2_ctrl *ctrl)
>+{
>+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
>+
>+ if (ctrl->id != V4L2_CID_STATELESS_HEVC_SPS)
>+ return RKVDEC_IMG_FMT_ANY;
>+
>+ if (sps->bit_depth_luma_minus8 == 0) {
>+ if (sps->chroma_format_idc == 2)
>+ return RKVDEC_IMG_FMT_422_8BIT;
>+ else
>+ return RKVDEC_IMG_FMT_420_8BIT;
>+ } else if (sps->bit_depth_luma_minus8 == 2) {
>+ if (sps->chroma_format_idc == 2)
>+ return RKVDEC_IMG_FMT_422_10BIT;
>+ else
>+ return RKVDEC_IMG_FMT_420_10BIT;
>+ }
>+
>+ return RKVDEC_IMG_FMT_ANY;
>+}
>+
>+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx,
>+ const struct v4l2_ctrl_hevc_sps *sps)
>+{
>+ if (sps->chroma_format_idc > 1)
>+ /* Only 4:0:0 and 4:2:0 are supported */
>+ return -EINVAL;
>+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
>+ /* Luma and chroma bit depth mismatch */
>+ return -EINVAL;
>+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
>+ /* Only 8-bit and 10-bit is supported */
>+ return -EINVAL;
>+
>+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width ||
>+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height)
>+ return -EINVAL;
>+
>+ return 0;
>+}
>+
>+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
>+{
>+ struct rkvdec_dev *rkvdec = ctx->dev;
>+ struct rkvdec_hevc_priv_tbl *priv_tbl;
>+ struct rkvdec_hevc_ctx *hevc_ctx;
>+
>+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL);
>+ if (!hevc_ctx)
>+ return -ENOMEM;
>+
>+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
>+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL);
>+ if (!priv_tbl) {
>+ kfree(hevc_ctx);
>+ return -ENOMEM;
>+ }
>+
>+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl);
>+ hevc_ctx->priv_tbl.cpu = priv_tbl;
>+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table,
>+ sizeof(rkvdec_hevc_cabac_table));
>+
>+ ctx->priv = hevc_ctx;
>+ return 0;
>+}
>+
>+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx)
>+{
>+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
>+ struct rkvdec_dev *rkvdec = ctx->dev;
>+
>+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size,
>+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma);
>+ kfree(hevc_ctx);
>+}
>+
>+static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx,
>+ struct rkvdec_hevc_run *run)
>+{
>+ struct v4l2_ctrl *ctrl;
>+
>+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
>+ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS);
>+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL;
>+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
>+ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS);
>+ run->slices_params = ctrl ? ctrl->p_cur.p : NULL;
>+ run->num_slices = ctrl->new_elems;
>+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
>+ V4L2_CID_STATELESS_HEVC_SPS);
>+ run->sps = ctrl ? ctrl->p_cur.p : NULL;
>+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
>+ V4L2_CID_STATELESS_HEVC_PPS);
>+ run->pps = ctrl ? ctrl->p_cur.p : NULL;
>+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl,
>+ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX);
>+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL;
>+
>+ rkvdec_run_preamble(ctx, &run->base);
>+}
>+
>+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
>+{
>+ struct rkvdec_dev *rkvdec = ctx->dev;
>+ struct rkvdec_hevc_run run;
>+
>+ rkvdec_hevc_run_preamble(ctx, &run);
>+
>+ assemble_hw_scaling_list(ctx, &run);
>+ assemble_hw_pps(ctx, &run);
>+ assemble_hw_rps(ctx, &run);
>+ config_registers(ctx, &run);
>+
>+ rkvdec_run_postamble(ctx, &run.base);
>+
>+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000));
>+
>+ writel(0, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN);
>+ writel(0, rkvdec->regs + RKVDEC_REG_H264_ERR_E);
>+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
>+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
>+
>+ /* Start decoding! */
>+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
>+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
>+ rkvdec->regs + RKVDEC_REG_INTERRUPT);
>+
>+ return 0;
>+}
>+
>+static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
>+{
>+ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS)
>+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps);
>+
>+ return 0;
>+}
>+
>+const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = {
>+ .adjust_fmt = rkvdec_hevc_adjust_fmt,
>+ .start = rkvdec_hevc_start,
>+ .stop = rkvdec_hevc_stop,
>+ .run = rkvdec_hevc_run,
>+ .try_ctrl = rkvdec_hevc_try_ctrl,
>+ .get_image_fmt = rkvdec_hevc_get_image_fmt,
>+};
>diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
>index 15b9bee92016..83bf790ed9b7 100644
>--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
>+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
>@@ -43,6 +43,7 @@
> #define RKVDEC_RLC_MODE BIT(11)
> #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12)
> #define RKVDEC_MODE(x) (((x) & 0x03) << 20)
>+#define RKVDEC_MODE_HEVC 0
> #define RKVDEC_MODE_H264 1
> #define RKVDEC_MODE_VP9 2
> #define RKVDEC_RPS_MODE BIT(24)
>diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
>index eb59605ccf28..eec68a7a1c95 100644
>--- a/drivers/staging/media/rkvdec/rkvdec.c
>+++ b/drivers/staging/media/rkvdec/rkvdec.c
>@@ -164,6 +164,67 @@ static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = {
> .s_ctrl = rkvdec_s_ctrl,
> };
>
>+static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = {
>+ {
>+ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS,
>+ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY,
>+ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS,
>+ .cfg.dims = { 600 },
>+ },
>+ {
>+ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS,
>+ .cfg.ops = &rkvdec_ctrl_ops,
>+ },
>+ {
>+ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS,
>+ },
>+ {
>+ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
>+ },
>+ {
>+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
>+ },
>+ {
>+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
>+ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
>+ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
>+ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
>+ },
>+ {
>+ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE,
>+ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
>+ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
>+ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
>+ },
>+ {
>+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
>+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
>+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
>+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
>+ },
>+ {
>+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
>+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
>+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
>+ },
>+};
>+
>+static const struct rkvdec_ctrls rkvdec_hevc_ctrls = {
>+ .ctrls = rkvdec_hevc_ctrl_descs,
>+ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs),
>+};
>+
>+static const struct rkvdec_decoded_fmt_desc rkvdec_hevc_decoded_fmts[] = {
>+ {
>+ .fourcc = V4L2_PIX_FMT_NV12,
>+ .image_fmt = RKVDEC_IMG_FMT_420_8BIT,
>+ },
>+ {
>+ .fourcc = V4L2_PIX_FMT_NV15,
>+ .image_fmt = RKVDEC_IMG_FMT_420_10BIT,
>+ },
>+};
>+
> static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
> {
> .cfg.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
>@@ -257,6 +318,21 @@ static const struct rkvdec_decoded_fmt_desc rkvdec_vp9_decoded_fmts[] = {
> };
>
> static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
>+ {
>+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
>+ .frmsize = {
>+ .min_width = 64,
>+ .max_width = 4096,
>+ .step_width = 64,
>+ .min_height = 64,
>+ .max_height = 2304,
>+ .step_height = 16,
>+ },
>+ .ctrls = &rkvdec_hevc_ctrls,
>+ .ops = &rkvdec_hevc_fmt_ops,
>+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
>+ .decoded_fmts = rkvdec_hevc_decoded_fmts,
>+ },
> {
> .fourcc = V4L2_PIX_FMT_H264_SLICE,
> .frmsize = {
>diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
>index 9a9f4fced7a1..2f3bda1df5f0 100644
>--- a/drivers/staging/media/rkvdec/rkvdec.h
>+++ b/drivers/staging/media/rkvdec/rkvdec.h
>@@ -138,6 +138,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
> void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
>
> extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops;
>+extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops;
> extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops;
>
> #endif /* RKVDEC_H_ */
>--
>2.42.0
>