2021-08-06 15:12:26

by Michal Simek

Subject: [PATCH] arm64: zynqmp: Enable gpio and qspi for zc1275-revA

Add missing gpio and qspio for zc1275-revA board.

Signed-off-by: Michal Simek <[email protected]>
---

.../boot/dts/xilinx/zynqmp-zc1275-revA.dts | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
index 66a90483b004..e971ba8c1418 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1275
*
- * (C) Copyright 2017 - 2019, Xilinx, Inc.
+ * (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <[email protected]>
* Siva Durga Prasad Paladugu <[email protected]>
@@ -20,6 +20,7 @@ / {
aliases {
serial0 = &uart0;
serial1 = &dcc;
+ spi0 = &qspi;
};

chosen {
@@ -37,6 +38,21 @@ &dcc {
status = "okay";
};

+&gpio {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ };
+};
+
&uart0 {
status = "okay";
};
--
2.32.0

2021-08-25 06:25:21

by Michal Simek

Subject: Re: [PATCH] arm64: zynqmp: Enable gpio and qspi for zc1275-revA

pá 6. 8. 2021 v 12:05 odesílatel Michal Simek <[email protected]> napsal:
>
> Add missing gpio and qspio for zc1275-revA board.
>
> Signed-off-by: Michal Simek <[email protected]>
> ---
>
> .../boot/dts/xilinx/zynqmp-zc1275-revA.dts | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
> index 66a90483b004..e971ba8c1418 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
> @@ -2,7 +2,7 @@
> /*
> * dts file for Xilinx ZynqMP ZC1275
> *
> - * (C) Copyright 2017 - 2019, Xilinx, Inc.
> + * (C) Copyright 2017 - 2021, Xilinx, Inc.
> *
> * Michal Simek <[email protected]>
> * Siva Durga Prasad Paladugu <[email protected]>
> @@ -20,6 +20,7 @@ / {
> aliases {
> serial0 = &uart0;
> serial1 = &dcc;
> + spi0 = &qspi;
> };
>
> chosen {
> @@ -37,6 +38,21 @@ &dcc {
> status = "okay";
> };
>
> +&gpio {
> + status = "okay";
> +};
> +
> +&qspi {
> + status = "okay";
> + flash@0 {
> + compatible = "m25p80", "jedec,spi-nor";
> + reg = <0x0>;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <4>;
> + spi-max-frequency = <108000000>;
> + };
> +};
> +
> &uart0 {
> status = "okay";
> };
> --
> 2.32.0
>

Applied.
M

--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: http://www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs